JPH0526380B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a communication control device that controls a plurality of data communication lines having different speeds.

<Prior Art> A conventional device of this type is provided with a serial-to-parallel conversion circuit corresponding to the line, which converts bit serial data on the line into parallel data (characters) handled within the communication control device. Each time a character is received or transmitted, the serial/parallel conversion circuit outputs a one character reception indication or a next transmission character request indication (processing request), thereby controlling the control within the communication control device. The circuit is
If one character is received, one character is read from the serial/parallel conversion circuit and transferred to the memory, and if the next transmission character is requested, the next transmission data to be sent is read from the memory and written to the serial/parallel conversion circuit. . By repeating this operation, data can be transmitted and received correctly with the data communication line.

By the way, when controlling data communication lines with multiple different communication speeds, the output interval of single character reception display or transmission character request display from the serial-to-parallel converter circuit is shorter for high-speed lines than for low-speed lines. , the control circuit must frequently check the processing requirements of the high-speed line serial-to-parallel conversion circuit. This method of checking processing requests includes an interrupt method in which when a processing request occurs in the serial-to-parallel conversion circuit, an interrupt is sent to the control circuit, and the control circuit checks whether or not there is a processing request for the serial-to-parallel conversion circuit for all lines at regular intervals. There is a scanning method that checks each individual item. Since the present invention relates to a processing request check based on a scanning method, a description of the interrupt method will be omitted hereinafter.

When checking the processing request using the scanning method, the line speed is, for example, 9600 bits per second (9600bps) and 1200 bits per second (1200bps).
In a device that uses a mixture of lines, it is necessary to check whether there is a processing request for the serial/parallel converter circuit for a 9600 bps line at a rate eight times faster than for a 1200 bps line. As a conventional method for accommodating high-speed lines, there is a method (scanning restriction method) that limits the number of accommodated lines. For example, in a communication control device that has the capacity to accommodate 64 lines at 1200 bps, when accommodating a 9600 bps line, it is necessary to check the 9600 bps line at a speed eight times faster than the 1200 bps line. 8) can be accommodated only in the line numbers (for example, numbers 0 to 7). In this case, even if only one 9600bps line was accommodated, the control circuit had the disadvantage that it could only accommodate the remaining seven lines, even though it had the capacity to handle 56 other 1200bps lines.

As a method for solving this drawback, there is an address replacement method in which when a certain line number comes in the scanning order, that line number is converted to a number for a high-speed line. For example, when one 9600bps line is accommodated in line 0, 8j of the line numbers 1 to 63 is used.
When the scanning order reaches number (j=1 to 7), that number is replaced with number 0. In this method, if only one 9600bps line is accommodated, 7 out of 64 lines (8, 16, 24, 32,
40, 48, 56), and when accommodating two lines of 9600 bps, 14 lines, 8j and 8j+1 (j = 1 to 7), become unusable. In this way, in the address substitution method, there is a gap in usable line numbers.

By the way, printed circuit boards (line adapters) that accommodate serial-to-parallel converter circuits and direct line interfaces generally accommodate 2, 4, or 8 lines per board, and the line numbers in the line adapter are the same as those of the line adapter. Normally, consecutive numbers are assigned due to the circuit configuration. Therefore, the address replacement method has the disadvantage that the serial/parallel converter circuit, etc. in the line adapter corresponding to the line number where the line number has been left out is not used, resulting in poor usage efficiency. Another disadvantage is that the conversion circuit for address substitution corresponding to the number of high-speed lines accommodated or the type of high-speed line becomes complicated, and increasing the number of address substitution modes significantly increases the amount of hardware. Furthermore, if the address replacement formula is created using wiring logic, there is a drawback that if it becomes necessary to change the address replacement formula, the circuit must be redesigned. Some conventional communication control devices are capable of setting multiple scanning patterns by combining the above two methods.
It didn't really solve the problem.

<Summary of the Invention> The purpose of the present invention is to fully utilize the processing capacity of a control circuit, prevent line numbers from being dropped midway through, use lines with consecutive numbers, and improve the efficiency of line adapter usage. It is an object of the present invention to provide a communication control device capable of configuring address replacement corresponding to the number of high-speed lines accommodated and the speed type with simple hardware.

According to this invention, information indicating the type of address conversion is input and held in the register from an external circuit, and the storage section is read out using the output of this register and the output of the binary counter as an address. A scanning line number is stored, and it is checked whether or not there is a processing request for the serial/parallel conversion circuit of the read output number, the binary counter is incremented by an update instruction, and one of the outputs of the storage section 1 bit is used as an initialization instruction for the binary counter.

The scanning circuit number is set so that all data communication lines are scanned uniformly when the ^speeds of all data communication lines are equal.
When the lowest ^bit of the output signal from the binary counter is ⁰ , when a low-speed line with a speed of , the high-speed line is set to scan the low-speed line in order when it is 1.

<Embodiment> FIG. 1 shows an embodiment of the present invention, in which a host device 1
A communication control device 2 is connected to the control circuit 20 in the communication control device 2, and a scanning mode holding register 21 and a 6-bit binary counter 22 are connected to the control circuit 20. The binary counter 22 receives a reset signal from the control circuit 20 through a reset signal line 23. can be applied to the reset input terminal 24 of the binary counter 22, and the control circuit 20 can provide a counter update signal to the binary counter 22 over line 25. The scanning number storage section 26 is a read-only or write-readable memory that stores scanning line numbers for each address conversion type, and the outputs of the register 21 and the binary counter 22 are read out as the address input 261. Storage section 26
Scan number 262 is output from. The write data signal line and address signal line from the control circuit 20, which are necessary when applying a write/read memory to the storage section 26, are omitted. The lower 2 bits of the scan number 262 that have been read out and the address for 4 lines of the serial/parallel conversion circuit 301 are supplied to the address signal line 27, and the bits of the scan number 262 other than the lower 2 bits and the upper 1 bit are as follows. It is supplied to the decoding circuit 28 for distinguishing the line adapter 30, and the top 1 of the scanning number 262 is
The bit is provided to the reset input terminal 24 of the binary counter 22 via a reset signal line 29. Line adapters 30 ₁ to 30 ₈ each accommodate serial-to-parallel conversion circuits 301 ₀ to 301 ₃ for four lines,
Processing request indications from each serial-parallel conversion circuit 301 are supplied to the control circuit 20 through the data bus signal line 31. Further, a decoder 302 for serial/parallel conversion circuit is provided in each of the line adapters 30 ₁ to 30 ₈ to decode the address of the signal line 27 .

FIG. 2 shows the type of scanning mode, its code (set in the register 21), the line number accommodated (scanning target), the line speed that can be accommodated, the number of lines accommodated, and the scanning number generation formula to be set in the scanning number storage section 26. show.
In this embodiment, four scanning modes are provided.
The scanning number generation formula is the output of the binary counter 22.
Indicates the data stored in the storage unit 26 when X ₄ , X ₃ , X ₂ , X ₁ , and X ₀ are the addresses of the storage unit 26,
_X0 is the least significant bit (LSB). The scan mode code is set in the scan mode holding register 21. When accommodating only 1200bps lines, the number of lines that can be accommodated is 32, so when accommodating 4 lines of 4800bps, one 4800bps line requires 4 lines of 1200bps, so the number of lines that can accommodate 1200bps lines. becomes 32-4×4=16.

FIG. 3 shows an example of the storage contents of the scanning number storage unit 26, where the 6th bit of the output (higher 1 bit) is reset instruction information to the binary counter 22, and output bits 5 to 1 indicate the scanning line number. . In mode 0, the outputs of the binary counter 22 are X ₅ , X ₄ , X ₃ ,
The lower order X ₄ , X _{3 , X 2 ,} X ₁ , and X ₀ among X ₂ , X ₁ , and X ₀ are stored as they are, and 32 line scanning numbers are assigned. In mode 1, a scanning number for a 4800 bps line is assigned to X ₂ and X ₁ when X ₀ =0. That is, for addresses 0, 2, 4, and 6, values 00, 01, 10, and 11 indicating respective X ₂ and X ₁ are stored. Similar numbers are stored for the following addresses 8, 10, 12, and 14, respectively. In other words
The scanning numbers of the 4800bps line are 0, 1, 2, and 3.
Every time a line is assigned and the address advances by 8,
The same line number of the 4800bps line is read out, so
The same line number is read out at 32/8=4 times the speed of a 1200bps line. On the other hand, for a 1200 bps line, when the address is X ₀ = 1, the addresses X ₄ , X ₃ ,
The scan number is 0100 added to X ₂ and X ₁ , so 4= for addresses 1, 3, 5...
00100, 5=00101, 6=00110, . . . are the scanning numbers, respectively. In other words, 16 lines with scan numbers 4 to 19 are allocated to a 1200 bps line. The storage unit 26 is used by being divided into four memory areas corresponding to four scanning modes. FIG. 4 is a map of the scan number storage section, and the contents of FIG. 3 are set in the respective corresponding areas of FIG.

An example of operation is as follows. When the control circuit 20 is instructed to select a scanning mode (for example, mode 1) from the host device 1 (one of the four types of scanning modes provided by the communication control device 2 is selected), the control circuit 20 starts scanning. The mode holding register 21 is set to "01" and the binary counter 22 is cleared through the reset signal line 23. Then, the binary counter 22 outputs all 0s, so the address input 261 of the scanning number storage section 26 becomes "01000000". When the control circuit 20 issues an input command to read the processing request display of the serial/parallel conversion circuit 301, the contents of the storage section 26 corresponding to the address "01000000" are all 0s as shown in FIG. 3, and the output 262 of the storage section 26 Since all 0s are output, the decoder circuits 28 and 302 output the serial/parallel converter circuit 3 of the line adapter 30 ₁ corresponding to line 0.
01 ₀ is selected, and the processing request display information of the serial/parallel conversion circuit 301 ₀ is read into the control circuit 20 via the bus line 31.

The control circuit 20 checks the read processing request display, and if, for example, the one-character reception display is significant, the control circuit 20 issues an input command to read the received data, thereby changing the selected serial/parallel conversion circuit 3 in the same manner as described above.
Received data can be read from 01 ₀ . The control circuit 20 sends the received data to the host device and finishes the scanning process for the line. Next, the control circuit 20 outputs a counter update signal to the line 25, updates the binary counter 22 (+1), and moves on to the scanning process for the next line. As a result of checking the read processing request display, if there is no processing request, the scanning processing for the line in question is terminated.

By updating the binary counter 22,
Address input 261 of storage unit 26 is “01000001”
and the corresponding content “000100” from the storage unit 26
is output. When the control circuit 20 issues an input command to display a processing request, line No. 4 is selected this time through the same route as above, and the contents of the corresponding serial-to-parallel conversion circuit are read.

As a result of sequentially updating the binary counter 22 as described above, bit 6 of the scan number storage section 26 output
is “1”, the reset signal line 29 of the binary counter 22 becomes significant, and bit 6 becomes “1”.
When the control circuit 20 issues an instruction to update the binary counter after scanning the line number output from the storage unit 26, the binary counter 22 is cleared, so scanning restarts from line 0. Thereafter, the above process is repeated. The same applies when other scanning modes are set.

In this example, a 4800 bps line and a 1200 bps line are mixedly accommodated, but even if any line speed is mixed, the capacity of the communication control device can be used without wasting the capacity to accommodate the maximum number of lines. . Furthermore, by making the scan number storage section 26 a readable/writable memory (RAM), the user can arbitrarily set the speed mixing conditions of this communication control device within the range of processing capability. In the above description, high-speed lines are assigned starting from number 0, but any scanning number may be assigned; however, it is easier to generate scanning numbers by doing as shown in FIG.

<Effects> As explained above, by applying the storage unit 26 to the location where the scanning line number is generated, flexibility in generating the scanning line number is increased, so that the scanning number can be stored in a communication control device that accommodates a mixture of different speed lines. It has the advantage that consecutive numbers can be used without dropping numbers from 0 onwards, line accommodation efficiency can be improved, and the hardware is simple.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing types of scanning modes and examples of scanning number generation formulas, and FIG. 3 is a scanning number storage corresponding to the scanning mode shown in FIG. Diagram showing the contents of section 26, No. 4
The figure shows a map of the storage section 26. 1: Host device, 2: Communication control device, 20: Control circuit, 21: Scanning mode holding register, 22: Binary counter, 23: Reset signal line, 24:
Reset input, 25: Binary counter update signal, 26: Scanning number storage section, 261: Address input terminal, 262: Output of 26, 27: Address signal line of serial/parallel conversion circuit, 28: Line adapter decoding circuit, 29 : reset signal line, 30: line adapter ( ₃₀₁ to ₃₀₈ ), 301: serial/parallel conversion circuit ( ₃₀₁₀ to ₃₀₁₃ ), 302: decoding circuit.

Claims (1)

[Claims] 1. In a communication control device that detects the presence or absence of a processing request from a serial/parallel conversion circuit provided for each of a plurality of data communication lines by scanning each line, information indicating the address conversion type input from an external circuit is retained. A register, a binary counter that is incremented by an update instruction and cleared by an initialization instruction, and a scanning line number for each type of address conversion are stored.The output of the register is used as the upper bit of the address, and the output of the binary counter is used as the lower address. a storage section that outputs the number of the serial/parallel conversion circuit to be scanned as a bit, and uses one bit of the output as an initialization instruction for the binary counter; When the speed of all data communication circuits is equal, the scanning line number is set so that all lines are scanned uniformly.
When the circuit consists of 2 ^m low-speed lines (m is a natural number) and 2 ^mn high-speed lines with a speed 2 ⁿ times faster (n is a natural number and n≦m), the least significant bit of the output signal from the binary counter is A communication control device characterized in that the communication control device is set to sequentially scan 2 ^mn high-speed lines when is 0, and to sequentially scan 2 ^mn low-speed lines when it is 1.