JPS6027222B2 - Digital level difference detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital level difference detection circuit in a PB dial test device.

FIG. 1 shows such a conventional level difference detection circuit. In Fig. 1, 1 and 2 are input terminals, 3, 4, 9, and 10 are amplifiers, 5, 6, and 15 are rectifiers, 7 and 8 are limiters, 11,
12 is an attenuator, 13 and 14 are comparators, 16 and 17 are gate circuits, 18 is a timer circuit, 19 is a determination circuit, and 20 is an output terminal.The operation thereof will be explained below. Input terminals 1 and 2 each receive a PB signal branched into a low group and a high group from a band-elimination filter (not shown).

The input signals are input to amplifiers 3 and 4, respectively, and the outputs amplified by the amplifiers 3 and 4 are input to rectifiers 5 and 6 and limiters 7 and 8. The rectifiers 5 and 6 rectify the outputs of the amplifiers 3 and 4 and convert them to DC level, and then input the outputs to the buffer amplifier 97 io'.
It is amplified from 101. The outputs of the amplifiers 9, 10 are input to attenuators 11, 12 and comparators 13, 14. The attenuator 111 attenuates the output of the amplifier 9 and the comparator 1
The attenuator 12 attenuates the output of the amplifier 10 and provides the other input signal of the comparator 13. That is, the comparators 13 and 14 determine whether there is a level difference greater than a specified value between the signals input to the input terminals 1 and 2, and if either input signal is large, a level difference can be detected. An OR gate 17 calculates the logical sum of the outputs of the comparators 13 and 14, and inputs a "1" logic level to the timer circuit 18 when the level difference is greater than a specified value. On the other hand, the amplifier 3
, 4 and compares it with a fixed threshold, and in the case of a normal input signal, when the signal level is above the fixed threshold, it sends out a rectangular wave with a constant amplitude at duratio/2. By doing so, normal signals can be distinguished from noise, voice, and the like. The outputs of the limiters 7 and 8 are logically summed by an OR gate 16, and if a normal signal is input to only one of the input terminals 1 and 2, a bell difference can be detected. The output of the OR gate 16 is input to the rectifier 15, rectified by the rectifier 15, converted to a constant DC logic level, and input to the timer circuit 18. The timer circuit 18 is composed of two timers, the input of the timer 1 is the output of the OR gate 17, and the input of the timer 2 is the output of the rectifier 15. The timer 1 checks the time period during which a level difference of more than a specified value continues between two input signals, and sends a logic level "1" to the determination circuit 19 when the intermittent time is longer than the specified time. Similarly, the timer 2 checks the duration of the "1" logic level of the output of the rectifier 15, and sends the "1" logic level to the determination circuit 19 when the duration is longer than a specified time. The determination circuit 19 receives the output of the timer circuit 18 and distinguishes between a regular input signal, noise, voice, etc., and determines only in the case of a regular input signal whether or not there is a level difference greater than a specified value. As explained above, conventional level difference detection circuits require separate amplifiers, rectifiers, limiters, attenuators, and comparators for each of the two input signals, requiring a large amount of hardware, and also requires a time-division alternator. When used in a signaling device, etc., a DA converter is required at the front stage, which has the drawback of being unsuitable from the standpoint of compatibility and economy.

The object of the present invention is to eliminate these drawbacks and provide an economical digital level difference detection circuit that can be used in a time division switch or the like, and will be described in detail below.

FIG. 2 shows a circuit diagram according to an embodiment of the invention. In the figure, 21' is an input terminal, A is an absolute value circuit, B is a maximum value detection circuit, C, D, and B are comparison circuits, F is a protection circuit, G is a timer circuit, day is a judgment circuit, and 49 is an output. It is a terminal. Further, FIG. 3 is an operation time chart of the circuit shown in FIG. 2. The operation of the circuit shown in FIG. 2 will be explained below. (
The symbols a, b, . . . , k' in FIG. 3 are the same as the symbols for each part of the circuit shown in FIG. 2. ) The input terminal 21 receives two pairs of high group frequency and low group frequency (frequency assigned to the column and row of push buttons, respectively) decomposed by a digital demultiplexing film (not shown) used in multiplexing. Serial digital signals SH and SL for a plurality of circuits expressed as complements are input.

Also, this signal has one high group frequency and one low group frequency for each of n circuits.
It is sampled every 25 seconds and multiplexed the amplitude values at that time. (FIG. 3a) Next, this signal is input to the absolute value circuit A, the absolute value of each value is taken, and the signal is input to the next maximum value detection circuit B. In the absolute value circuit A, the polarity bit of the input digital signal is latched by the flip-flop 22, and the output of the flip-flop 22 and the signal delayed by the shift register 23 are exclusive-ORed by the OR gate 24. The absolute value of the signal is taken.

(Fig. 3b) Maximum value detection circuit B detects the maximum value of each of the above two types (high group wave series digital signal SH and high group wave series digital signal SL) for each multiple circuit within a certain period of time. , OR gate 2 of the absolute value circuit A
The output of 4 is input to the comparator 25 and simultaneously input to the shift register 26.

The comparator 25 compares the output of the OR gate 24, that is, the newly input signal this time, with the output of the delay register 30, that is, the maximum value signal up to the previous time, and uses the result as a selection control signal for the selector 28. . On the other hand, select evening 28-2
The two inputs are the OR gate 24 and the delay register 30.
is the output of the shift registers 26 and 27 which are delayed until the comparison result is obtained by the comparator 25, and the output of the selector 2
The output of 8 is sent to the shift register 26 by the selection control signal.
The output of the shift register 27 or the output of the shift register 27, whichever has a larger value, is selected and inputted to the delay register 30 through the AND gate 29. The output of the delay register 30 waits for one frame time (125 seconds in this embodiment) until the signal of the same channel is output again to the output of the OR gate 24. Thereafter, each time new data is input, the comparator 25 compares it with the contents of the delay register 30 and detects the maximum value within a certain period of time (hereinafter referred to as maximum value detection time) TM.
The maximum value detection time TM is set by adding a gate pulse GPO to the AND gate 29 at a constant cycle (1 second in this embodiment).The contents of the delay register 30 are cleared by this gate pulse GPO, and the next Preparations are made for maximum value detection within the maximum value detection time TM. Furthermore, by further delaying the output of the delay register 30 by the shift register 27, the shift register 27 outputs the maximum value of the low group frequency at the timing when the delay register 30 outputs the maximum value of the high group frequency (Fig. 3c). Output the maximum value. (Figure 3d)
That is, the maximum values of the two signals in a pairwise relationship whose level difference is to be detected are simultaneously sent to the comparator circuit C.
Hereinafter, processing from the comparison circuit C to the protection circuit F is performed at a cycle of the maximum value detection time TM (:1 skin s). The comparator 31 of the comparison circuit C compares the magnitude of the maximum signal of the high group frequency and the maximum value signal of the low group frequency, which are the outputs of the maximum value detection circuit B, and this power is the selection signal of the selector 33. Become.

The input of the selector 33 is the maximum value signal delayed by the shift register 27 and the shift register 32 until the comparison result by the comparator 31 is obtained. The maximum value of the low group frequency is input to . On the other hand, a large signal is output to the output S of the selector 33 (
A small signal is output to , out, and circle T-. (FIG. 3e) Then, the large signal S is sent to the comparison circuit D, and the small signal T is sent to the comparison circuit E. Comparator circuit D distinguishes between a regular PB signal and noise or voice.Comparator 3
Reference numeral 4 compares the large signal S with a fixed threshold value P, and outputs a signal V having a logic level "1" when S and P, for example, and a logic level "0" when S<P.

(FIG. 3f) Also, the comparator circuit E determines the presence or absence of a level difference to be detected, and the shift register 5 outputs the small signal T with a bit delay (in this embodiment, it is the level difference of 1 phantom B). A comparator 36 compares the signal T', which is amplified according to the level difference to be detected (difference) and delay), and the large signal S. For example, when SZT', the logic level is "1" and S
When <T', a signal W of logic level "0" is output.
(Figure 3g) Next, the protection circuit F is designed to correctly detect the level difference even if noise occurs on the transmission path in Mayumachi M and causes signal cracking (pig breakage) when the maximum value is detected. It is.
First, the multiplexer 37 selects the comparator 3 of the comparison circuit D.
4 and V, which is the output signal of the comparator 36 of the comparator circuit E,
After converting W into a serial signal, the output of the shift register 40 is logically summed with the OR gate 38, and the output of the shift register 40' is input again through the AND gate 9. ) is protected, and the protection signal W′,
V' are alternately output from the shift register 40. (FIG. 3b) FIG. 4 is a time chart for explaining the operation of the protection circuit F when there is a break in the input signal.

FIG. 4a shows an actual input waveform, where the part A is a short instantaneous interruption, and the mouth part is a part where there is no signal input (a part where the OFF time is long). Corresponding to this input signal, the input signals (V and W) to the protection circuit F are as shown in FIG. 4b. Next, a gate pulse GP with a period of 4 s shown in FIG.
I and enters shift register 40. This shift register 40' is a delay register for processing n multiplexed signals. Therefore, the output of the shift register 40 becomes as shown in FIG. 4d.
Since the subsequent writing and reading timings of the counter memory 43 of the timer circuit G and the shift register 47 of the judgment circuit day are performed at the timing of the gate pulse GPI, the portions a and b in FIG. The mouth part may be considered as FF). The output of the shift register 40 is input to the timer circuit G, and the other output is input to the determination circuit. Hereinafter, the timer circuit G and the determination circuit are processed at the cycle (4s) of the gate pulse GPI. Timer circuit G is adder 4
1 is added to the output of the counting memory 43, and the AND gate 42 performs a logical product with the protection signals W' and V', and the protection signals W' and V' are set to the logic level by inputting them to the counting memory 43. The duration time Tv of the state of “1” is counted.

The counting memory 43 alternately outputs digital values KW and Kv corresponding to the duration TW and Tv, and the comparator 44 outputs fixed values Q and R (Q is for correctly determining the level difference to be detected). , and R is for distinguishing it from an audio signal.In this example, Q=40s, R=
A value corresponding to 300 s is used. ) are compared alternately. First, the output × of the comparator 44 is “1” only in the case of KW2Q.
"The logic level is reached, and the judgment circuit HI signal is sent out. (FIG. 3i)
The output X of 4 and the output of the shift register 47 are logically summed by an OR gate 45, and the output of the OR gate 45 and the output of the shift register 40 of the protection circuit F are logically ANDed by an AND gate 46, and the output of the shift register 47 is ANDed again. 47, once the output x of the comparator 44 of the timer circuit G reaches the "1" logic level, the holding signal V' input to the AND gate 46 is shifted until it becomes the "0" logic level. The output of register 47 maintains a logic level of "1".

Next, when KvZR, the output Y of the comparator 44 (FIG. 3j) becomes a "1" logic level, and the AND gate 48 sends level difference detection information DET to the output terminal 49.

In other words, only when a level difference greater than a specified value exists between two input signals for a specified period of time or longer, and one of the signals has a level higher than the specified value for a specified period of time or longer, is the true level difference detected. It detects the presence of the device and prevents false detection due to noise or voice. It is a time chart showing the above-mentioned tie-doro G and the judgment wordless motion.

The outputs V' and W' of the shifter 40 have waveforms as shown in Figure 1, but as mentioned above, the outputs of the output circuit G and the determination circuit are at the timing of 4 cycles of the gate pulse GPI. As a result of the processing, the signal becomes in a signal state in which signal cracking is protected, as shown in FIGS. 5a and 5c. Figure 5 a, b, c, d
In this case, the protection signal W' of the output of the shift register 40 is "1"
The duration of the logic level state is a fixed value Q (=40ms
) At the above times, the output The output of the register 47 indicates that the logic level "1" is maintained.Furthermore, FIGS. ) In the above case, the output Y of the comparator 44 becomes "1" logic level, and the level difference detection information DET is sent to the output terminal 49 under the conditions of the output of the shift register 47 and the output Y of the comparator 44.
It shows that appears. As explained above, in the present invention, the maximum value of two input signals within a certain period of time is first taken, and the maximum values are compared to determine the magnitude of the signal level. There is no need to have two circuits for each circuit, and there is no need for level compression with a limiter, so there is an advantage that the amount of hardware can be reduced.

Since all the level difference detection circuits of the present invention perform digital signal processing, they can be used multiplexed and are highly economical, so they can be used as signal devices for digital systems such as time division switching.

[Brief explanation of the drawing]

FIG. 1 shows a block diagram of a conventional level difference detection circuit.
FIG. 2 is a block diagram of a digital level difference detection circuit which is an embodiment of the present invention, FIG. 3 is a time chart for explaining the operation of the present invention, and FIG. 4 is for explaining the operation of the protection circuit F. FIG. 5 is a time chart for explaining the operation of the timer circuit G and the determination circuit. A: Absolute value circuit, B: Maximum value detection circuit, C, ○, E: Comparison circuit, F: Rectifier circuit ''G: Timer circuit, H: Judgment circuit Y'2ii input terminal, 23, 2' 6, 27",/3
0, 32, 35, 40, 47: register, 25, 31,
34, 36, 44: Comparator, 28, 33: Selector, 3
7: multiplexer, 43: memory, 49: output terminal.
Figures of the ship, dimensions of the ship, N rudder diagram of the boat, Figure 3

Claims (1)

[Claims] 1. In a digital level difference detection circuit which receives a plurality of pairs of serial digital signals expressed in two's complement and detects the presence or absence of a signal level difference of a certain value or more with respect to each pair of the series digital signals, an absolute value circuit A that takes the absolute value of a pair of serial digital input signals; a maximum value detection circuit B that receives the output of the absolute value circuit A and detects the maximum value within a certain period of time; a first comparator circuit C that inputs the output and determines a large signal and a small signal based on the signal level difference between the two digital signals in the relationship of each pair of signals; A second comparison circuit D that compares the large signal with a fixed threshold value and a level difference between the small signal determined by the first comparison circuit C and the large signal are determined to determine whether or not the level difference is greater than a certain value. A third comparison circuit E to determine, an output of the second comparison circuit D and the third comparison circuit
A protection circuit F converts the output of the comparison circuit E into a serial signal and protects against instantaneous interruption for a certain period of time, and an input signal is input at the output of the protection circuit F to prevent false detection of signal level differences due to voice or noise. A timer circuit G that checks the signal intermittent time and the signal level difference intermittent time, and a determination circuit H that determines from the output of the protection circuit F and the output of the timer circuit G whether there is a signal level difference that is equal to or greater than a specified value due to the normal signal. If a level difference greater than a specified value exists between the plurality of pairs of serial digital input signals for a specified period of time or more, and one of the signals has a level higher than the specified value intermittently for a specified period of time or more. A digital level difference detection circuit characterized in that it detects the existence of a true level difference.