JP3114682B2 - Training signal detection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a training signal detecting device, and more particularly to a training signal detecting device used for detecting the arrival of a training signal in a TCM (time compression multiplex) type digital subscriber line termination device. Related to the device.

[0002]

2. Description of the Related Art Conventionally, this type of training signal detecting apparatus is sent from an opposite terminating device in a digital subscriber line termination system of the TCM system (time compression multiplex, so-called ping-pong transmission system). Used to detect training signals.

FIG. 5 shows an example of a received waveform of a training signal. This training pattern is "+
1 "," 0 "," 0 "," 0 "," 0 "," 0 ",
"0", "0", "-1", "0", "0", "0",
It consists of repetitions of "0", "0", "0", "0", and is transmitted from the transmitting side. Then, it is used for equalizer training of the receiving unit.

Incidentally, the loss is large depending on the transmission line characteristics, and the peak level of the received signal may be about 1/100 at the transmission point. For this reason, the training signal detection device includes: To reliably detect signals even on transmission lines with large losses. 2. Do not mistakenly detect noise as a signal. Performance is required.

FIG. 6 is a block diagram showing a first example of a conventional training signal detecting device. Referring to FIG. 1, a conventional training signal detection device 500
Is a band-pass filter 5 that receives the received signal 901 as an input.
01, a root-mean-square circuit 502 receiving the output of the band-pass filter 501 as an input, and a comparator 503 receiving the output of the root-mean-square circuit 502 as an input.

Next, the operation of the training signal detecting device 500 having the above configuration will be described. As shown in FIG. 5, the training signal has a periodicity every 16 samples. In the case of the digital subscriber line transmission system of the TCM system, since data is transmitted and received at 320 Kbaud, the training signal has a power spectrum characteristic peak at 20 KHz obtained by dividing 320 KHz by 16. The band-pass filter 501 separates and extracts this band component from other frequency components. The mean square circuit 502
The power average of the input signal in a certain unit time is calculated. The comparator 503 receives a signal when the output of the mean square circuit 502 is larger than the predetermined threshold value using a predetermined threshold value. And the detection signal 902 indicates “1”.
Is output.

FIG. 7 shows a second example of a conventional training signal detecting device. Referring to the figure, the training signal detecting apparatus 600 includes a comparator 604 having a received signal 901 as an input, and n having a first output of the comparator 604 and an operation clock 4 (n is a multiple of 8). +
1) D flip-flops 602 connected in cascade, D flip-flops 603 connected in cascade with m (m is n + 8) receiving the second output of the comparator 604 and the operation clock 4, and D flip-flops 602 , The output of the D flip-flop 16 steps away from the first step, the output of the ninth step of the D flip-flop 603, and the output of the D flip-flop 16 steps away from the ninth step. And an AND circuit 601.

In this case, if it is assumed that eight repetitions of +1 and -1 are confirmed and a signal is detected, n is 49 and m is 57
Becomes An operation clock 903 is input for operation timing of each of the D flip-flops 602 and 603.

Next, the operation of the training signal detecting device 600 having the above configuration will be described. Comparator 604
Outputs a first output when the level of the received signal is higher than a predetermined first threshold, and outputs a second output when the level of the received signal is lower than a predetermined second threshold. Output the output. When a training signal is received, “1” is input to the D flip-flop 602 every 16 stages, and “1” is input to the D flip-flop 603 every 16 stages, which is 8 steps away from the D flip-flop 602. Is set. When all inputs become “1”, the AND circuit 601 regards this as a signal arrival and outputs “1” as the detection signal 902.

[0010]

The above-mentioned conventional training signal detecting apparatus has the following problems. In the former training signal detection device 500, an arithmetic unit (multiplier, adder) is required for the mean square circuit 502 and the bandpass filter 501, and the circuit scale increases. In the latter training signal detection device 600, although the configuration is simplified because no arithmetic circuit is required, 106 D flip-flops (49 + 57) are still required.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a training signal detecting device capable of further reducing the circuit configuration.

[0012]

According to a first aspect of the present invention, there is provided a training signal detecting apparatus for detecting a training signal consisting of a predetermined short repeating unit pattern transmitted at the start of communication. , On
A unit pattern detecting means for detecting the unit pattern;
The unit pattern is detected by the unit pattern detection means.
Repeat timing of the same unit pattern
Timing detection means for detecting the
Repeat timing detected by return timing detection means
Feature bits representing training signals are input for each
Is detected, and if it cannot be detected,
Is a characteristic view that initializes the repetition timing detection means.
Bit detection means and the continuous detection by the characteristic bit detection means.
When the number of outgoings reaches the specified number,
It is constituted you and a counter for determining the arrival of training signals.

[0013] In the invention according to claim 1 configured as described above, the unit pattern detecting means includes the unit pattern detector.
Is detected, the timing is detected repeatedly from that point
The means starts detecting the repetition timing of the same unit pattern.
Therefore, the characteristic bit detecting means is provided for each repetition timing.
Whether the feature bit representing the training signal has been input
Detect whether or not. And if detected, the counter
Counts the number of consecutive detections,
It is determined that the training signal has arrived. Against this
And the characteristic bit detecting means detects the characteristic bit.
If not, reset the repetition timing detector
Therefore, the unit pattern detection means again makes the unit pattern
It repeats from detecting the turn.

[0014]

[0015]

Further, the invention according to claim 2 provides the invention
1. The training signal detection device according to 1, wherein the training signal is repeated while inverting the polarity by grouping a first bit of a predetermined polarity and a plurality of intermediate bits of any polarity. There is.

In the invention according to claim 2 configured as described above, for example, a plurality of intermediate bits follow as the first bit representing "+1", and then the same number as "-1" as the first bit. , And this is repeated to become the training signal.

Furthermore, according invention in claim 3, it said unit pattern detecting means is configured to detect a repeating pattern of the first bit as a unit pattern.

In the invention according to claim 3 configured as described above, after the intermediate bit following the first bit, the first bit whose polarity is inverted comes again, so that only this continuous pattern is used. The unit pattern detection means will detect.

Furthermore, the invention according to claim 4, the characteristic bit detection means, is configured so as to determine the presence or absence of incoming as a feature bits the first bit.

According to the fourth aspect of the present invention, since the first bit repeatedly arrives with the intermediate bit interposed therebetween, the characteristic bit detecting means sets the arrival of the first bit at each repetition timing. Is determined, it can be determined that the training signal has arrived.

Furthermore, the invention according to claim 5, the repeating timing detection means are constituted by a counter for determining that the repetitive timing signal every predetermined number of times according to the clock input.

In the invention according to claim 5 configured as described above, the repetition timing detecting means counts the number of clock inputs, and determines that the repetition timing is reached when the number of clock inputs becomes a predetermined number of times. I have.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a training signal detection device according to an embodiment of the present invention.

In FIG. 1, the training signal detecting device 1 includes a comparator (phase comparator) 11 to which the received signal 2 and the operation clock 4 are input. The comparator 11 samples the received signal 2 at the operation clock 4 and converts the received signal 2 into +1, 0, −1 based on a predetermined threshold value.
Is determined. That is, "1" is output to the first output when the determination result is +1 and "1" is output to the second output when the determination result is -1.

The operation clock 4 and the output of a D flip-flop 15 described later, together with the two outputs of the comparator 11, are input to a pattern detection circuit 12.

FIG. 2 is a block diagram showing the pattern detection circuit 12. In the figure, a pattern detection circuit 12 receives a first input signal 121 as a first output of the comparator 11 and an operation clock 4 as inputs.
A flip-flop 125 and a nine-stage cascade-connected D flip-flop 126 to which the second input signal 122 as the second output of the comparator 11 and the operation clock 4 are input
And an AND circuit 127 having the output of the D flip-flop 125 and the output of the last stage of the D flip-flop 126 as inputs, the output of the AND circuit 127, the operation clock 4, and the reset being the output of the D flip-flop 15 Set / reset circuit 128 having signal 123 as input
It is composed of

The pattern detection signal 124, which is the output signal of the pattern detection circuit 12,
The set reset circuit 128 outputs the pattern detection signal 124 at the next rising edge of the operation clock 4 when the output of the AND circuit 127 becomes "1".
Is set to "1". That is, the pattern detection circuit 12 receives the output of the comparator 11 as an input, and has an input pattern of +1, D, D, D, D, D, D, D, -1 (D is d
In the case of “on't care”, the output is set to “1”.

Next, the output of the pattern detection circuit 12 and the operation clock 4 are input to a first counter 13, and the output of the first counter 13 and the pattern detection circuit 12
Is output to a toggle circuit 16, and two outputs of the comparator 11 and an output of the toggle circuit 16 are connected to a selector 14.
The output of the selector 14, the output of the pattern detection circuit 12, and the output of the first counter 13 are D
The output of the flip-flop 15 and the output of the pattern detection circuit 12 and the output of the first counter 13 are input to a second counter 17.

The first counter 13, the D flip-flop 15, the toggle circuit 16, and the second counter 17
The output of the pattern detection circuit 12 is used as a reset input, and the operation starts when the output of the pattern detection circuit 12 is set to "1".

That is, the first counter 13 outputs "1" every eight samples, and the toggle circuit 16 inverts the output at the rising edge of the output of the first counter 13 to select the first counter 13.
4 is switched. The D flip-flop 15 captures the output of the selector 14 at the rising edge of the output of the first counter 13 (every eight samples).
It is always "1" when the determination result alternately repeats +1 and -1 every eight samples.

Then, the second counter 17 counts up at the rising edge of the output of the first counter 13,
If the counter 17 has expired, it is determined that the training signal has arrived, and the detection signal 3 is set to "1".

However, if the output of the D flip-flop 15 becomes "0" before the second counter 17 expires, the output of the pattern detection circuit 12 is set to "0". Then, the first counter 13, the D flip-flop 15, the toggle circuit 16, and the second counter 17
Are all in the reset state, and stop the operation until the output of the pattern detection circuit 12 becomes "1" again.

Next, the operation of the present embodiment having the above configuration will be described with reference to the timing chart shown in FIG.

Also in the present embodiment, it is assumed that a training signal that repeats +1 and −1 every eight samples as in the received waveform of FIG. 5 is received. The output of each block is performed in phase with the operation clock 4.

The comparator 11 discriminates the received signal 2 into +1, 0, and -1 in synchronization with the operation clock 4, and sets the first output and the second output according to the discrimination result. The determination and the output are performed as follows based on two thresholds A and B prepared in advance.

Relationship between input and threshold value Result of determination First output Second output Received signal 2> A + 1 “1” “0” A ≧ received signal 2> B 0 “0” “0” B ≧ received signal 2 −1 “0” “1” Here, threshold value A> threshold value B (generally, threshold value A = −threshold value B).
Is preferably set to a level at which noise is not erroneously determined to be +1 (or -1) when there is no signal.

The pattern detection circuit 12 receives the output of the comparator 11 as an input, and the input pattern is -1D, D, D, D,
When D, D, D, and +1 (D is don't care), "1" is output at the timing shown in FIG. This output "1" is held until reset. First
Is a counter that outputs "1" every eight samples. Then, the output of the pattern detection circuit 12 is used as a reset input, and the output of the pattern detection circuit 12 becomes "
When it is "0", it is in a reset state, and its count value is "0". On the other hand, when the output of the pattern detection circuit 12 becomes "1", the reset is released,
The pattern detection circuit 12 counts up at the fall of the operation clock 4. Therefore, as shown in FIG. 3, the first counter 13 outputs “1” when the count value becomes 7, and returns to “0” at the next falling edge of the operation clock 4. After this, the pattern detection circuit 1
The above operation is repeated while the output of 2 is "1".

The toggle circuit 16 includes the first counter 1
3 is used as a clock input, and the output is inverted every fall as shown in FIG. That is, each time the count value of the first counter 13 becomes 7 and outputs “1”, the output is inverted.

The selector 14 which receives the first and second outputs of the comparator 11 selects one of them according to the output of the toggle circuit 16 and outputs the selected one. Is the first input (the first output side of the comparator 11) when the output of the toggle circuit 16 is "1"
Is output, and when the output of the toggle circuit 16 is “0”, the second input (the second output side of the comparator 11) is output.

Here, the received signal 2 is "+1", "-1"
Is repeated every eight samples, the comparator 11
Are alternately output via the selector 14. And this selector 14
Are latched by the D flip-flop 15 every eight samples, so that the received signal 2 becomes “+1” or “−”.
If "1" is repeated every eight samples, the output of the D flip-flop 15 maintains "1". However, if the line condition is bad or the pattern detection circuit 12 accidentally detects the pattern, if the received signal 2 input to the comparator 11 repeats "+1" and "-1" every eight samples. Not necessarily. In such a case, the D flip-flop 15 outputs “0”.

Since the output of the D flip-flop 15 is connected to the pattern detection circuit 12, when the output of the D flip-flop becomes "0", the first counter 13
Then, the toggle circuit 16, the D flip-flop 15, and the second counter 17 enter a reset state, and stop operating until the output of the pattern detection circuit 12 becomes "1" again.

However, as long as such a situation does not occur, as shown in FIG. 3, if a training signal is received, the D flip-flop 15 always outputs "1". The second counter 17 uses the output of the pattern detection circuit 12 as a reset input, clears the count value to "0", and counts up at the falling edge of the output of the first counter 13 as a clock input. That is,
The second counter 17 advances the count value by one at the falling of the first counter 13.

When the second counter 17 expires while the output of the D flip-flop 15 is "1",
Assuming that a training signal has been detected, detection signal 3 is set to "1".
Set to. Here, the expiration value of the second counter 17 is set to “6”, for example, when confirming eight repetitions of “+1” and “−1”. This is because the pattern is detected twice by the pattern detection circuit 12.

Therefore, when the training signal is repeated a predetermined number of times, the detection signal becomes "1", and it can be determined that the training signal has arrived.

As described above, normally, only the pattern detection circuit 12 having a small circuit size is operated, and after detecting a pattern, the processing of the entire circuit is started, so that power consumption can be reduced. Further, since the pattern detection circuit 12 only needs to detect a short pattern, the circuit scale can be reduced.

That is, since the pattern detection circuit for detecting a short pattern is used and the block which always operates is limited to the pattern detection circuit, and the processing of the entire circuit is started after the pattern detection, the power consumption during standby is reduced. Since the configuration can be reduced and the pattern detection circuit detects short patterns, the circuit scale can be reduced.

For example, in the conventional training signal detection apparatus, when the repetition of "+1" and "-1" every eight samples is detected eight times to perform signal detection, the required number of D flip-flops required for the pattern detection circuit is obtained. The number is 49 for "+1 (or -1)", 57 for "-1 (or +1)", and a total of 106 is required, whereas the pattern detection circuit of the present invention requires "+1 (or -1)". Or -1) "for the side
, Which is 9 for “−1 (or +1)”, for a total of 10, so that it is possible to delete 1/10 or more D flip-flops.

Next, FIG. 4 shows a flowchart when the training signal detecting apparatus of the present invention is realized by software processing using a digital signal processor.

Basically, the hardware circuit shown in FIG. 1 is realized by software processing according to the same procedure, and the correspondence is as follows. The comparator 11 is configured in step S1, the pattern detection circuit 12 is configured in steps S2 to S5, the first counter 13 is configured in steps S6 and S7, and the toggle circuit 1 is configured in step S8.
6 and the selector 14 and the D flip-flop 15 in steps S9 to S12.
16 constitutes a second counter 17. Of course, this correspondence is a schematic one, and not all of them correspond perfectly, but the operation can detect the training signal almost in the above-described correspondence relation.

That is, even in this case, a short pattern is detected (steps S3 to S5), and after the detection, a +
Confirm that 1 (-1) is repeated (steps S6, S
7) Signal detection is performed when the number of times reaches a predetermined number (step S8), and signal detection is performed when the number of repetitions reaches the predetermined number after pattern detection (steps S13 and S14). ), After the pattern is detected, before the number of repetitions reaches a predetermined number,
When 1, -1 is not repeated (step S1
0, S12)), and the processing is performed again from the pattern detection.

When a digital signal processor is used, the storage capacity for pattern detection can be reduced as in the previous embodiment.

As described above, according to the present invention, the configuration of the training signal detecting apparatus is divided into a pattern detecting means for detecting a short pattern and a means for confirming repetition of "+1" and "-1" every eight samples. Normally, only the pattern detecting means is operated, so that power consumption and circuit scale can be reduced.

[0054]

As explained above, the present invention is
Training that can sufficiently reduce the circuit size
A signal detection device can be provided.

[0055]

[0056]

[0057]

[Brief description of the drawings]

FIG. 1 is a block diagram of a training signal detection device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a pattern detection circuit.

FIG. 3 is a timing chart of the training signal detection device.

FIG. 4 is a flowchart when a training signal detection device according to another embodiment is configured by a digital signal processor.

FIG. 5 is a waveform diagram of a training signal.

FIG. 6 is a block diagram of a conventional training signal detection device.

FIG. 7 is a block diagram of another conventional training signal detection device.

[Explanation of symbols]

 Reference Signs List 11 comparator 12 pattern detection circuit 13 first counter 14 selector 15 D flip-flop 16 toggle circuit, 17 second counter 121 input signal 122 input signal 123 reset signal 124 pattern detection signal 125 D flip-flop 126 D flip-flop 127 AND Circuit 128 Set reset circuit

Claims (5)

(57) [Claims] 1. A training signal detecting device for detecting a training signal consisting of a predetermined short repetitive unit pattern transmitted at the start of communication, comprising: a unit pattern detecting means for detecting the unit pattern ; The above unit pattern
From the time of detection, repeat timing of the same unit pattern
Repeatedly timing detecting means for detecting the ring, repeat is detected by the repetition timing detecting means
At each timing, the characteristic bit representing the training signal is
It detects whether or not it has been
The repetition timing detection means is initialized.
And wherein the bit detection means that, counting the consecutive number of times of detection by the feature bit detecting means
When the predetermined number of times
A training signal detection device comprising: a counter for determining arrival . 2. The training signal detecting apparatus according to claim 1, wherein the training signal is obtained by inverting the polarity of a first bit having a predetermined polarity and a plurality of intermediate bits of any polarity. A training signal detection device that is repeated. 3. The training signal detecting device according to claim 1, wherein the unit pattern detecting means detects the repeating pattern of the first bit as a unit pattern. 4. The training signal detecting device according to claim 1, wherein the characteristic bit detecting means determines whether the first bit has arrived as a characteristic bit. Training signal detection device. 5. The training signal detecting apparatus according to claim 1, 2, 3 or 4, the repeating timing detection means, a counter for determining that a recurring timing signal every predetermined number of times in response to the clock input A training signal detection device, comprising: