JPS6027214A - Electromagnetic delay line - Google Patents

Electromagnetic delay line

Info

Publication number
JPS6027214A
JPS6027214A JP13549783A JP13549783A JPS6027214A JP S6027214 A JPS6027214 A JP S6027214A JP 13549783 A JP13549783 A JP 13549783A JP 13549783 A JP13549783 A JP 13549783A JP S6027214 A JPS6027214 A JP S6027214A
Authority
JP
Japan
Prior art keywords
conductor
delay line
inductance element
winding grooves
bobbin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13549783A
Other languages
Japanese (ja)
Other versions
JPH0211168B2 (en
Inventor
Kazuo Kametani
一雄 亀谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Elmec Corp
Original Assignee
Elmec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elmec Corp filed Critical Elmec Corp
Priority to JP13549783A priority Critical patent/JPS6027214A/en
Publication of JPS6027214A publication Critical patent/JPS6027214A/en
Publication of JPH0211168B2 publication Critical patent/JPH0211168B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/30Time-delay networks

Landscapes

  • Coils Or Transformers For Communication (AREA)

Abstract

PURPOSE:To reduce an electromagnetic delay line at its size and to speed up the transmission by setting up a specific relation on a distance between the width of a conductor constituting a flat inductance element of the electromagnetic delay line and the center of a conductor opposed to its short side. CONSTITUTION:Plural winding grooves 8, 9 are formed on both the wide main sides of a flat and thin bobbin 7 consisting of an insulator with a prescribed pitch P in its width direction. The winding grooves 8, 9 formed on the upper and lower sides of the bobbin 7 are formed so as to have the depth allowing the winding grooves 8, 9 to overlap slightly each other and to be shifted by a half pitch respectively between the upper and lower sides. A conductor 10 having the approximately same width, i.e. a linear shape D, as the width of the winding grooves 8, 9 is wound around the winding grooves of the bobbin 7 with spaces like a single layer solenoid to form an inductance element 11. Since the winding grooves 8, 9 are formed with the depth allowing the winding grooves 8, 9 to overlap slightly each other, the wound element 11 is set up to D>=T so that the distance T between the centers of the conductors 10 in the short side direction of the bobbin 7 is smaller than the wire diameter D of the conductor 10.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明はインダクタンス素子とコンデンサを組み合わせ
た電磁遅延線に係り、特に、超高周波での使用に適し遅
延時間の比較的大きな電磁遅延線の改良に関する。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an electromagnetic delay line that combines an inductance element and a capacitor, and particularly relates to an improvement in an electromagnetic delay line that is suitable for use at ultra-high frequencies and has a relatively large delay time. .

〔従来技術とその問題点〕[Prior art and its problems]

この種の電磁遅延線としては、第1図および第2図に示
す構成のものがある。
This type of electromagnetic delay line has the configuration shown in FIGS. 1 and 2.

すなわち、偏平な棒状ボビン1に、線径りの導線2を所
定のピッチPで単層ソレノイド状にスペース巻きしてイ
ンダクタンス素子3を形成し、細長い誘電体板4の一主
面にアース電極5を設りるとともに対向主面に前記導線
2と同ピンチで容量電極6を設けてコンデンサCを形成
し、そのコンデン−!l−Cの容量電極6とインダクタ
ンス素子3の導線2とを接続して複数区間を有する集中
定数型に構成したものである。
That is, an inductance element 3 is formed by space-winding a conductive wire 2 having a diameter around a flat rod-shaped bobbin 1 at a predetermined pitch P in the shape of a single layer solenoid, and a ground electrode 5 is formed on one main surface of an elongated dielectric plate 4. At the same time, a capacitor C is formed by providing a capacitor electrode 6 on the opposite main surface with the same pinch as the conductor wire 2, and the capacitor C is formed. The 1-C capacitor electrode 6 and the conductive wire 2 of the inductance element 3 are connected to form a lumped constant type having a plurality of sections.

なお、両図において符号Wはボビン1における断面長辺
方向の距離であり、符号Bはボビン1の断面短辺方向の
距離であり、さらに符号Tは、ボ 、ビン1の断面短辺
方向における電流の向きが異なる導線2の中心間の距離
を示している。
In both figures, the symbol W is the distance in the long side direction of the cross section of the bobbin 1, the symbol B is the distance in the short side direction of the cross section of the bobbin 1, and the symbol T is the distance in the short side direction of the cross section of the bobbin 1. It shows the distance between the centers of conductive wires 2 with different current directions.

このように構成された電磁遅延線は、距離T、B、Dの
間に T = B、 + D・・・・・ (1)なる関係があ
り、ピッチPと距離Tの比を適当(例えば0.2 < 
P/T<1.9程度)に選定することにより、良好な遅
延特性例えば超高速の立ち上がり特性を得ることが可能
である。このような関係については本出願人が既に特願
昭57−27135号をもって開示した。
The electromagnetic delay line configured in this way has the following relationship between the distances T, B, and D: T = B, + D... (1), and the ratio between the pitch P and the distance T is set appropriately (for example, 0.2 <
P/T<about 1.9), it is possible to obtain good delay characteristics, for example, ultra-high-speed rise characteristics. This relationship has already been disclosed by the present applicant in Japanese Patent Application No. 57-27135.

そして、このような電磁遅延線にあって、超高速で遅延
時間の比較的大きなものを得るためには、巻数(区間数
)を多くしなければならない。
In such an electromagnetic delay line, in order to obtain ultra-high speed and a relatively large delay time, the number of turns (number of sections) must be increased.

例えば100程度の区間数を有する電磁遅延線において
は、導線2の損失による超高周波域での減衰が無視でき
なくなり、それを防ぐために導線2の断面積を大きくす
る必要がある。
For example, in an electromagnetic delay line having about 100 sections, attenuation in the ultra-high frequency range due to loss in the conducting wire 2 cannot be ignored, and in order to prevent this, it is necessary to increase the cross-sectional area of the conducting wire 2.

しかし、上述の(1)式から明らかなように、導線2の
断面積を大きくするために線径りを増やすと、距離Tも
大きくなってピッチPと距離Tの関係が遅延特性を良好
にする上述の条件からずれてくる。
However, as is clear from equation (1) above, when the wire diameter is increased to increase the cross-sectional area of the conductor 2, the distance T also increases, and the relationship between the pitch P and the distance T improves the delay characteristics. This deviates from the above-mentioned conditions.

もっとも、ボビン1の距離Bを小さくて距離りを増やし
ても距離Tが大きくならないようにすればよいが、ボビ
ン1に導線2を巻く構成の電磁遅延線にあってば、ボビ
ン1の距離Bを零とすることができず、−(1)式から B=T−D>0・・・・ (2) の関係があり、結局、 T>D・・・・・・・・ (3) すなわち、導線2の距離Tが線径りより大きくなってい
た。
However, if the distance B of the bobbin 1 is small so that the distance T does not increase even if the distance is increased, if the electromagnetic delay line has a configuration in which the conductor 2 is wound around the bobbin 1, the distance B of the bobbin 1 cannot be made zero, and from formula -(1), there is a relationship of B=T-D>0... (2), and in the end, T>D...... (3) That is, the distance T of the conducting wire 2 was larger than the wire diameter.

そのため、比較的遅延時間が大きい、換言すれば区間数
の多い電磁遅延線を構成する場合には、導線2の損失を
抑え、かつピッチPと距離Tの寸法双方を上述した関係
に選定するとともに小さくして超小型および超高速の電
磁遅延線を実現するには限界がある。
Therefore, when configuring an electromagnetic delay line with a relatively large delay time, in other words, a large number of sections, it is necessary to suppress the loss of the conductor 2, and to select both the pitch P and the distance T in the above-mentioned relationship. There are limits to the miniaturization of ultra-compact and ultra-high speed electromagnetic delay lines.

〔発明の目的〕[Purpose of the invention]

本発明はこのような状況の下になされたもので、インダ
クタンス素子における導体の幅を大きく保ったまま上述
したピッチPや導体間の距離Tの寸法を小さくすること
が可能で、損失が少なく、超小型および超高速で構造の
簡単な電磁遅延線の提供を目的とする。
The present invention was made under these circumstances, and it is possible to reduce the pitch P and the distance T between the conductors while keeping the width of the conductor in the inductance element large, thereby reducing loss. The purpose is to provide an electromagnetic delay line that is ultra-compact, ultra-high speed, and has a simple structure.

〔発明の構成と効果〕[Structure and effects of the invention]

この目的を達成するために本発明は、導体を単層ソレノ
イド状にスペース巻きした偏平なインダクタンス素子と
、このインダクタンス素子の所定のターン毎にアースと
の間に接続したコンデンサを備具、してなる電磁遅延線
において、前記導体の幅をDとし、前記インダクタンス
素子の短辺方向で対向する前記導体の中心間の間隔をT
とし、前記インダクタンス素子がD≧Tなる関係に設定
されてなるものである。
In order to achieve this object, the present invention includes a flat inductance element in which a conductor is space-wound in the form of a single-layer solenoid, and a capacitor connected between each predetermined turn of this inductance element and ground. In the electromagnetic delay line, the width of the conductor is D, and the distance between the centers of the conductors facing each other in the short side direction of the inductance element is T.
The inductance element is set to satisfy the relationship D≧T.

このような本発明の構成によれば、インダクタンス素子
における導体の幅を大きく保ったままピッチPおよび距
離Tの寸法を共に小さくすることが可能となり、導体の
損失を抑えてインダクタンス素子の望ましい結合係数を
得ることができる。
According to the configuration of the present invention, it is possible to reduce both the pitch P and the distance T while keeping the width of the conductor in the inductance element large, thereby suppressing loss in the conductor and improving the desirable coupling coefficient of the inductance element. can be obtained.

そのため、超高周波域での信号の減衰が少なく、かつ良
好な遅延特性例えば超高速の立ち上がり特性が得られる
とともに超小型化を図ることが極めて容易となる。
Therefore, signal attenuation in the ultra-high frequency range is small, good delay characteristics, such as ultra-fast rise characteristics, can be obtained, and it is extremely easy to achieve ultra-miniaturization.

特に、区間数の多い電磁遅延線にあっては、導体の損失
が極めて少なくなるので、有用である。
This is particularly useful for electromagnetic delay lines with a large number of sections, since conductor loss is extremely reduced.

〔発明の実施例〕[Embodiments of the invention]

以下本発明の詳細な説明する。 The present invention will be explained in detail below.

第3図および第4図は本発明の一実施例を示す平面図お
よび断面図である。
FIGS. 3 and 4 are a plan view and a sectional view showing an embodiment of the present invention.

両図において、絶縁体からなり偏平で細長いボビン7の
幅の広い両主面(図中上面および下面)には、幅方向に
複数の巻溝8.9が所定のピッチPで形成されている。
In both figures, a plurality of winding grooves 8.9 are formed at a predetermined pitch P in the width direction on both wide main surfaces (upper and lower surfaces in the figures) of a flat and elongated bobbin 7 made of an insulator. .

ボビン7の上面および下面に形成された巻溝8.9は、
互いに若干オーバーシップする深さ、かつ上面および下
面の間で各々半ピッチ分ずれるようにして形成されてい
る。
The winding grooves 8.9 formed on the upper and lower surfaces of the bobbin 7 are
They are formed to have depths that slightly overlap each other, and to be offset by a half pitch between the upper and lower surfaces.

ボビン7の’J$8.9には、巻溝8.90幅と略同じ
幅すなわち線径りを有する導線10が単層ソレノイド状
にスペース巻きされており、インダクタンス素子11が
形成されている。そして、巻溝8.9が互いに若干オー
パーラ・ノブする深さで形成されているので、巻かれた
インダクタンス素子11は、ボビン7の短辺方向の導線
10の中心間の距離Tが導線10の線径りよりも小さく
、T<Dとなっている。
In the 'J$8.9 of the bobbin 7, a conductive wire 10 having a width approximately the same as the width of the winding groove 8.90, that is, a wire diameter, is space-wound in a single-layer solenoid shape, and an inductance element 11 is formed. . Since the winding grooves 8 and 9 are formed at depths that are slightly parallel to each other, the wound inductance element 11 has a distance T between the centers of the conductive wire 10 in the short side direction of the bobbin 7. It is smaller than the wire diameter, and T<D.

インダクタンス素子11の一側面(ポビン7の短辺方向
の一側面)において、第4図に示すように、誘電体板1
2の一生面にアース電極13を形成しかつ対向主面に導
線10と同ピ・ノチで容量電極14を形成してなるコン
デンサ素子Cが、その容量電極14を導線10に半田付
けして接続されており、複数区間を有する集中定数型の
電磁遅延線が構成されている。
As shown in FIG.
A capacitor element C is formed by forming a ground electrode 13 on the living surface of the conductor 2 and forming a capacitor electrode 14 on the opposite main surface with the same pitch and notch as the conductor 10, and connects the capacitor electrode 14 to the conductor 10 by soldering. A lumped constant electromagnetic delay line having multiple sections is constructed.

なお第3図中符号Pは、ポビン7の両主面各々における
隣合う導体10の中心間の間隔であり、上述した第1図
の電磁遅延線のビ・ノチPに相当する。
Note that the symbol P in FIG. 3 is the distance between the centers of adjacent conductors 10 on each of both main surfaces of the pobbin 7, and corresponds to the bi-notch P of the electromagnetic delay line in FIG. 1 described above.

このように構成された電磁遅延線においては、インダク
タンス素子11が、ポビン7の短辺方向の導線10の中
心間の距離Tを導線10の線径りよりも小さく、すなわ
ちT<Dとしているので、導線10の線径りが大きくて
も導線10の中心間の距離Tの寸法が小さくなる。
In the electromagnetic delay line configured in this way, the inductance element 11 makes the distance T between the centers of the conducting wire 10 in the short side direction of the pobbin 7 smaller than the wire diameter of the conducting wire 10, that is, T<D. Even if the wire diameter of the conducting wire 10 is large, the distance T between the centers of the conducting wire 10 becomes small.

そのため、区間数が多くても導線10の損失を抑えるこ
とが可能で、ピッチPおよび距1i3IiTを小さくか
つ良好な条件に選定してインダクタンス素子9における
望ましい結合係数も確保することができる。
Therefore, even if the number of sections is large, loss in the conducting wire 10 can be suppressed, and a desirable coupling coefficient in the inductance element 9 can also be ensured by selecting the pitch P and the distance 1i3IiT to be small and under favorable conditions.

従って、超高周波域において、減衰を改良できるし、良
好な遅延特性例えば超高速の立ち上がり特性を得ること
ができ、形状も小型となる。
Therefore, in the ultra-high frequency range, attenuation can be improved, good delay characteristics, such as ultra-fast rise characteristics, can be obtained, and the size can be reduced.

しかも、距1@Tは、第1図のようにボビン1を介して
得られるものではなく、巻溝8.9の深さを適当に選択
することにより、任意に、特に微小に選定可能であって
構造が簡単である。
Moreover, the distance 1@T is not obtained through the bobbin 1 as shown in Fig. 1, but can be arbitrarily selected, especially minutely, by appropriately selecting the depth of the winding groove 8.9. The structure is simple.

第5図〜第7図は本発明の電磁遅延線の別の実施例を示
すものである。
5 to 7 show other embodiments of the electromagnetic delay line of the present invention.

この実施例においては、銅箔や銅板からなり所定の長さ
くH−I、I−J、J、−に、・・)を有する幅りの導
体片15〜17・・を、その中心を交互にずらせて一体
的に連結して帯状導体18を形成し、第6図に示すよう
に、各導体片15〜17の境界部(H,I、J、に、・
・)をじぐざぐ状に折り曲げた偏平なインダクタンス素
子11を形成し、その帯状導体18の折り曲げ部に、第
4図に示すようなコンデンサCの容量電極14を接続し
、複数区間を有する集中定数型の電磁遅延線が構成され
ている。
In this embodiment, conductor pieces 15 to 17, which are made of copper foil or copper plate and have predetermined lengths H-I, I-J, J, -, etc., are arranged alternately at their centers. The band-shaped conductor 18 is formed by integrally connecting the conductor pieces 15 to 17 at the boundaries (H, I, J, etc.) as shown in FIG.
) is bent into a jagged shape to form a flat inductance element 11, and the bent part of the band-shaped conductor 18 is connected to the capacitive electrode 14 of a capacitor C as shown in FIG. A type of electromagnetic delay line is constructed.

このような電磁遅延線は、H−I、J−に間の各導体片
15.17の中心は、第5図に示す仮想線Q−Qの上に
位置し、I−J間の導体片16の中心は仮想線R−Rの
上に位置する。そのため、上述した電磁遅延線の距離T
に相当する距離は、帯状導体18が折り曲げられた場合
に対向する導体の中心間の距離、すなわち仮想線Q−Q
とR−8間の距離となる。
In such an electromagnetic delay line, the center of each conductor piece 15.17 between H-I and J- is located on the imaginary line Q-Q shown in FIG. 16 is located on the virtual line RR. Therefore, the distance T of the electromagnetic delay line mentioned above
The distance corresponding to
and R-8.

この場合にも、距離Tは、各導体片15.17と導体片
16の中心をずらせるだけで極めて小さくすることが可
能となるうえ、導体片15〜17の幅りは距離Tより広
くすることが可能であり、損失を抑えることができる。
In this case as well, the distance T can be made extremely small by simply shifting the centers of the conductor pieces 15, 17 and 16, and the width of the conductor pieces 15 to 17 is made wider than the distance T. It is possible to reduce losses.

さらに、第6図に示すように、導体18が薄くピッチP
も小さくできるので、ピッチPおよびTを共に極めて小
さく選定可能となり、そのため、高密度化および超小型
化を図りつつ良好な遅延特性を得ることができる。
Furthermore, as shown in FIG.
Since the pitches P and T can both be made extremely small, it is possible to obtain good delay characteristics while achieving high density and ultra-miniaturization.

また、上述の実施例においてインダクタンス素子11の
導線10や導体片18の幅りと距離Tの関係をD>Tと
して構成したが、本発明にあっては少なくともD≧Tな
る関係に選定すれば本発明の目的達成が可能である。
Further, in the above-described embodiment, the relationship between the width of the conductive wire 10 and the conductor piece 18 of the inductance element 11 and the distance T was configured as D>T, but in the present invention, it is preferable to select the relationship such that at least D≧T. The object of the invention can be achieved.

以上説明したように本発明の電磁遅延線は、偏平なイン
ダクタンス素子を構成する導体の幅をDとし、短辺方向
で対向する前記導体の中心間の間隔をTとし、前記イン
ダクタンス素子をD≧Tなる関係に設定したので、導体
の断面積を大きくしたままPおよびTを共に小さくする
ことが可能となり、導体の損失が小さく、超小型化およ
び超高速化を達成することが可能であり、構造も簡単と
なる。
As explained above, in the electromagnetic delay line of the present invention, the width of the conductor constituting the flat inductance element is D, the distance between the centers of the conductors facing each other in the short side direction is T, and the inductance element is D≧ Since the relationship is set as T, it is possible to reduce both P and T while increasing the cross-sectional area of the conductor, and the loss of the conductor is small, making it possible to achieve ultra-miniaturization and ultra-high speed. The structure is also simple.

【図面の簡単な説明】[Brief explanation of drawings]

第1図および第2図は本発明の参考となる電磁遅延線を
示す正面図および側面図、第3図および第4図は本発明
の電磁遅延線の一実施例を示す平面図および側面図、第
5図〜第7図は本発明の電磁遅延線の他の実施例を示す
要部展開図、正面図および概略側面図である。 1.7・・・・・ボビン 2.10.18・導体(導線) 3.11・・・・インダクタンス素子 4.12・・・・絶縁基板(誘電体板)5.13・・・
・アース電極 6.14・・・・容量電極 15〜17・・・導体片 I8・・・・・・帯状導体 C・・・・・・・コンデンサ 特許出願人 エルメック株式会社
1 and 2 are a front view and a side view showing an electromagnetic delay line as a reference for the present invention, and FIGS. 3 and 4 are a plan view and a side view showing an embodiment of the electromagnetic delay line of the present invention. , FIG. 5 to FIG. 7 are a developed view, a front view, and a schematic side view of essential parts showing other embodiments of the electromagnetic delay line of the present invention. 1.7...Bobbin 2.10.18 Conductor (conductor wire) 3.11...Inductance element 4.12...Insulating substrate (dielectric plate) 5.13...
・Earth electrode 6.14... Capacitive electrode 15-17... Conductor piece I8... Band-shaped conductor C... Capacitor patent applicant Elmec Co., Ltd.

Claims (3)

【特許請求の範囲】[Claims] (1)導体を単層ソレノイド状にスペース巻きした偏平
なインダクタンス素子と、 このインダクタンス素子の所定のターン毎にアースとの
間に接続したコンデンサを備具してなる電磁遅延線にお
いて、 前記導体の幅をDとし、前記インダクタンス素子の短辺
方向で対向する前記導体の中心間の間隔をTとし、前記
インダクタンス素子がD≧Tなる関係に設定されてなる
ことを特徴とする電磁遅延線。
(1) In an electromagnetic delay line comprising a flat inductance element in which a conductor is space-wound in the shape of a single-layer solenoid, and a capacitor connected to the ground at each predetermined turn of the inductance element, An electromagnetic delay line characterized in that a width is D, a distance between the centers of the conductors facing each other in the short side direction of the inductance element is T, and the inductance elements are set in a relationship such that D≧T.
(2)インダクタンス素子が、偏平なボビンの対向主面
に各々所定のピンチで互いにオーバーラツプする深さで
形成された巻溝に導体を巻いてなる特許請求の範囲第1
項記載の電磁遅延線。
(2) The inductance element is formed by winding a conductor in winding grooves formed on the opposing main surfaces of a flat bobbin at a depth that overlaps each other with a predetermined pinch.
Electromagnetic delay line as described in section.
(3)インダクタンス素子が、所定の長さの導体片複数
をその導体片の中心を交互にずらせて一体的に連続形成
するとともに、隣合う導体片の境界部を順次じぐざぐ状
に折り曲げてなる特許請求の範囲第1項記載の電磁遅延
線。
(3) The inductance element is formed by integrally and continuously forming a plurality of conductor pieces of a predetermined length with the centers of the conductor pieces alternately shifted, and by sequentially bending the boundaries of adjacent conductor pieces in a zigzag shape. An electromagnetic delay line according to claim 1.
JP13549783A 1983-07-25 1983-07-25 Electromagnetic delay line Granted JPS6027214A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13549783A JPS6027214A (en) 1983-07-25 1983-07-25 Electromagnetic delay line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13549783A JPS6027214A (en) 1983-07-25 1983-07-25 Electromagnetic delay line

Publications (2)

Publication Number Publication Date
JPS6027214A true JPS6027214A (en) 1985-02-12
JPH0211168B2 JPH0211168B2 (en) 1990-03-13

Family

ID=15153120

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13549783A Granted JPS6027214A (en) 1983-07-25 1983-07-25 Electromagnetic delay line

Country Status (1)

Country Link
JP (1) JPS6027214A (en)

Also Published As

Publication number Publication date
JPH0211168B2 (en) 1990-03-13

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