JPS59144204A - Electromagnetic delay line - Google Patents

Electromagnetic delay line

Info

Publication number
JPS59144204A
JPS59144204A JP1852483A JP1852483A JPS59144204A JP S59144204 A JPS59144204 A JP S59144204A JP 1852483 A JP1852483 A JP 1852483A JP 1852483 A JP1852483 A JP 1852483A JP S59144204 A JPS59144204 A JP S59144204A
Authority
JP
Japan
Prior art keywords
conductor
line
folded
capacitor
conductors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1852483A
Other languages
Japanese (ja)
Other versions
JPH0451081B2 (en
Inventor
Kazuo Kametani
一雄 亀谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Elmec Corp
Original Assignee
Elmec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elmec Corp filed Critical Elmec Corp
Priority to JP1852483A priority Critical patent/JPS59144204A/en
Publication of JPS59144204A publication Critical patent/JPS59144204A/en
Publication of JPH0451081B2 publication Critical patent/JPH0451081B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P9/00Delay lines of the waveguide type
    • H01P9/006Meander lines

Abstract

PURPOSE:To improve delay characteristics and to realize size reduction and use in an ultrahigh frequency band by connecting a capacitor which is connected between a conductor line and the earth to a halfway point of a breadthwise conductor in the line, and dividing it to adjacent sections. CONSTITUTION:The conductor line 3 as a folded conductor line is formed by bending a thin and long conductor integrally, alternately, and perpendicularly at pitch P, and folded conductors 4, 5... folded breadthwise are arranged in parallel to constitute inductance elements. A thin and long beltlike earth electrode 1 is arranged opposite to the folded electrodes 4, 5... under the conductors line 3 while crossing the centers of the folded conductors. Capacitor chips 9... of capacitor C obtained by providing counter electrodes to dielectrics are interposed between the reverse surface centers of the folded conductors and earth electrode 1 by connecting the counter electrodes to the folded conductors 4, 5... and earth electrode 1.

Description

【発明の詳細な説明】 本発明はインダクタンス素子とコンデンサを組合せてな
る電磁遅延縁に係り、特に折れ曲り導線路とコンデンサ
を具備し、膜技術等によって平面的に構成することが容
易でノ・イブ’Jノt’IC’4への実装に適した電磁
遅延線に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electromagnetic delay edge formed by combining an inductance element and a capacitor. This invention relates to an electromagnetic delay line suitable for implementation in Eve'Jnot'IC'4.

従来、平面的なパターンからなるインダクタンス電子を
用いて構成した電磁遅延線としては・一般の電子部品を
実装するプリント基板上に配線用回路パターンと一緒に
渦巻状のコイルパターンを複数形成し・各コイルを直列
接続してインダクタンス素子を構成するとともに・各コ
イルの接続点とアース間にコンデンサを接続してなる構
造を有するものがある。
Conventionally, electromagnetic delay lines constructed using inductance electrons consisting of planar patterns have been constructed by forming multiple spiral coil patterns together with wiring circuit patterns on a printed circuit board on which general electronic components are mounted. Some have a structure in which coils are connected in series to form an inductance element, and a capacitor is connected between the connection point of each coil and ground.

しかし・このようにプリント基板上に渦巻状のコイルを
形成してコンデンサと組合せる構造にあっては、渦巻状
のコイルおよびコンデンサのプリント基板上に占る面積
が広くなりがちとなって形状が大形化し易く、遅延特性
も十分ではなかった。
However, in this structure where a spiral coil is formed on a printed circuit board and combined with a capacitor, the spiral coil and capacitor tend to occupy a large area on the printed circuit board, resulting in the shape being distorted. It was easy to increase the size and the delay characteristics were not sufficient.

また一方、第1図に示すように、アース電極1の主面に
形成した誘電体層2上に所謂折れ曲り線路と称されるジ
グザグ状の導線路3を形成し、この導線路3をインダク
タンス素子としてこの導線路3とアース電極1間で形成
される容量とによって分布定数型の電磁遅延線を構成し
たものもある。
On the other hand, as shown in FIG. 1, a zigzag-shaped conducting path 3 called a so-called bent line is formed on the dielectric layer 2 formed on the main surface of the earth electrode 1, and this conducting path 3 is connected to an inductance. There is also an element in which a distributed constant type electromagnetic delay line is constructed by the capacitance formed between the conducting line 3 and the ground electrode 1.

なお第1図中、誘電体層2は導線路3と同様に折れ曲る
ように形成された状態で示したが、アース電極1と略同
様に一様な面積で形成されている。
In FIG. 1, the dielectric layer 2 is shown to be bent like the conductive line 3, but it is formed to have a uniform area almost like the ground electrode 1.

極1上に誘電体層2および導線路3を形成することが可
能であるうえ、導線路3とアース電極1間でコンデンサ
を形成するので・量産性が良好で小形になる反面・第1
図における導線路3中に矢印で示すように・導線路3に
おける並行なρり合う導線4・5.6・・に流れる電流
の方向か互V−に逆方向となることから、隣り合う導線
4・5.6・・・間の結合が負となる。
It is possible to form the dielectric layer 2 and the conductive line 3 on the pole 1, and also form a capacitor between the conductive line 3 and the earth electrode 1.
As shown by the arrows in the conductor line 3 in the figure, the directions of current flowing through the parallel conductor lines 4, 5, 6, etc. in the conductor line 3 are opposite to each other, so the adjacent conductors The coupling between 4, 5, 6... is negative.

従って、インダクタンス素子の主要な相互誘導が負とな
って、遅延特性の平担な周波数範囲が著しく狭く、立上
り時間や出力波形歪等の遅延特性が劣る欠点がある。特
に、インダクタンス素子の形成密度を向上きせるため、
隣り合う導線4.5.6・・・間の間隔を狭くすると、
さらに負の結合が増加するので、超高周波帯における実
施および小形化か困難なものになっていた。
Therefore, the main mutual induction of the inductance elements becomes negative, and the frequency range in which the delay characteristics are even is extremely narrow, resulting in poor delay characteristics such as rise time and output waveform distortion. In particular, in order to improve the formation density of inductance elements,
If the distance between adjacent conductors 4.5.6... is narrowed,
Furthermore, the increase in negative coupling makes implementation in ultra-high frequency bands and miniaturization difficult.

このように従来の電磁遅延線は、いずれの構成にあって
も遅延特性が良好で小形かつ超高周波帯での実施が可能
な電磁遅延線を実現しにくかった。
As described above, regardless of the configuration of conventional electromagnetic delay lines, it has been difficult to realize an electromagnetic delay line that has good delay characteristics, is compact, and can be implemented in an ultra-high frequency band.

本発明は、上述の従来例に示した折れ曲り線路を鋭意検
討した結果、インダクタンス素子における主要な相互誘
導である瞬り合う導線間の負の相互誘導が遅延特性に影
響しにくくするとともに、□逆に正の相互誘導を主要な
相互誘導とすることの可能なことを見出した。
As a result of careful study of the bent line shown in the conventional example described above, the present invention has been developed to make negative mutual induction between twinkling conductors, which is the main mutual induction in an inductance element, less likely to affect delay characteristics. On the contrary, we found that it is possible to make positive mutual induction the main mutual induction.

本発明はこのような状況の下になされたもので、遅延特
性が良好で・小形かつ超高周波帯での実施が可能な電磁
遅延線の提供を目的とする。
The present invention was made under these circumstances, and aims to provide an electromagnetic delay line that has good delay characteristics, is compact, and can be implemented in an ultra-high frequency band.

この目的を達成するため本発明は、折れ曲り導線路と、
この導線路とアース間に接続されたコンデンサとを具備
し、複数の区間を有する電磁遅延線において、前記コン
デンサカベ前記導線路中の1pF@方向の導体の途中に
接続され、この導体の途中で隣り合う区間に分割されて
なることを特徴とするものである。
To achieve this objective, the present invention provides a bent conductor line,
In an electromagnetic delay line that includes a capacitor connected between the conductive line and the ground and has a plurality of sections, the capacitor wall is connected in the middle of the conductor in the 1 pF@ direction in the conductive line, and It is characterized by being divided into adjacent sections.

このような本発明の構成によれば、隣り合う区間の相互
誘導を正の結合状態にすることが可能となり、遅延特性
が良好になるうえ小形化および超高周波帯での使用を確
保することができる。
According to such a configuration of the present invention, it is possible to make the mutual induction between adjacent sections into a positive coupling state, and it is possible to improve delay characteristics and also to ensure miniaturization and use in an ultra-high frequency band. can.

以下本発明の詳細な説明する。なお・従来例と共通する
部分には同一の符号を付す。
The present invention will be explained in detail below. Note that parts common to the conventional example are given the same reference numerals.

第2図および第3図は本発明に係る電磁遅延線の一実施
例を示す斜視図および概略平向図である。
2 and 3 are a perspective view and a schematic plan view showing an embodiment of the electromagnetic delay line according to the present invention.

折れ曲り導線路としての導線路3は、薄く細゛長い導体
を一体的に所定のピッチPで交互かつ直角に折り返えす
ように曲げて形成されており、所定のピッチPで−jN
 (2W)方向に折り返えされた折り返し尊称4.5.
6・・・が各々並行に配置され、インダクタンス素子を
構成している。なお符号7.8・・・は、各折り返し導
線4.5.6・・・間を連結する連結部である。
The conductor line 3 as a bent conductor line is formed by integrally bending a thin and long conductor at a predetermined pitch P so as to be bent alternately and at right angles.
Folded honorifics folded in the (2W) direction 4.5.
6... are arranged in parallel, forming an inductance element. Note that the reference numerals 7.8, . . . are connecting portions that connect the respective folded conducting wires 4, 5, 6, .

導線路3の下方には、各折り返し導線4.5.6・・・
の中央を各々直角に横切るような仮想線Y −Yに沿っ
て細長い帯状のアース電極1がその打丁り返し導線4.
5.6・・・と対向して配置されている。
Below the conductor line 3, each folded conductor line 4,5,6...
An elongated strip-shaped ground electrode 1 is connected to the conductive wire 4 along the virtual line Y-Y that crosses the center of each at a right angle.
5.6... are arranged opposite to each other.

各折り返し導線4・5・6・・・の下面中央とアース電
極1間には・誘電体に対向電極を形成した容量Cのチッ
プ状のコンデンサ9・・・が、その対向電極を折り返し
導線4・5・6・・・およびアース電極1に接続して介
在され・集中定数型の電磁遅延称が構成されている。
Between the center of the lower surface of each folded conductor 4, 5, 6... and the ground electrode 1, a chip-shaped capacitor 9 having a capacitance C with a counter electrode formed on a dielectric material is connected to the folded conductor 4.・A lumped constant type electromagnetic delay term is constructed by being connected to 5, 6, and the earth electrode 1.

この電磁遅延線は、各折り返し導線4.5.6・・・に
おける仮想線Y−Yと交わる部分すなわち各中央部にコ
ンデンサを配置してなり、例えば折り返し導線4.5.
6・・およびそれらの連結部7.8に着目し、第3図に
示すように、折り返し導線46.5.6・・・の中央部
をA点、F点、5点、折り返し導線4.5と連結部7の
境をB点、E点とすると、各点A、B、E、Fで結ばれ
た口字形の導線部10が1区間分のインダクタンスLを
形成し、同様に折り返し4排5.6と連結部8との境を
G点、H点とすれば、各点F、G、H,Jで結ばれた口
字形の導線部11が前記インダクタンス素子隣り合う1
区間分のインダクタンスLを形成しており、電磁遅延線
が複数の区間から構成されている。
This electromagnetic delay line is formed by arranging a capacitor at a portion of each of the folded conductors 4.5.6, .
6... and their connecting parts 7.8, as shown in FIG. 5 and the connecting portion 7 are points B and E, the opening-shaped conducting wire portion 10 connected at each point A, B, E, and F forms an inductance L for one section, and similarly the folding portion 4 If the boundaries between the exhaust 5.6 and the connecting portion 8 are points G and H, then the opening-shaped conducting wire portions 11 connected at each point F, G, H, and J are connected to the adjacent inductance element 1.
An inductance L for each section is formed, and the electromagnetic delay line is composed of a plurality of sections.

1区間分のインダクタンスL、例えば折り返し導線4.
5および連結部7の点4.B、E、Fで形成すれる口字
形の導線部10のインダクタンスL中に含まれる相互誘
導は、点A=B、点E −Fの2本の長さWの並行な導
線間に形成されるものだけであり、導線路3における主
要な相互誘導である隣り合う折り返し導線4・5間の負
の相互誘導(折り返し導線4.5の逆方向電流による)
の半分の長さWが、1区間のインダクタンスLの中に含
まれてしlう。そしてこの負の結合は、1区間における
インダクタンスLを減少させる作用のみを有することと
なる。
Inductance L for one section, for example, folded conductor 4.
5 and point 4 of connecting portion 7. Mutual induction included in the inductance L of the opening-shaped conducting wire portion 10 formed by B, E, and F is formed between two parallel conducting wires of length W at points A=B and points E-F. Negative mutual induction between adjacent folded conductors 4 and 5 (due to reverse current in folded conductors 4 and 5) is the main mutual induction in conductor line 3.
A half of the length W is included in the inductance L of one section. This negative coupling only has the effect of reducing the inductance L in one section.

第4図は第2図に示す電磁遅延線の等価回路であり・符
号a1は隣り合うインダクタンスL間の結合係数・符号
a2は1個おいた2番目のインダクタンスL間の結合係
数、符号anはn番目のインダクタンスL間の結合係数
であり、同図において最左端のインダクタンスLとの結
合係数を示しているが、その左側にもインダクタンスL
があってそれらとも結合しており、他のインダクタンス
しについても同様に左右のインダクタンスLと結合して
いる。
Figure 4 is an equivalent circuit of the electromagnetic delay line shown in Figure 2. Symbol a1 is the coupling coefficient between adjacent inductances L. Symbol a2 is the coupling coefficient between the second inductance L. Symbol an is the coupling coefficient between adjacent inductances L. This is the coupling coefficient between the n-th inductance L, and the coupling coefficient with the leftmost inductance L in the figure is shown, but there is also an inductance L on the left side.
The other inductances are similarly connected to the left and right inductances L.

次に、このように構成された本発明の電磁遅延線につい
て、各区間の結合状態、特に隣り合う区間の結合係数a
1を第3図および第5図を参考にして説明する。
Next, regarding the electromagnetic delay line of the present invention configured as described above, the coupling state of each section, especially the coupling coefficient a of adjacent sections, will be explained.
1 will be explained with reference to FIGS. 3 and 5.

両図において、折り返し導線5の中央部にコンデンサ9
が接続され、折り返し導線5がこの接続部によって点A
、B、E、Fで結ばれた口字形の導線部10と点F、G
、H,Jで結ばれた口字形の導線部11とに分割されて
隣り合う区間が形成され、両コ字形の導線部10.11
の相互誘導の符号と値が結合係%alを決定する。
In both figures, a capacitor 9 is placed in the center of the folded conductor 5.
is connected, and the folded conductor 5 is connected to point A by this connection.
, B, E, F and the points F, G.
, H, and J to form adjacent sections, and both U-shaped conducting wire sections 10.11
The sign and value of the mutual induction of determines the coupling coefficient %al.

第5図は口字形の導線部10.11間に形成される全て
の相互誘導を示すものであり、連結部(点B−E、点G
−H’)7.8間をMl、折り返し導線5における点E
−Fと点F−G間の相互誘導をM2、折り返し導線4お
よび6における点A−Bと点H−J間の相互誘導をM3
、折り返し導線4および5における点A−Bと点F−G
間の相互誘導をM4、そして折り返し導線5および6に
おける点E−Fと点H’−J間の相互誘導をM5とすれ
ば、M1〜M3は電流の向きが同しであるので正結合と
なり・M4およびM5は電流の向きが逆向きであるから
負結合となる。なお、M1〜M5 は絶対値で示されて
いる。
FIG. 5 shows all the mutual guidance formed between the mouth-shaped conductor parts 10 and 11, and the connecting parts (points B-E, G
-H')7.8 Ml, point E on folded conductor 5
M2 is the mutual guidance between -F and point FG, and M3 is the mutual guidance between point A-B and point H-J in folded conductors 4 and 6.
, point A-B and point F-G in folded conductors 4 and 5
If the mutual induction between them is M4, and the mutual induction between points E-F and H'-J in folded conductors 5 and 6 is M5, the current directions in M1 to M3 are the same, so they are positive coupled. - M4 and M5 have negative coupling because the current directions are opposite. Note that M1 to M5 are shown as absolute values.

従って、両コ字形の導線部10.11間の相互誘導は・
M l+ M 2 + M 37 M 4  M s 
となる。またM2〜M5 についてはその距離関係から
M2>M4”M 5 、> M 3の関係が成立し、さ
らKM2+M3−へ44−ki、)Oなる関係がある“
ので、これらの関係と・正結合のMlをまとめると、結
合係数a1は常に正になる0 しかも結合係数21は、折り返し導線4・5・6・・・
の長さ、すなわち導線路3の幅(2WもしくはW)方向
の長さ、折り返し導線4.5.6・・・の厚さ、ピンチ
P等によって色々の値が得られるので最適値を選定する
ことが可能であり、一方相互誘導M4およびM5は、導
線路3における負の主要相互誘導を構成する一要素であ
るか、alに含まれるとともに211を構成する他の正
の結合より常に小さいので・alを負にするような悪影
響をインダクタンス素子に与えない。
Therefore, the mutual induction between the two U-shaped conductor portions 10 and 11 is...
M l + M 2 + M 37 M 4 M s
becomes. Regarding M2 to M5, the distance relationship holds that M2>M4''M5, > M3, and furthermore, there is a relationship of 44-ki to KM2+M3-, )O.
Therefore, if we summarize these relationships and Ml of positive coupling, the coupling coefficient a1 is always positive 0.Moreover, the coupling coefficient 21 is the folded conductors 4, 5, 6, etc.
Various values can be obtained depending on the length of the conductor line 3 in the width direction (2W or W), the thickness of the folded conductor line 4, 5, 6, the pinch P, etc., so select the optimal value. It is possible, on the other hand, that the mutual inductions M4 and M5 are one element constituting the negative main mutual induction in the conducting line 3, or are always smaller than the other positive couplings contained in al and constituting 211. -Does not have an adverse effect on the inductance element, such as making al negative.

次に、折り返′し導線5および6における点E−Fと点
J−に間の相互誘導は、流れる電流の向きが逆であるの
で負であり、これも導線路3における負の主要相互誘導
を構成する一要素であるが、これはコ字形の導線部10
に対して2査目の区間との間の結合係数32に含まれる
こととなり、一般に遅延線にあってはa2が負の結合で
あることが望ましいことから、a2に対し有用に機能す
る。
Next, the mutual induction between points E-F and J- in the folded conductors 5 and 6 is negative because the direction of the current flowing is opposite, and this is also due to the negative main mutual induction in the conductor line 3. One element that constitutes the guidance is the U-shaped conducting wire portion 10.
It is included in the coupling coefficient 32 between the second scanning interval and the second scan interval, and since it is generally desirable for a2 to be a negative coupling in a delay line, it functions usefully for a2.

このように本発明に係る電磁遅延線は・インダクタンス
素子を構成する導線路3に生ずる負の主要な相互誘導を
1区間分のインダクタンスし、インダクタンスL間の結
合係数a1およびa2に′分割して含ませることにより
その影響を抑え、結合係数31を正の結合にすることが
できるので、従来の如き導線路3を用いても立上り時間
や出力波形の歪等の遅延特性を広い周波数帯域で良好に
保つことができる。
In this way, the electromagnetic delay line according to the present invention is constructed by: - Inducting the main negative mutual induction occurring in the conducting line 3 constituting the inductance element into one section's worth of inductance, and dividing it into the coupling coefficients a1 and a2 between the inductance L. By including it, the effect can be suppressed and the coupling coefficient 31 can be made positive, so even if a conventional conducting line 3 is used, delay characteristics such as rise time and output waveform distortion can be maintained in a wide frequency band. can be kept.

そして、本発明の電磁遅延線は、導線路3を用いるので
、厚膜や薄膜等の膜形成技術を応用して構成することか
容易となり、量産性の向上および縮小形化を図ることが
できる。
Since the electromagnetic delay line of the present invention uses the conductive line 3, it can be easily constructed by applying film forming technology such as thick film or thin film, and it is possible to improve mass productivity and reduce the size. .

第6図および第7図は、膜形成技術による構成に適した
本発明の池の実施例を示す断面図であり、上述の第3図
におけるX−X方向での断面構造にて図示しである。
6 and 7 are cross-sectional views showing embodiments of the pond of the present invention suitable for construction using film forming technology, and are not shown in the cross-sectional structure in the X-X direction in FIG. 3 above. be.

第6図に示すものは、アース電極1上に後述する導線路
3の軸方向すなわち仮想線方向に沿って誘電率の高い誘
電体、例えばセラミックからなる幅の狭い誘電体層12
をスパッタリング等によって薄膜形成し、この誘電体層
12の周りのアース電極1上に、例えばガラスを主成分
として誘電体層12より4・、誘電率の低い絶縁ペース
トを印刷。
What is shown in FIG. 6 is a narrow dielectric layer 12 made of a dielectric material having a high dielectric constant, such as ceramic, and extending along the axial direction, that is, the virtual line direction, of the conductor path 3, which will be described later, on the ground electrode 1.
A thin film is formed by sputtering or the like, and an insulating paste containing glass as a main component and having a lower dielectric constant than the dielectric layer 12 is printed on the ground electrode 1 around the dielectric layer 12.

焼成して誘電体層12より厚く、しかも誘電体層12の
上端縁部に乗り上げるように絶縁体層13を厚膜形成し
、これら誘電体層12および絶縁体層13上に導電ペー
ストを上述の第3図の導線路3と同様な形状に印刷して
インダクタンス素子を形成するとともに、導線路3の折
り返し導線14と誘電体層12を挾むアース電極1との
間でコンデンサ9を形成して電磁遅延線を構成している
The insulating layer 13 is fired to form a thick film that is thicker than the dielectric layer 12 and runs on the upper edge of the dielectric layer 12, and a conductive paste is applied on the dielectric layer 12 and the insulating layer 13 as described above. An inductance element is formed by printing in the same shape as the conductor line 3 in FIG. It constitutes an electromagnetic delay line.

なお、誘電体層12は折り返し導線14の中央部で重な
っており、この中央部は誘電体層12が絶縁体層13よ
りも薄くなっているので多少凹陥した形状となるが、イ
ンダクタンス素子の相互誘導にはほとんと影響しないし
、誘電体層12の上端縁部に絶縁体層13が重なってい
るので、導線路3形成時にアース電極1との短絡が生じ
ない0また、アース電極1は、導線路3の形成される領
域に広く形成する必要はなく、例えば第2図に示すよう
に、折り返し導線14を横切るように細長い帯状に形成
してもよい。その場合には図示を省略した基板上に、ア
ース電極1、誘電体層12、絶縁体層13および折れ曲
り導線路3を順次形成すればよい。
Note that the dielectric layer 12 overlaps the folded conductive wire 14 at the center, and since the dielectric layer 12 is thinner than the insulator layer 13 at this center, it has a somewhat concave shape. It has almost no effect on induction, and since the insulating layer 13 overlaps the upper edge of the dielectric layer 12, there is no short circuit with the ground electrode 1 when forming the conductive path 3. It is not necessary to form it widely in the region where the conductive line 3 is formed, and it may be formed in a long and narrow strip shape so as to cross the folded conductive wire 14, as shown in FIG. 2, for example. In that case, the ground electrode 1, the dielectric layer 12, the insulator layer 13, and the bent conductive path 3 may be sequentially formed on a substrate (not shown).

また、第7図は、アース電極1に突出部15を設け、ア
ース電極1上に低誘電率の絶縁ペーストをその突出部1
5か隠れる程度に印刷・焼成して絶縁体層13を厚膜形
成し、この絶縁体層13上に導電性ペーストによって折
り返し導線14の中央部か突出部15に対向するよう導
線路3を形成してなる電磁遅延線を示しているQ この構成の電磁遅延線は、第6図に示す電磁遅延線が絶
縁体層13よりも薄い誘電体層12を用いてコンデンサ
9を形成しているのに対し・誘電率の低い絶縁体層13
を用いて折り返し導線14に向けてアース電極1の一部
をその絶縁体層13中へ突出させ、距離を狭めて折り返
し導線14の中央部にコンデンサ9を形成したものであ
る。第7図の実施例にあっても、アース電照1を細長く
することが可能である。
Further, in FIG. 7, a protrusion 15 is provided on the earth electrode 1, and an insulating paste with a low dielectric constant is applied to the protrusion 15 on the earth electrode 1.
5 is printed and fired to form a thick insulating layer 13, and a conductive line 3 is formed using conductive paste on this insulating layer 13 so as to face the central part of the folded conductive wire 14 or the protrusion 15. The electromagnetic delay line with this configuration is similar to the electromagnetic delay line shown in FIG. Insulator layer 13 with low dielectric constant
A part of the ground electrode 1 is made to protrude into the insulating layer 13 toward the folded conducting wire 14 by using the folded conducting wire 14, and the capacitor 9 is formed in the center of the folded conducting wire 14 by narrowing the distance. Even in the embodiment shown in FIG. 7, it is possible to make the earthing lamp 1 elongated.

また、アース電極1の突出部15の先端に誘電率の高い
材料からなる誘電体層を形成し、第6図および第7図を
一緒に実施することも可能であり、折り返し導線14の
中央部にコンデンサ9がさらに集中して形成されるので
効果的である。
It is also possible to form a dielectric layer made of a material with a high dielectric constant at the tip of the protruding portion 15 of the earth electrode 1, and to perform the steps in FIGS. 6 and 7 together. This is effective because the capacitors 9 are formed in a more concentrated manner.

次に本発明の電磁遅延線を構成するインダクタンス素子
における導線路3の池の実施例を説明i−る0 第8図A−Dは・導線路3を示す平面図である。
Next, an embodiment of the conductive line 3 in the inductance element constituting the electromagnetic delay line of the present invention will be described. FIGS. 8A to 8D are plan views showing the conductive line 3. FIG.

同JAは上述の第3図に示すような導線路3において折
り返し導線4.5.6・・・の中央部にυ1り返し導線
より幅広のコンデンサ電極16を設け、折り返し導線4
.5.6・・・の中央部にコンデンサ力(集中して形成
されるようにしたものである。
The same JA provides a capacitor electrode 16 wider than the υ1 folded conductor wire in the center of the folded conductor wires 4, 5, 6, etc. in the conductor line 3 as shown in FIG.
.. 5. The capacitor force (is formed in a concentrated manner) at the center of 6...

第8図B−Dは折り返し導線4.6.6・・・を軸方向
に対し傾斜をもたせて折り返して形成されており、同図
Bは折り返し導線4.5.6・・・による開口部すなわ
ち連結部7.8・・・の反対側を連結部7.8・・・よ
り狭く形成したものであり、同図へに比べ幅(2W)方
向の寸法およびピッチPが同一であるならば、各インダ
クタンスLの値が増加する一方結合係数a1が減少する
8B-D are formed by folding back the folded conducting wires 4.6.6... with an inclination to the axial direction, and FIG. 8B shows the opening formed by the folded conducting wires 4.5.6... In other words, the opposite side of the connecting part 7.8... is formed narrower than the connecting part 7.8..., and if the dimension in the width (2W) direction and the pitch P are the same as in the same figure, then , the value of each inductance L increases, while the coupling coefficient a1 decreases.

第8図Cは連結部7.8・・が短く、折り返し導線4.
5.6・・・による開口部を連結部7.8・・より広く
形成したもので、同図Aに比べ幅(2W’ )方向の寸
法およびピッチPが同一であるならば、各インダクタン
スLの値が減少し、結合係数81は増加する。
In Fig. 8C, the connecting portions 7.8... are short, and the folded conductors 4.
5.6... is formed wider than the connecting part 7.8..., and if the dimensions in the width (2W') direction and the pitch P are the same compared to A in the same figure, then each inductance L decreases, and the coupling coefficient 81 increases.

さらに第8図D、は、連結部7.8・・・を省略し、折
り返し導v!4・5.6・・・を鋸歯状に形成したもの
であり・同図Cに比べ結合係数31がさらに犬きくなる
Furthermore, in FIG. 8D, the connecting portions 7.8... are omitted, and the folded guide v! 4, 5, 6, etc. are formed into a sawtooth shape.The coupling coefficient 31 is even sharper than that of C in the same figure.

また・本発明にあっては・導線路3を薄く細長い導体で
形成する場合に限らず、榎々の断面形状を有する導体で
形成す為ことか可能であり・導線路3についても平面的
に形成する場合に限らず立体的、例えば断面長方形のボ
ビン外周に貼り付けるように形成することも可能であり
、小形化が容易になる。
Furthermore, in the present invention, the conductive line 3 is not limited to being formed of a thin and elongated conductor, but it is also possible to form it with a conductor having a circular cross-sectional shape. It is not limited to the case where it is formed, but it is also possible to form it three-dimensionally, for example, by attaching it to the outer periphery of a bobbin having a rectangular cross section, which facilitates miniaturization.

一方、導線路3に接続するコンデンサ9も、折り返し導
線4.5.6の各々の中央部に正確に形成する必要はな
く、例えば隣り合う折り返し導線4.5.6・において
交互に逆方向へ中央部からずれた千鳥状に形成してもよ
く・多少結合体% a 1が小さくなるが、本発明の目
的達成が可能であり、コンデンサ9を接続する位置は所
望の遅延特性に応じて調節すればよい。なお、アース電
極1もコンデンサ9.を形成する位置に対応させて種々
のパターン形状にすればよい。
On the other hand, the capacitors 9 connected to the conductor line 3 do not need to be formed precisely in the center of each folded conductor 4.5.6, but are alternately formed in opposite directions in adjacent folded conductors 4.5.6. It may be formed in a staggered manner offset from the center. Although the combined body % a 1 becomes somewhat smaller, the purpose of the present invention can be achieved, and the position where the capacitor 9 is connected can be adjusted according to the desired delay characteristics. do it. Note that the ground electrode 1 is also connected to the capacitor 9. Various pattern shapes may be formed depending on the position where the pattern is formed.

以上説明したように本発明の電磁遅延線は、折れ曲り導
線路における折り返し導線すなわち折れ曲り導線路の幅
方向の導体途中にコンデンサを接続し・その導体途中で
隣り合う区間に分割してなるので・遅延特性を良好に保
つことが可能で小形fヒも容易となる。
As explained above, the electromagnetic delay line of the present invention is constructed by connecting a capacitor midway through the folded conductor in the bent conductor, that is, the conductor in the width direction of the bent conductor, and dividing the conductor into adjacent sections midway. - It is possible to maintain good delay characteristics, and it is easy to create a small f-hi.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の電磁遅延線を示す斜視図、第2図〜第4
図は本発明の電磁遅延線の一実施例を示す斜視図、概略
平面図および等価回路図、第5図は第2図の電磁遅延線
における隣り合う区間の結合状態を示す図、第6図およ
び第7図は本発明の池の実施例を示す断面図、第8図は
インダクタンス ス素子を構成する折れ曲り導≠路の他の実施例を示す平
面図である。 1・・・・・アース電極、2・12・・・・・・誘電体
層、3・・・折れ曲り導勝路・4・5・6.14・・・
・・七fり返し導線、7.8・・・・連結部、9・・・
・コンデンサ、10.11・・・・・ コ字形の導線部
・13・・・・・絶縁体層・15・・・・突出部特許出
願人 エルメック株式会社 第1ヅ オ 2 圃 A′3  逆 オ、4 圃 オ 5 逆 オ 6 逆 オ 7 蔓
Figure 1 is a perspective view showing a conventional electromagnetic delay line, Figures 2 to 4
The figures are a perspective view, a schematic plan view, and an equivalent circuit diagram showing one embodiment of the electromagnetic delay line of the present invention, FIG. 5 is a diagram showing the coupling state of adjacent sections in the electromagnetic delay line of FIG. 2, and FIG. FIG. 7 is a sectional view showing an embodiment of the pond of the present invention, and FIG. 8 is a plan view showing another embodiment of the bent conductive path constituting the inductance element. 1... Earth electrode, 2.12... Dielectric layer, 3... Bent guide path, 4, 5, 6.14...
...7F repeating conductor, 7.8...Connection part, 9...
・Capacitor, 10.11... U-shaped conducting wire part ・13...Insulator layer ・15...Protrusion part Patent applicant Elmec Co., Ltd. No. 1 Zuo 2 Field A'3 Reverse O, 4 Field O 5 Reverse O 6 Reverse O 7 Vines

Claims (5)

【特許請求の範囲】[Claims] (1)折れ曲り導線路と、この導線路とアース間に接続
されたコンデンサとを具備し、複数の区間を有する電磁
a延線において、前記コンデンサが、前記導線路中の幅
方向の導体の途中に接続され、この導体の途中で隣り合
う区間に分割されてなることを特徴とする電磁遅延線。
(1) In an electromagnetic line having a plurality of sections, comprising a bent conductive line and a capacitor connected between the conductive line and the ground, the capacitor is connected to the conductor in the width direction of the conductive line. An electromagnetic delay line characterized by being connected in the middle and divided into adjacent sections in the middle of this conductor.
(2)  コンデンサが、幅方向の各導体の中央を横切
る仮想緋上に配置されてなる特許請求の範囲第1項記載
の電磁遅延線。
(2) The electromagnetic delay line according to claim 1, wherein the capacitor is arranged on a virtual line that crosses the center of each conductor in the width direction.
(3)  コンデンサが、幅方向の各導体の中央を横切
る仮想林に対し交互に逆方向にずれた位置に配置されて
なる特許請求の範囲第1項記載の電磁遅延線。
(3) The electromagnetic delay line according to claim 1, wherein the capacitors are arranged at positions alternately shifted in opposite directions with respect to a virtual forest that crosses the center of each conductor in the width direction.
(4)折れ曲り導線路が、絶縁体層上に形成されるとと
もに、コンデンサが、アース電極上に前記絶縁体層より
高い誘電率を有しかつ薄く形成された誘′亀体層に前記
導線路の幅方向の導体を重ねて形成されてなる特許請求
の範囲第1項〜第3項いずれか1項記載の電磁遅延線。
(4) A bent conducting path is formed on the insulating layer, and the capacitor is connected to the conducting wire on the ground electrode on a dielectric body layer having a higher dielectric constant than the insulating layer and formed thinner. An electromagnetic delay line according to any one of claims 1 to 3, which is formed by overlapping conductors in the width direction of the path.
(5)折れ曲り導線路か、絶縁体層上に形成されるとと
もに、コンデンサが、前記導線路の幅方向の導体に向け
てアース電極の一部を前記絶縁体層中へ突出して形成さ
れてなる特許請求の範囲1項〜第3項いずれか1項記載
の電磁遅延線0
(5) A bent conductive line is formed on the insulating layer, and a capacitor is formed with a part of the ground electrode protruding into the insulating layer toward the conductor in the width direction of the conductive line. The electromagnetic delay line 0 according to any one of claims 1 to 3
JP1852483A 1983-02-07 1983-02-07 Electromagnetic delay line Granted JPS59144204A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1852483A JPS59144204A (en) 1983-02-07 1983-02-07 Electromagnetic delay line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1852483A JPS59144204A (en) 1983-02-07 1983-02-07 Electromagnetic delay line

Publications (2)

Publication Number Publication Date
JPS59144204A true JPS59144204A (en) 1984-08-18
JPH0451081B2 JPH0451081B2 (en) 1992-08-18

Family

ID=11974014

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1852483A Granted JPS59144204A (en) 1983-02-07 1983-02-07 Electromagnetic delay line

Country Status (1)

Country Link
JP (1) JPS59144204A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05327325A (en) * 1992-05-15 1993-12-10 A T R Koudenpa Tsushin Kenkyusho:Kk Microwave slow-wave circuit
EP1723690B1 (en) * 2004-03-09 2011-11-02 Telefonaktiebolaget LM Ericsson (publ) An improved tuneable delay line
WO2013156058A1 (en) * 2012-04-17 2013-10-24 Telefonaktiebolaget L M Ericsson (Publ) Tunable delay line arrangement
US20150229287A1 (en) * 2014-02-12 2015-08-13 Taiwan Semiconductor Manufacturing Co., Ltd. Device For Blocking High Frequency Signal And Passing Low Frequency Signal
WO2020157804A1 (en) * 2019-01-28 2020-08-06 日本電業工作株式会社 Transmission line and phase shifter

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05327325A (en) * 1992-05-15 1993-12-10 A T R Koudenpa Tsushin Kenkyusho:Kk Microwave slow-wave circuit
EP1723690B1 (en) * 2004-03-09 2011-11-02 Telefonaktiebolaget LM Ericsson (publ) An improved tuneable delay line
WO2013156058A1 (en) * 2012-04-17 2013-10-24 Telefonaktiebolaget L M Ericsson (Publ) Tunable delay line arrangement
US9478844B2 (en) 2012-04-17 2016-10-25 Telefonaktiebolaget Lm Ericsson (Publ) Tunable delay line arrangement
US20150229287A1 (en) * 2014-02-12 2015-08-13 Taiwan Semiconductor Manufacturing Co., Ltd. Device For Blocking High Frequency Signal And Passing Low Frequency Signal
US9628041B2 (en) * 2014-02-12 2017-04-18 Taiwan Semiconductor Manufacturing Co., Ltd. Device for blocking high frequency signal and passing low frequency signal
US9905897B2 (en) 2014-02-12 2018-02-27 Taiwan Semiconductor Manufacturing Co., Ltd. Device for blocking high frequency signal and passing low frequency signal
WO2020157804A1 (en) * 2019-01-28 2020-08-06 日本電業工作株式会社 Transmission line and phase shifter
JPWO2020157804A1 (en) * 2019-01-28 2021-11-11 日本電業工作株式会社 Transmission line and phase shifter

Also Published As

Publication number Publication date
JPH0451081B2 (en) 1992-08-18

Similar Documents

Publication Publication Date Title
JP3120682B2 (en) Chip type filter
WO2001045207A1 (en) Microstrip antenna
US3609600A (en) Distributed parameters delay line,on folded support
JPH0481890B2 (en)
US20030025573A1 (en) Electromagnetic delay line with improved impedance conductor configuration
JPS59144204A (en) Electromagnetic delay line
JP6800181B2 (en) Resonator and filter
JPWO2005043750A1 (en) Electromagnetic delay line inductance element
JPS62200713A (en) Integrated capacitor
JPS6243909A (en) Resonator and filter using it
US6496710B1 (en) Signal filter having circularly arranged resonators
JP7115117B2 (en) LC filter
JPH0219013A (en) Electromagnetic delay line
JP3591806B2 (en) Inductor
US9620289B2 (en) Ceramic capacitor for suppressing high-frequency noise
JPH0223041B2 (en)
JP2903112B2 (en) Connection method of cross type microstrip line
US4583062A (en) Electromagnetic delay line having a coil with divergent adjacent turns
JPH0238012B2 (en)
JP2020171066A (en) Resonator and filter
JPS607201A (en) Electromagnetic delay line
JPH0211169B2 (en)
JPH0476906A (en) Noise filter
JPS5921522Y2 (en) Lumped constant circulator
JPH055201B2 (en)