JPH04167703A - Delay line - Google Patents

Abstract

PURPOSE:To attain miniaturization of delay line without sacrificing its high frequency characteristic by forming the width of a strip conductor in close approach to the edges of a dielectric layer wider than that of the strip conductor not in close to the edge. CONSTITUTION:A strip conductor 2 is formed in a meandering shape by using a conductive material and a conductor width W1 of both ends 2a and a folded part 2b close to the edge of a dielectric layer 1 is formed wider than a conductor width W2 of a straight line part 2c in the middle not close to the edge. Thus, even when the distance between the end of the dielectric layer 1 and the strip conductor 2 is decreased to attain miniaturization, the reduction in the capacitance attended with the distance made short is compensated by the increase in the conductor width of the strip conductor 2. Thus, the characteristic impedance is uniformized entirely even when miniaturization is implemented and the small distribution constant type delay lime with an excellent high frequency characteristic is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a delay line used for delaying signal transmission in computers, measuring instruments, and the like.

Disaster ■One type of limb distortion delay line is a distributed constant type. This delay line is shown in Figure 4 (plan view) and Figure 5.
As shown in FIG. A so-called microstrip having a ground conductor 13 formed on the surface thereof is used, and a structure in which the delay time is determined by the length of the strip conductor 12 is known.

Further, as another delay line, one having the structure shown in FIG. 6 is also known. This is an example of a structure in which the structures shown in FIG. 4 described above are laminated, and a strip conductor 15 is formed between two dielectric layers 14. Ground conductor 16 on the outer surface.
16 are formed.

Such miniaturization of the delay line generally requires reducing the width of the dielectric layers 11 and 14, and also reducing the width of the strip conductor 1.
This is done by bending 2 or 15 and making it meander.

By the way, when the above-mentioned miniaturization was attempted, the following problems occurred. That is, as shown in FIG. 7, when the ground conductor 13 (or 16) is small, the end of the meandering strip conductor 12 (or 15), that is, the portion close to the edge of the dielectric layer 11 Since the grounding conductor 13 (or 16) is close to the end, the capacitance becomes smaller than the center part away from the end, and the characteristic impedance becomes larger, resulting in a problem that the characteristic impedance is not constant in the high frequency range. In addition, the locations where the characteristic impedance becomes large include not only the ends of the meandering strip conductor 12 (or 15) but also all locations close to the edges of the dielectric layer 11, such as bent portions, etc. There is.

In order to solve this problem, the area of the ground conductors 13 and 16 should be made infinitely large, but this is not possible considering the above-mentioned miniaturization, and as shown in FIG. Since the distance a from the strip conductor 12 to the strip conductor 12 was set to be long enough, as a result, sufficient miniaturization could not be achieved.

The present invention has been made to solve such problems,
The purpose of this invention is to provide a distributed constant type delay line that is small and has good high frequency characteristics.

The present invention provides a delay line in which a strip conductor and a ground conductor are formed with a dielectric layer in between, and the strip conductor is close to the edge of the dielectric layer. It is characterized in that it is formed with a conductor portion in part, and that the conductor portion is wider than other conductor portions.

In the present invention, the width of the strip conductor portion close to the edge of the dielectric layer is made wider (formed) than the width of the strip conductor portion that is not close, so the distance a can be shortened to achieve a compact size. Even if the strip conductor portion of the former is made larger, the capacitance generated between the strip conductor portion and the ground conductor can be increased, and therefore the capacitance generated between the strip conductor portion of the latter portion and the ground conductor can be made almost equal to the capacitance generated between the strip conductor portion and the ground conductor. The characteristic impedance also becomes uniform throughout.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings. 1st
The figure is a plan view showing one embodiment of the delay line according to the present invention, and FIG. 2 is a cross-sectional view taken along the line ■--■ in FIG. 1. In the figure, reference numeral 1 denotes a dielectric layer made of a dielectric substrate formed into a rectangular plate shape, for example, and a strip conductor 2 is disposed on one surface of the dielectric layer 1 (upper side in the figure), and a strip conductor 2 is placed on the surface of the other side (lower side in the figure). ) is formed with a ground conductor 3 on its surface.

The strip conductor 2 is formed, for example, in a meandering shape using a conductive material, and has a portion close to the edge of the dielectric layer 1;
For example, the conductor width W1 at both end portions 2a and the bent portion 2b is not wider than the conductor width W2 at a portion that is not close to each other, for example, the central straight portion 2C.

On the other hand, the ground conductor 3 on the lower side of the dielectric layer 1 is formed on the entire lower surface of the dielectric layer 1 using, for example, a conductive material.

Therefore, in the delay line configured in this way, the conductor width W1 at both end portions 2a and bent portions 2b that are close to the edge of the dielectric layer 1 is made wider than the conductor width W2 at the center straight portion 2C that is not close to the edge. Therefore, even if the distance a shown in FIG.
The capacitance generated between the ground conductor 3 and the ground conductor 3 can be increased,
Therefore, the grounding conductor 3 is
This can be approximately equal to the capacitance generated between Therefore, even if the distance a is shortened in order to achieve downsizing, the decrease in capacity due to the shortening of the distance a can be compensated for by increasing the conductor width of the strip conductor 2. Characteristic impedance can be made uniform throughout. Note that the dimension of the conductor width W1 may be set to an appropriate value depending on the characteristic impedance at the straight portion 2C having the conductor width W2.

Although the above embodiment is applied to a single layer structure in which there is one dielectric layer 1 sandwiched between the strip conductor 2 and the ground conductor 3, the present invention is not limited to this. Of course, the present invention can also be similarly applied to a laminated structure having a plurality of layers 1.

FIG. 3 illustrates a case where there are four dielectric layers 1 sandwiched between strip conductors 2 and ground conductors 3. In FIG.

Moreover, what is shown in FIG. 3 is an embodiment in which the present invention is applied to a laminated structure.

Further, in the above embodiments, the case where the strip conductor is meandering has been described as an example, but the present invention is not limited to the case where the strip conductor is meandering.
It is similarly applicable to a structure in which a portion is formed in a spiral or meandering shape, or in other words, a structure in which at least a portion of the structure has a portion close to the edge of the dielectric layer.

Highlights - Bundle As described in detail above, in the case of the present invention, the width of the strip conductor portion close to the edge of the dielectric layer is formed wider than the width of the strip conductor portion not close to the edge, so that miniaturization is achieved. The capacitance generated between the former strip conductor portion and the ground conductor can be increased, and the capacitance generated between the latter strip conductor portion and the ground conductor can be made almost equal to the capacitance generated between the latter strip conductor portion and the ground conductor, thus sacrificing the characteristic impedance in the high frequency range. This has the effect of making it possible to reduce the size without causing any problems, and also making the characteristic impedance uniform throughout.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing an embodiment of the delay line according to the present invention, FIG. 2 is a sectional view taken along the line ■-■ in FIG. 1, and FIG.
The figure is a sectional view showing another embodiment of the present invention, FIG. 4 is a plan view showing a conventional delay line, and FIG. 5 is a cross-sectional view showing a conventional delay line.
6 is a perspective view showing another conventional example, and FIG. 7 is a diagram for explaining the problems of the conventional method. 1... Dielectric layer, 2... Strip conductor, 2a...
-Both ends, 2b...bent part (both conductor parts close to the edge of the dielectric layer), 2c... straight part (conductor part not close), 3... ground conductor. Patent applicant Murata Manufacturing Co., Ltd. 8 Figure 4 Figure 6 Figure 7 Figure 5 Figure 13 (ma is 16)

Claims (1)

[Claims] (1) In a delay line in which a strip conductor and a ground conductor are formed with a dielectric layer in between, the strip conductor is formed with a part of the conductor portion close to the edge of the dielectric layer, and the conductor A delay line characterized by having a conductor part wider than other conductor parts.