JPS6026237B2 - Display blinking control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display blinking control method that allows a display to blink in a display device that displays a display for each of a plurality of addresses using digital data.

For example, in a stock price display device, stock prices are displayed for each of a large number of stocks on a large display board.

It has been proposed that this display be performed using a digital numeric light-emitting display element. In this way, when many display parts of a display unit, for example, parts that display the stock price of each stock, are arranged on one display panel, there are many displays even if the display is simply changed for each stock due to stock price fluctuations. Therefore, it is difficult to notice which stocks' stock prices have changed. Therefore, it has been proposed that the changed display be made to blink for a certain period of time after the change to notify the user of the change.
In order to blink the display in this type of display device, a blinking timer and a blinking control circuit are provided for each display portion of the display unit.

Therefore, in a display device having a large number of display parts,
The disadvantages are that the number of components for the blinking display increases, the overall price increases, and reliability decreases. This invention focuses on the average output time of display data to the display unit and the blinking time of the display unit, assumes the number of pieces of display data that will arrive in the average output time within the blinking time, and provides buffer memories of this assumed number. The display unit blinks by controlling the sending of data in this buffer memory, and the blinking timer and blinking control circuit for each display part of the display unit are removed, thereby providing an economical and rational display blinking control device. It provides:

In the display blinking control system of the present invention, when display data is received, the display data is first saved in the first register.

This saving is done because the second register, which is specially provided to perform display blinking control, transfers the received data, and when the received display data cannot be transferred to the second register, it is transferred to the receiving display unit. This is because it is carried out next. The received display data saved in the first register is processed as follows. Only when there is space in the second register to write display data, or when there is display data in the second register that matches the address part (indicating the brand in the stock price display above) of the display data in the first register, The contents of the first register are transferred to the vacant position of the second register or the part with the matching address; otherwise, it is assumed that the blinking scheme is not possible and is transferred to the display unit without being transferred to the second register. . The contents of the second register transferred from the first register are read by a timer that operates in a cycle consisting of a lighting period and a darkening period, and the displayed display data is converted as is) or into dimming data. Then, the data is transferred to the corresponding address of the display unit, and this direct transfer and the transfer of the light-off data are performed alternately to provide a blinking display. Next, an embodiment of the display blinking control method according to the present invention will be described with reference to the drawings.

The display data shown in FIG. 2 is input to the signal line a in the upper left corner of FIG. The display data consists of a display unit address AD such as a stock, followed by data DT such as the stock price of the stock to be displayed. For example, the address AD is 8.
The data DT is composed of 1 character of bits, and the data DT is composed of 15 characters of 8 bits. The transmission time of one display data block consisting of the display unit address AD and data DT is y, and the transmission time for one display data block consisting of the display unit address AD and data DT is y, and the transmission time for one display data block consisting of the display unit address AD and data DT is y,
The time interval with the display data is T. For example, average arrival interval Tm=0.5 seconds, y. =80 inputs outside the display data. Address A in the input display data of signal line a
A signal indicating that it is a character part of D is connected to the signal line P,
Then, signals indicating character portions of address AD and data DT are respectively applied to signal line P2.
Indicating that the signal line P, is an address character,
The address character of signal line a is stored in an address register 9 connected to signal line a. Further, when the signal line P2 indicates the address AD and data DT, all characters of the address AD and data DT are stored in the first register 1 connected to the signal line a. On the other hand, signal line P
When the reception control circuit 4 connected to the control circuit 2 detects the reception of one display data block by, for example, the counting operation of a counter, the detection output is transmitted to the control circuit 5 through the signal line g. The control circuit 5 searches the contents of the second register 2 based on the lighting signal e and blinking signal f from the timer 3.

A plurality of display data blocks are stored in the second register 2, as shown in FIG. 3, and a control character CNT is added to the beginning of one display data block shown in FIG. 2 for storage. The control character CNT indicates whether or not the area of the address AD and data DT following CNT is empty or not, and the area of address AD and data DT that follows CNT is to be flashed. The lighting signal e from the timer 3 has a period of 2 as shown in FIG. Indicates the time to be transferred to the thigh display unit, and the castle light signal f is the lighting signal e and the next lighting signal e.
It is located midway between the two registers, has a period 73, is repeated at a cycle of T, 10T2, and converts one display data block from which the second register 2 is read out to a data block that turns off on the display unit. indicates the time to transfer.

The period from the leading edge of the lighting signal e to the leading edge of the next lighting signal f is the lighting period, and the period from the leading edge of the wave lighting signal f to the leading edge of the next lighting signal e is the lighting period. T2, and these are T
,, T2 is maintained for 0.9 seconds, for example. The contents of the second register 2 are searched for periods other than the lighting signal e and the dimming signal f. That is, the read counter 14 is set to all 0s by the output signal line n of the control circuit 6, and the switching gate 7 is set to all 0s by the signal line m.
The output of the read counter 14 passes through the gate 7, and the output line x of the read counter 14 is switched to the output Q side of the second register 2.
Give the Suzudashi address to . Furthermore, the control circuit 5 provides an offer signal to the second register 2 via the signal line y. Therefore, the contents of address 0 (C
NT) is read. Specific bits of the control character CNT, for example, 8 bits, are the next address AD, and when the data DT area has finished blinking control or has not been written at all, it is “
Therefore, when the control circuit 5 detects that the 8th bit is "0" based on the output c of the second register 2, the address AD and data DT areas are regarded as empty, and the read counter 14 The contents of are stored in the empty address register 12 through the signal line Q, and read counter 1
4 is increased to 116 to set the address of the next control character CNT. Control character C taken from second register 2
If the 8th bit of NT is "1", it is assumed that the address AD and data DT area are valid, and the read counter 14 is set to 11, thereby setting the address AD stored at the next address of CNT to the second address. The data is read from register 2, and compared with the contents of address register 9 by comparison circuit 10'.

When the two match, the output line j of the comparator circuit 10 is connected to the control circuit 5.
The control circuit 5 instructs the read counter 14 to
The contents minus 1 from the contents at that time, that is, the CN at that time
The storage address of T is stored in the matching address register 1, and then the contents of the read counter 14 are incremented by 115, and the address of the next CNT character is set in the counter 14. Such operations are performed until the last CNT and AD regions. C.N.T., A.D.
If the data is one area, then, for example, two portions of this area are provided in the second register 2. When such a search operation is completed, the control circuit 5 controls the comparator circuit 10 during the search operation.
If there is a match signal from , the contents of the match address register 11 are set to the write counter 13 via the signal line 6, and if there is no match signal but there is an empty address, the contents of the empty address register 2 are set to the write counter 13 by the signal line 6. is set to

If there is neither a vacant address nor a matching address, the contents of the first register 1 are input to the drive circuit 15 through the switching gate 8, and output to the display unit via the output line v of the drive circuit 15.
When a matching address or a vacant address is set in the write counter 13, this address is given as an address to the second register 2 through the switching gate 7, and the number of blinks, for example, 10 in binary, is written to the 1st to 7th bits of that address. to 8 bits “
1” is set through the signal line k of the switching gate 6,
In other words, CNT is stored, and after that, the write counter 13 increments by 11, and through the switching gate 6, the first register 1
The contents of are transferred to the second register 2. Next, the operation of the second register 2 at times ↑2 and 73 (see FIG. 4) of the signals e and f from the timer will be explained.

When the lighting signal e from the timer reaches time 72, the read counter 14 is first set to all "0"s, and address 0 of the second register 2 is read out. A CNT character is written at address 0.

If the 8th bit of the content discussed is 1, the next address A
D. The registers DT are sequentially set, and the drive circuit 15 is operated as is.
output to the display unit through the output v of. However, before reading address AD and register DT, the contents of the first to seventh bits of the CNT character are decremented by 1, and the contents become “0.”
”, “0” is written to the 8th bit, and when the content is not “0”, “1” is written to the 8th bit, and the contents subtracted by 1 are written to the 1st to 7th bits. Furthermore, when the turn-off signal f from the timer reaches time 73, the same operation as the turn-on signal e from the timer reaches time 72 is performed, but the second
All or part of the data area of the register 2 is converted into data that causes the display unit to turn off, for example, all "1", and is outputted by the switching gate 8. The operation of both the lighting signal e and the dimming signal f from the timer ends when the second register 2 is output from address 0 to the last address. In this way, the display to be blinked is displayed blinking by the lighting signal e and the dimming signal f, and this control is commonly used for each display unit. This blinking display time is determined by the number of the first to seventh bits set in CNT, and after that time, the storage area of the display data block is considered empty. Although the outline of the operation has been described above, the operations of the first register and the second register can be easily executed using a microcomputer or the like. Next, the operation of the main parts shown in FIG. 1 will be explained with reference to the drawings.

FIG. 5 shows a time chart of timing pulses used to explain the logic circuit diagrams of FIGS. 6 to 8. Timings L to t and 6 in FIG. 5 are pulses that are sequentially shifted in time. FIG. 6 shows an example of the reception control circuit 4 in FIG. 1, in which the signal line P2 is connected to the signal line P2 in FIG. 1, and the number of write pulses on the signal line P2 is counted by a 16-ship counter A2. and when its count reaches 16, its output is gated by AND gate A3 with a timing pulse t, setting flip-flop A5. The output line g of flip-flop A5 corresponds to the signal line g in FIG. When the signal on the output line g of the flip-flop A5 becomes "1", the 1 mirror counter is reset by the signal gated by the timing pulse and the like by the AND gate. The input signal m is a flag signal that is set when the output line g of the flip-flop A5 becomes "1", and is generated as shown in FIG. 7, which will be explained next. Signal m is gated by a band gate with timing pulse t4 to set flip-flop A5. FIG. 7 shows a search control portion of the second register control circuit 6 of FIG.

Signals e and f correspond to signals c and f in FIG. 1, and signal g corresponds to the signal on signal line g in FIG. 6 (hereinafter, signals on signal lines are indicated by the same symbols as the signal lines). The signal g is a logical value “
1", the lighting signal e and the lighting signal f from the timer
When the logic value is "0", the flip-flop A8 is set by the timing pulse W by the gate A7. When the flip-flop is set, the band gate opens and the flip-flop A, at timing pulse t3.
is set. Flip-flops A and o are flag flip-flops for performing a search operation, and their set output is a signal m. Flip-flop A8 is “1”
”, the read counter clear signal n is generated by the AND gate only while the flip pins A and . are “0”. The signal n corresponds to the signal n in FIG.
This corresponds to the signal m in the figure, and the contents of the read counter 14 are
This is a signal to be given as the address of register 2.
Flip Flop A. When the AND gate A.2 is set, the AND gate A.2 opens, and the timing pulse that passes through it causes the talk signal P4 of the second register 2 to be output to the OR gate A.2. It is given through 3. The eighth bit of the output of the second register 2 is applied as an input signal C to this control circuit 5.

If the signal C is ``0'', inverters A, 4, AND gates A, 5, AND gates A, 6 are sequentially opened, and the timing pulse hi passes through gates A, 6, and the contents of the read counter 14 of the second register 2 are read. A signal Q for transferring the address to the empty address register 12 is output.
is opened by the output of gate A5, and the gate A, the 7th timing pulse, etc. pass through, and the read counter 14 of the second register 2
A signal P5 for multiplying by 116 is output. Signal C is “
1'', gates A and 9 are opened through AND gate A and 9, and the timing pulses pass through this, and a signal P6 for incrementing the read counter 14 of the second register 2 is output. AND gate A2 with the output of 8,
opens, the timing pulses pass through gates A, 3, and the output signal P4 of the second register 2 is output.
Furthermore, an AND gate is formed by the outputs of gates A and 3. opens, timing pulses and the like pass through this, and a gate signal P7 for comparing the output of the second register 2 and the contents of the Andres register 9 is output. Flip-flop 3 is a control flag flip-flop for detecting the control character CNT (see Figure 3) of the second register 2, and gate A is opened by the outputs of gates A and 6, and the signal passes through gate A22. It is set by the timing pulse et al. Flip-flop o is a flag flip-flop indicating that the second register 2 has at least one empty area for one display data.

The AD character of the second register 2 and the contents of the address register 9 are compared by the output signal P7, and when the contents match, the input signal i becomes "1". When the input signal i becomes "1", the (pulse) flag flip-flop 5 is set, and the AND gate A26 is opened by the set output, and a matching address is detected by the timing pulse t8 that passes through this. Flag flip-flop A2 indicating
9 is set. When flip-flop A is set, AND gate A opens, and the timing pulses that pass through this register subtract 1 from the contents of the read counter 14 in the second register (the address of the CNT character in Figure 3) to the match register. A signal P8 for transfer to 11 is output. Furthermore, the set output of the flip-flop A25 opens the AND gate A, and the timing pulse t9 that passes through it sets the read counter 14 of the second register to 115.
A signal P9 for this purpose is output. A32 is a counter for performing the search operation 20 times, and when the count reaches 21, the outputs P and o become 1. Input P, 5 is a signal output from FIG. 8, which is generated when the transfer operation flag following the search operation is set. Figure 8 is the second part of Figure 1.
A portion of the register control circuit 5 that transfers the contents of the first register 1 is shown.

Input signals P and o are generated from the power detector 2 in FIG. 7 when the search operation is completed. The signals P and o open the AND gate 6, and the timing pulse t... that passes through it,
Set flip-flop 7. Input P, . ,P,
2, P, 3, P, 4 are the flip flops in Figure 7,
When the flip-flop 7 is set, the signals P, . If a character matching the received address AD exists in the second register 2 in the search operation due to the state of ~P, 4, the timing pulse t8 passes through the AND gate A crab, and the contents of the matching address register 11 in FIG. Signals P and 6 are generated to be transferred to the write counter 13 in FIG. Also, if there is an empty area in the second register 2 during the search operation, the AND gate 5
opens, and at the timing pulse t・2 that passes through this, the first
Signals P and 7 are generated to transfer the contents of the empty address register 12 shown in the figure to the write counter 3 shown in FIG. Furthermore, if there is no character or empty space in the second register 2 that matches the received address AD in the search operation, the AND gate A46 opens and the timing pulse et al.
Is there a flag flip-flop for supplying the contents of the first register in the figure to the drive circuit 15? is set. When the flip-flop A47 is set, its output opens the AND gate A48, generating a signal that switches the switching gate 8 in FIG. is opened, and the timing pulses that have passed through it are used to register the first register 1 in Figure 1.
A signal P,8 is provided for providing the output of the signal P,8 to the drive circuit 15.

Also, the output of the gate A tooth opens the AND gate A5, and the timing pulse t3 that passes through it changes the signals P and 6 to 1.
A counter pulse is generated to generate a needle fixation, and the 17-decimal counter A spot counts up. Furthermore, outputs P and 9 of AND gate 2 are signals for reading the first register 1 in FIG. 1, and output P2o of AND gate A43 is a signal for incrementing the read counter of the first register 1 in FIG. be.
Output P2 of AND gate A5o. is a signal for applying the output of the write counter 13 shown in FIG. 1 to the output x of the switching gate 7. The output P22 of the band gate 2 passes through the timing signal t, 3 and becomes the character CN in Fig. 3.
This is a signal for writing T into the second register 2 in FIG. 1, and the output P23 of the AND gate 8 is a signal for writing data DT in FIG. 3 into the second register 2 in FIG. be. The output P of the band gate 4 is the timing pulse t.
, 4 is a signal for incrementing the write counter 13 in FIG. The output P of the or gate A57 is 16 ships when the counter A55 becomes 16.
Or “1” when hexadecimal counter A56 reaches 17
This is the signal.

When the output P25 becomes "1", the flip-flop A is reset by the timing pulse t4 by the AND gate A59, and the transfer operation of the first register is completed. The main parts of the reception control circuit 4 and second register control circuit 5 shown in FIG. 1 have been explained above. However, since the operation of the second register 2 by the timer 3 of the second register control circuit 5 can be configured in the same manner as described above using the same logic using timing pulses, a description thereof will be omitted. As explained above, by providing the first register, this invention can transmit the received display data to the display unit without losing it when blinking control is not possible, and furthermore, the data stored outside the second register can be operated by a timer. By doing so, the blinking control circuit and timer for each display unit can be removed, and rational and economical blinking control can be performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the blinking display control method according to the present invention, FIG. 2 is a diagram showing an example of the display data input format of FIG. 1, and FIG. 3 is a block diagram showing an example of the display data input format of FIG.
A diagram showing an example format when stored in a register,
Fig. 4 is a time chart of a timer signal for controlling blinking by operating the second register, Fig. 5 is a time chart of timing pulses for controlling each part of Fig. 1,
6 is a logic circuit diagram showing an example of the reception control circuit of FIG. 1, and FIGS. 7 and 8 are logic circuit diagrams showing specific examples of a part of the second register control circuit 5 of FIG. 1, respectively. be. 1...First register, 2...Second register, 3...Timer, 4
...Reception control circuit, 5...Control circuit, 6, 7, 8...Switching gate, 9...Andres register, 10...Comparison circuit, 1 1...Match address register, 12...Empty address register , 13... Write counter, 14... Read counter, 15... Drive circuit. Diagram O2 Diagram Ice 3 Diagram Om Diagram Diagram Bo Diagram

Claims (1)

[Claims] 1. In a display blinking control method in which a plurality of display data consisting of a plurality of types of addresses and data are input, transferred to a display unit, and displayed at a position corresponding to the address, register means for storing a plurality of display data; a timer means for alternately outputting a lighting signal having a predetermined period and a dimming signal having a period substantially the same as that of the lighting signal and whose phase is shifted to approximately an intermediate position between adjacent lighting signals, and the lighting signal; and control means for reading the display data stored in the register means during the sending period of the lighting signal, and supplying the display data read during the sending period of the lighting signal to the corresponding address position of the display unit as lighting data. to turn on the display, convert the display data read during the sending period of the light-off signal to light-off data, and supply the data to the corresponding address position of the display unit to turn off the display. a display blinking control method, characterized in that the display data is displayed blinking at the corresponding address position of the display unit at the predetermined period in which the blinking can be visually confirmed.