JPS60261141A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS60261141A
JPS60261141A JP11794884A JP11794884A JPS60261141A JP S60261141 A JPS60261141 A JP S60261141A JP 11794884 A JP11794884 A JP 11794884A JP 11794884 A JP11794884 A JP 11794884A JP S60261141 A JPS60261141 A JP S60261141A
Authority
JP
Japan
Prior art keywords
contact hole
oxide film
bored
edge section
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11794884A
Other languages
Japanese (ja)
Inventor
Hiroaki Ootani
大谷　博晃
Akira Kanzawa
神沢　公
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP11794884A priority Critical patent/JPS60261141A/en
Publication of JPS60261141A publication Critical patent/JPS60261141A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To equalize the thickness of an evaporating metal such as a wiring conductor formed to a bored edge section in a contact hole shaped to an oxide film, and to prevent a disconnection at a stepped section of the evaporating metal by forming the bored edge section in a tapered manner. CONSTITUTION:A resist layer 16 is shaped to an oxide film 14 formed on the surface of a semiconductor substrate 12, and a contact hole 18 is bored selectively to the oxide film 14 through etching treatment while using the resist layer 16 as a mask. The contact hole is etched and treated again under conditions in which the selection ratio of the oxide film 14 and the resist layer 16 is increased. Consequently, a section shown in a broken line 20 is removed through etching treatment, and a tapered surface 22 is shaped at the bored edge section of the contact hole 18 in the oxide film 14. When the tapered surface 22 is formed at the bored edge section of the contact hole 18, an evaporating metal such as a wiring conductor shaped while coating the bored edge section can be formed in uniform thickness.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、配線導体など金属蒸着部分のいわゆる段切
れを防止した半導体装置およびその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same, which prevent so-called breakage of metal vapor deposited parts such as wiring conductors.

　− 〔従来の技術〕 第２図は従来の半導体装置におけるコンタクトボールの
形成およびその部分への配線導体の形成状態を示してい
る。- [Prior Art] FIG. 2 shows the formation of a contact ball and the formation of a wiring conductor in the contact ball in a conventional semiconductor device.

第２図（Ａ）において、シリコン基板２の表面に形成さ
れた酸化膜′４にレジスト層６を堆積し、このレジスト
層６をマスクとして酸化膜４にコン　□″タクトホール
８形成する場合、リアクティブイオンエツチング（ＲＩ
　Ｂ）などの異方性エツチング処理によって行われる。In FIG. 2(A), when a resist layer 6 is deposited on the oxide film '4 formed on the surface of the silicon substrate 2, and a contact hole 8 is formed in the oxide film 4 using this resist layer 6 as a mask, Reactive ion etching (RI)
This is done by an anisotropic etching process such as B).

この場合、エツチング処理によって形成されたコンタク
トホール８の開口縁部が急峻な角度を呈するため、第２
図（Ｂ）に示すように、配線導体１０を設置した場合、
配線導体１０のコンタクトホール８の開口縁部を覆う部
分が薄くなり、段切れを生じるおそれがある。In this case, since the opening edge of the contact hole 8 formed by the etching process exhibits a steep angle, the second
When the wiring conductor 10 is installed as shown in Figure (B),
The portion of the wiring conductor 10 that covers the opening edge of the contact hole 8 becomes thinner, and there is a risk that breakage may occur.

そこで、エツチング中にレジスト膜６を後退させるなど
によってコンタクトホール８の形成角度を緩やかなもの
としたり、等方性エツチングを施した後に異方性エツチ
ングを施すなどの種々の方法が採られている。Therefore, various methods have been adopted, such as making the formation angle of the contact hole 8 gentler by retreating the resist film 6 during etching, or performing anisotropic etching after isotropic etching. .

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、従来の何れの方法もコンタクトホールの
形成について、再現性および制御性に難□があり、金属
蒸着部分の段切れを皆無にすることは困難であった。However, all of the conventional methods have difficulty in reproducibility and controllability with respect to the formation of contact holes, and it has been difficult to completely eliminate step breaks in the metal vapor deposited area.

第１の発明は、先鋭な角部を持つコンタクトホールの開
口縁部ををテーバ状に形成し、配線導体などの金属蒸着
部分の段切れを防止した半導体装置を提供しようとする
ものもある。A first aspect of the invention is to provide a semiconductor device in which the opening edge of a contact hole having a sharp corner is formed into a tapered shape to prevent breakage of a metal vapor deposited portion such as a wiring conductor.

また、第２の発明は、コンタクトホールの開口縁部をテ
ーパ状に形成し、配線導体の段切れを防止する半導体装
置の製造方法を提供しようとするものである。A second aspect of the invention is to provide a method for manufacturing a semiconductor device in which the opening edge of a contact hole is formed into a tapered shape to prevent the wiring conductor from breaking.

〔問題点を解決するための手段〕[Means for solving problems]

第１の発明の半導体装置は、半導体基板の表面を覆う酸
化膜に開口したコンタクトホールの開口縁部をテーパ状
に形成している。In the semiconductor device of the first invention, the opening edge of the contact hole opened in the oxide film covering the surface of the semiconductor substrate is formed in a tapered shape.

第２の発明の半導体装置の製造方法は、半導体基板の表
面を覆う酸化膜に選択的にエツチング処理してコンタク
トホールを開口する工程と、開口されたコンタクトホー
ルの開口縁部をエツチング処理してテーパ状に加工する
工程とを含むものである。A method for manufacturing a semiconductor device according to a second aspect of the invention includes a step of selectively etching an oxide film covering a surface of a semiconductor substrate to open a contact hole, and etching an opening edge of the opened contact hole. This process includes a step of processing into a tapered shape.

〔作　用〕[For production]

第１の発明は、酸化膜に形成したコンタクトホールの開
口縁部をテーパ状に形成することにより、その部分に設
置される配線導体などの蒸着金属の肉厚を一様にし、そ
の段切れを防止する。The first invention is to form the opening edge of a contact hole formed in an oxide film into a tapered shape, thereby making the thickness of vapor-deposited metal such as a wiring conductor installed in that part uniform, and eliminating the step break. To prevent.

また、第２の発明は、エツチング処理によってコンタク
トホールを形成するとともに、その開口縁部を選択的に
エツチング処理によって除き、テーパ状に形成する。Further, in the second aspect of the invention, a contact hole is formed by an etching process, and the edge of the opening is selectively removed by an etching process to form a tapered shape.

〔実施例〕〔Example〕

以下、各発明を図面に示した実施例を参照して詳細に説
明する。Hereinafter, each invention will be described in detail with reference to embodiments shown in the drawings.

第１図は、この発明の半導体装置およびその製造方法の
実施例を示している。FIG. 1 shows an embodiment of a semiconductor device and a manufacturing method thereof according to the present invention.

第１図において、（Ａ）はコンタクトホールの開口の形
成を示している。すなわち、シリコンなどからなる半導
体基板１２の表面に形成されたＳ　ｉ　Ｏ２膜などの酸
化膜１４にレジスト層１６を設置し、このレジスト層１
６をマスクにしてＲＩＥなどのエツチング処理により、
選択的にコンタクトホール１８が酸化膜１４に開口され
る。In FIG. 1, (A) shows the formation of a contact hole opening. That is, a resist layer 16 is provided on an oxide film 14 such as a SiO2 film formed on the surface of a semiconductor substrate 12 made of silicon or the like, and this resist layer 1
By etching process such as RIE using 6 as a mask,
Contact holes 18 are selectively opened in oxide film 14 .

このようなコンタクトホール１８の開口工程を経た後、
第１図（Ｂ）に示すように、酸化膜１４とレジスト層１
６との選択比を高めた条件で、再びＲＩＥなどのエツチ
ング処理を行う。After going through the process of opening such a contact hole 18,
As shown in FIG. 1(B), the oxide film 14 and the resist layer 1
Etching processing such as RIE is performed again under conditions where the selectivity with respect to No. 6 is increased.

エツチングガスとしては、たとえば、ＣＨＦ３＋０□系
ガスなどを用いることができる！この場合、０□の量を
大にすることによって選択比を高めることができる。As the etching gas, for example, CHF3+0□-based gas can be used! In this case, the selection ratio can be increased by increasing the amount of 0□.

この結果、第１図（Ｂ）に破線２０で示す部分がエツチ
ング処理で除かれ、第１図（Ｃ）に示すように、酸化膜
１４のコンタクトホール１８の開口縁部にはテーパ面２
２が形成される。As a result, the portion indicated by the broken line 20 in FIG. 1(B) is removed by the etching process, and as shown in FIG. 1(C), a tapered surface 2 is formed at the opening edge of the contact hole 18 in the oxide film 14.
2 is formed.

このように本来エツチング処理で先鋭な角度を呈するコ
ンタクトホール１８の開口縁部にテーパ面２２を形成す
れば、第１図（Ｄ）に示すように、その部分を覆って形
成する配線導体などの蒸着金属２４を、第２図（Ｂ）と
の比較から明らかなように、一様な肉厚に形成すること
ができる。If the tapered surface 22 is formed at the opening edge of the contact hole 18, which originally has a sharp angle through etching, as shown in FIG. As is clear from the comparison with FIG. 2(B), the vapor-deposited metal 24 can be formed to have a uniform thickness.

したがって、このようなコンタクトホール１８の開口部
の角部を除き、テーパ面２２を形成すれば、その部分に
形成される金属蒸着など配線導体の段切れを防止するこ
とができ、半導体装置の信頼性を高めることができる。Therefore, if the tapered surface 22 is formed except for the corner of the opening of the contact hole 18, it is possible to prevent the wiring conductor from being broken due to metal vapor deposition formed in that portion, thereby increasing the reliability of the semiconductor device. You can increase your sexuality.

また、このような製造方法によれば、コンタクトホール
１８の形成とともに、それに連続して開口縁部をテーパ
面２２に形成できるので、再現性および制御性の優れた
コンタクトホール１８の形成およびその加工精度を高め
ることができる。Further, according to such a manufacturing method, since the contact hole 18 can be formed and the opening edge can be formed continuously on the tapered surface 22, the contact hole 18 can be formed and processed with excellent reproducibility and controllability. Accuracy can be increased.

なお、前記実施例では、コンタクトホール１８の形成に
おいて、その開口部の酸化膜１４を全面的に剥離したが
、第３図（Ａ）に示すように、その一部分を開口部分に
残し、次のエツチングガスで、第３図（Ｂ）に示すよう
に、残留している酸化膜１４およびコンタクトホール１
８の開口縁部およびレジスト層１６の破線２６で示す部
分を除いてテーパ面２２を形成しても、同様の効果が期
待できる。この場合、コンタクトホール１８の内部に残
留させた酸化膜１４が、半導体基板２の保護膜として機
能するので、半導体基板２の劣化が防止できる。In the above embodiment, when forming the contact hole 18, the oxide film 14 at the opening was completely peeled off, but as shown in FIG. 3(A), a part of it was left in the opening and the next step With etching gas, the remaining oxide film 14 and contact hole 1 are removed as shown in FIG. 3(B).
A similar effect can be expected even if the tapered surface 22 is formed except for the opening edge 8 and the portion shown by the broken line 26 of the resist layer 16. In this case, the oxide film 14 left inside the contact hole 18 functions as a protective film for the semiconductor substrate 2, so that deterioration of the semiconductor substrate 2 can be prevented.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、第１の発明の半導体装置によれば
、コンタクトホールの開口縁部をテーパ状に形成したの
で、配線導体などの金属蒸着部の段切れを防止でき、信
頼性を向上させることができる。As explained above, according to the semiconductor device of the first invention, since the opening edge of the contact hole is formed in a tapered shape, it is possible to prevent breakage of metal vapor deposited parts such as wiring conductors, and improve reliability. be able to.

また、第２の発明の製造方法によれば、コンタクトホー
ルの開口縁部をテーパ状に形成できるとともに、高い再
現性および制御性を維持して容易かつ精密に形成できる
。Further, according to the manufacturing method of the second invention, the opening edge of the contact hole can be formed into a tapered shape, and can be formed easily and precisely while maintaining high reproducibility and controllability.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明の半導体装置およびその製造方法の実
施例を示す説明図、第２図は従来のコンタクトホールの
形成および電極形成を示す説明図、第３図はこの発明の
半導体装置の製造方法の他の実施例を示す説明図である
。 １２・・・半導体基板、１４・・・酸化膜、１６・・・
レジスト層、１８・・・コンタクトホール、２２・・・
テーパ面。 （Ａ） ６ ノ ＋２ （Ｂ） ９ ｚ − 第１図 （Ｃ） ２ （Ｄ） 第３図 （Ａ） ２ （Ｂ） 菖６ 第２図 （Ａ） （Ｂ） １９２−FIG. 1 is an explanatory diagram showing an embodiment of the semiconductor device and its manufacturing method of the present invention, FIG. 2 is an explanatory diagram showing the conventional formation of contact holes and electrode formation, and FIG. FIG. 6 is an explanatory diagram showing another example of the method. 12... Semiconductor substrate, 14... Oxide film, 16...
Resist layer, 18... Contact hole, 22...
Tapered surface. (A) 6 ノ+2 (B) 9 z - Figure 1 (C) 2 (D) Figure 3 (A) 2 (B) Iris 6 Figure 2 (A) (B) 192-

Claims (3)

【特許請求の範囲】[Claims] （１）半導体基板の表面を覆う酸化膜に開口したコンタ
クトホールの開口縁部をテーパ状に形成してなることを
特徴とする半導体装置。(1) A semiconductor device characterized in that the opening edge of a contact hole opened in an oxide film covering the surface of a semiconductor substrate is formed in a tapered shape. （２）半導体基板の表面を覆う酸化膜に選択的にエツチ
ング処理してコンタクトホールを開口する工程と、開口
されたコンタクトホールの開口縁部をエツチング処理し
てテーパ状に加工する工程とからなる半導体装置の製造
方法。(2) Consists of a step of selectively etching the oxide film covering the surface of the semiconductor substrate to open a contact hole, and a step of etching the opening edge of the opened contact hole to form a tapered shape. A method for manufacturing a semiconductor device. （３）前記コンタクトホールの内部に酸化膜を僅かに残
してエツチング処理した後、この残留している酸化膜の
除去と同時に、コンタクトホールの開口縁部の処理を行
うようにした特許請求の範囲第２項に記載の半導体装置
の製造方法。(3) After etching is performed to leave a slight oxide film inside the contact hole, the remaining oxide film is removed and at the same time, the opening edge of the contact hole is treated. 2. The method for manufacturing a semiconductor device according to item 2.
JP11794884A 1984-06-07 1984-06-07 Semiconductor device and manufacture thereof Pending JPS60261141A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11794884A JPS60261141A (en) 1984-06-07 1984-06-07 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11794884A JPS60261141A (en) 1984-06-07 1984-06-07 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS60261141A true JPS60261141A (en) 1985-12-24

Family

ID=14724192

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11794884A Pending JPS60261141A (en) 1984-06-07 1984-06-07 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS60261141A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0747947A2 (en) * 1995-06-05 1996-12-11 International Business Machines Corporation Dual Damascene process having tapered vias

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5540180A (en) * 1978-09-15 1980-03-21 Matsushita Electric Works Ltd Installing device of push button
JPS5687666A (en) * 1979-12-20 1981-07-16 Toshiba Corp Plasma etching method
JPS5789223A (en) * 1980-11-25 1982-06-03 Seiko Epson Corp Manufacture of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5540180A (en) * 1978-09-15 1980-03-21 Matsushita Electric Works Ltd Installing device of push button
JPS5687666A (en) * 1979-12-20 1981-07-16 Toshiba Corp Plasma etching method
JPS5789223A (en) * 1980-11-25 1982-06-03 Seiko Epson Corp Manufacture of semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0747947A2 (en) * 1995-06-05 1996-12-11 International Business Machines Corporation Dual Damascene process having tapered vias
EP0747947A3 (en) * 1995-06-05 1997-04-02 Ibm Dual Damascene process having tapered vias
US5874201A (en) * 1995-06-05 1999-02-23 International Business Machines Corporation Dual damascene process having tapered vias

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