JPS60260998A - Musical sound generation circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a musical sound generation circuit that generates musical sounds such as percussion instrument sounds.

[Conventional technology]

Conventionally, as a device for generating percussion instrument sounds, etc., an attenuated phase-shifted oscillator is used, and a trigger pulse is applied to the oscillator to cause it to oscillate.
An analog circuit could be used to output a waveform with a frequency and envelope determined by a time constant, and output a percussion instrument sound by changing the time constant and forming an attack section. ing.

[Problems with conventional technology]

However, in such devices, the percussion instrument sounds are generated by analog circuits, so the generated sounds tend to change due to product variations, temperature changes, etc., which requires an extra adjustment circuit. However, it is not possible to implement LSI (Large Scale Integrated Circuit), resulting in problems such as an increase in the number of parts and an increase in the mounting area.

[Purpose of the invention]

Therefore, the present invention provides musical tones that can be implemented in LSI, are suitable for miniaturization by reducing the number of parts, can be manufactured at lower cost, and are suitable for generating percussion instrument sounds that can produce a wide variety of tones with a single device. The purpose is to provide a generation circuit.

[Key points of the invention]

In order to achieve this object, the main feature of the present invention is to obtain an output with a predetermined duty ratio from a clock signal, convert this into noise data, and apply an envelope to the noise data.

[Summary of the invention]

The outline of this invention will be explained based on FIG.

The frequency generation circuit 1 outputs a serial lock signal (a) that is a combination of a long-cycle frequency clock and a short-cycle frequency clock, and provides it to the duty ratio control circuit 2. The duty ratio control circuit 2 generates a clock signal ( 1)
A clock signal (C), (d) or (i), (j) with a duty ratio of 50% or other is output from the clock signal. Here, the duty ratio is 1"(1") for one period of the clock signal.
It shows the percentage of the output time (high state of binary logic level), and if the duty ratio is 50%, it is the state of 1''.
0'' (binary logic level lOW state) state is the same ratio.

This duty-controlled clock signal (C) (d
) or (i) (j) is converted into noise data (f) by the exclusive OR gate 3 and is given to the gate circuit 4 as data having various frequency spectra with random output patterns. The gate circuit 4 receives envelope data E from the envelope generation circuit 5. ~E is given, an envelope is added to the maze data (f) to generate musical tone data Ao~Ae, and the musical tone is emitted from the speaker 7 via the D/A (digital/analog) converter 6. be done.

[Configuration of First Embodiment] The configuration of the first embodiment of the present invention will be described in detail below with reference to FIGS. 2 to 8.

<Configuration of Frequency Generating Circuit> FIG. 2 shows the circuit configuration of the frequency generating circuit 1, in which the half adder 8 is a. -a.

For data input to the terminal. It adds 1", which is always given to the terminals, and outputs it from the So to S3 terminals. The added data from the S.-S and terminals is sent to a 2-bit shift register 9 through AND gates A1 to A4, respectively. .10, 11, and 12. Each bit of this shift register 9 to 12 takes in the added data when the clock signal φ1 shown in the upper part of FIG. 3 is applied, and outputs the data that was taken in when the next clock signal φ2 is applied. to do,
Since the clock signal φ2 has the same period as φ1 but is shifted by half a period from φ, each shift register 9 to 12
takes in the added data by applying the signal φ1, shifts the added data by applying the next signal φ1, and then shifts the added data by applying the next signal φ1.
Outputs added data when applied.

The outputs of the shift registers 9 to 12 are again sent to a of the half adder 8. - input to the a3 terminal, 1'' from the bo terminal is added to the shift register 9 via the ant gates A1-A4.
12, the outputs of the shift registers 9 to 12 count up at twice the period of the clock signal φ1.

The count outputs from the shift registers 9 to 12 are applied directly to the decoder D1 via the inverters 1, .about.I. The decoder D1 receives the clock signal G, which repeatedly rises and falls at the timing of the '1'' signal of the clock signal φ2, as it is, and the inverter (2).
is given through. The decoder D1 has a plurality of Nant gates (indicated by circles in the figure), and when the clock signal G is "1", the outputs of the shift registers 9 to 12 are "1".
Select line A every time it reaches 1000 (8) and set it to 0.
"Output the signal, and every time the clock signal G is "0" and the output of the shift register 9.10 becomes "11 (3)", select line B, output the "0" signal, and give it to the decoder D2. . When the decoder D2 receives a "0" signal through either line A or B, it outputs a "1" signal through the Nant gate (indicated by a circle in the figure), and this "1" signal is sent to the NOR gate N1, the inverter is applied to the duty ratio control circuit 2 as a clock signal (a) through the shift registers 9 to 12.
000 (8)'' and a long frequency clock (the one without the diagonal line in Figure 2 (a)) and the shift register 9.10 change to 11 (3). A serial lock signal is obtained by combining a short frequency clock (hatched in FIG. 2(a)) with a short period of "1" every time. Note that a reset signal is applied to the NOR gate N1.

<Configuration of duty ratio control circuit> The above clock signal (a) passes through the exclusive NOR gate E1 and NOR gate N2 of the duty ratio control circuit 2, and then enters the latch 1.
3.14 to the exclusive NOR gate E1 again.

The launches 13 and 14 take in data when the clock signal φ1 is applied, and output the data that was taken in when the next clock signal φ2 is applied, and the latch 13 and 14 are delayed by 11 cycles of the clock signal φ1, and the clock signal φ1 is the clock signal. Since the period is half of G, the signal applied from the latch 14 to the exclusive NOR gate E1 is the clock signal (a) from the frequency generating circuit 1 delayed by the period of the clock signal G1. Then, the output signal (c) of the latch 13 and the output signal (d) of the latch 14 are applied to the NOR gate N3 of the gate circuit 4 via the exclusive OR gate 3 and the latch 15 as noise data (f).

Further, the signals (c) and (d) are passed through latches 16 and 17, which are provided temporarily for explanation, respectively, to the signals (C'a) and (d).
It can be seen that this signal (C;) (direct) has a duty ratio of 50%.

The latches 15, 16, and 17 take in data when the clock signal φS is applied, and output the taken data when the next clock signal φ2 is applied.

Note that a reset signal is applied to the NOR gate N2.

Gate circuit configuration> The above noise data (f) is inverted by NOR gate N3 and given to exclusive OR gates E2 to E7, and when noise data (f) is ``1'', the output of NOR gate N3 is ``O''.
Therefore, the envelope data Eo-E is directly outputted as the musical sound data A via the exclusive OR gates E2 to E7.
. ～A, and the noise data (f) is N0”
In this case, the output of NOR gate N3 becomes "1", and the envelope data Eo to Ea are inverted and become musical tone data A.

The envelope data Eo-E5 outputted as ~A5 and shown in FIG. 6 is musical tone data A shown in FIG.

~A, will be converted. Also, Noah Gate N3
The noise data (f) that has passed through is inverted via an inverter 6, and musical tone data is output as data 86 indicating positive polarity or negative polarity, as shown in FIG. The envelope data Eo-E is inputted to the NOR gate N3 via the NOR gate N4, and the output of this NOR gate N4 is inputted to the NOR gate N3, and the envelope data Eo-E is inputted to the NOR gate N3.

When ~E, are all 0'', the output of Noah gate N4 is 1''
Therefore, the output of NOR gate N3 is set to "0" regardless of the value of noise data (f), and envelope data E is generated. -E, is prevented from being reversed from "00...0" to "11...1".

[Operation of the first embodiment] Next, the operation of the first embodiment will be explained with reference to FIGS. 3, 8, etc.

Half adder 8 is now cleared and shift registers 9-1
Assuming that the contents of 2 are also cleared, decoder D
Since neither line A or B of 1 is selected, the output of decoder D2 is 0'' and the output of NOR gate N1 is ``1'', ant gates A1-A4 are open. and,
Half adder 8. Since the 1" signal is always given to the terminal, "1" is added to the output "0O00" of shift registers 9 to 12 and input to shift registers 9 to 12, and after two cycles of clock signal φ1, That is, after one cycle of the clock signal G, "0001" is input to the half adder 8, and "0010" is output, and binary counting is sequentially performed at the same tempo as the clock signal G. And the A line of decoder D1 has count data of “10”.
00(8)" and the B line is selected every time it becomes "11(8)".
3)", and the clock signal (a) in which the longer cycle and the shorter cycle are serialized via NOR gate N1 and inverter 6 is output in the pattern shown in Figure 3. . When this clock signal (a) is output, the output of the NOR gate N1 becomes "0", so the ant gates A1 to A4 are temporarily closed, and the data input to the shift registers 9 to 12 is also temporarily stopped, resulting in binary counting. It also stops temporarily.

The clock signal (a) from the frequency generation circuit 1 becomes the signal (b) via the exclusive NOR gate El and the NOR gate N2 of the duty ratio control circuit 2, and is delayed by the latch 13 and 14, and then becomes the exclusive NOR gate El again. and the output signals (C) and (d) of the latches 13 and 14 become the signal (e) via the exclusive OR gate 3), the latch 15
After that, noise data (f) is output.

This noise data (f) becomes a signal containing various frequency components.

The noise data (f) is then given to the exclusive OR gates E2 to E7 via the NOR gate N3 of the gate circuit 4,
Noise data (f) is 9゛1'' and envelope data E
. -E is output as is, and the envelope data Eo-E is inverted and output with the noise data (f) 0". Therefore, as shown in the upper part of FIG. 8, the envelope data F.-E.

is incremented during attack and decremented during decay, musical tone data A is partially inverted to negative polarity as shown in the lower part of FIG. 8 according to the value of noise data (f). ~
A6 is output. Therefore, a musical tone as shown in FIG. 7 is generated in which a varying envelope as shown in FIG. 6 is added to the noise data (f), and the D/A converter 6
The sound is emitted from the speaker 7 via.

Furthermore, if the periods of the clock signals φ8, φ2, φ8, and G are changed to be shorter or longer, the noise data (f
) N1” signal width becomes shorter or longer,
By changing the frequency components, it is possible to output musical tones with various tones.

[Second example] FIGS. 9 and 10 show a second embodiment.

In this embodiment, as shown in FIG. 9, only the duty ratio control circuit 2 outputs the clock signal (a) through the N-ary counter 20 via the latch 18 and 19, and outputs the clock signal (a) through the N-ary counter 20 via the latch 21. The signal is outputted via the counter 22, and this output (iHj) is input to the exclusive OR gate 3.

The latch 18, like the above-mentioned launches 13.14, takes in data when the clock signal φ1 is applied, and outputs the data taken in when the clock signal φ2 is applied, and the latches 19.21, like the latches 15 to 17, take in the data when the clock signal φ1 is applied, and output the data when the clock signal φ2 is applied. It takes in data and outputs the data that has been taken in for Q times when the clock signal φ2 is applied.

As a result, in this embodiment, the clock signal (a) from the frequency generating circuit 1 is not decomposed into two signals (ri) and (h) according to timing as shown in FIG.
, N-ary counter 22 is set to N=31M=5, each counter 20.22 has a duty ratio of 33.
% clock signal (i) and 20% clock signal N) are output, so that it is possible to obtain noise data (f) having a variation different from that of 50% described above.

Note that the noise data (f) can be produced by changing the output pattern of the decoder D1 and the duty ratio of the duty ratio control circuit 2 over time according to the values of the envelope data E0 to E, to produce musical sounds with more dynamic frequency components. Obtainable.

In addition, the clock signal (a
) may be one in which two types of frequency clocks are serialized, or three or more types of frequency clocks are serialized by increasing the number of lines of decoders D1 and D2.

Further, the duty ratio control circuit 2 may be any circuit other than the one using the gate, launch, or counter of the above embodiments as long as it can control the duty ratio.

〔Effect of the invention〕

As described above, the present invention obtains an output with a predetermined duty ratio from a clock signal, converts it into noise data, and applies an envelope to it to obtain a musical tone suitable for, for example, a percussion instrument. can be realized with digital circuits, and by using LSI, the number of parts and mounting area can be reduced, making it possible to miniaturize the device and lower the cost of the device. In addition to being able to generate clear musical tones that are not affected by external factors such as noise and temperature, it is also possible to generate various musical tones with a single device by simply changing the cycles of clock signals φ1 to φ3. This has effects such as being able to generate .

[Brief explanation of the drawing]

The drawings show each embodiment of the present invention. FIG. 1 is a schematic diagram of the overall configuration, FIG. 2 is a circuit diagram of the frequency generation circuit 1 and duty ratio control circuit 2, and FIG. 3 is a diagram of each part of FIG. 2. FIG. 4 is a circuit diagram of the gate circuit 4, and FIG. 5 is the musical tone data A. - Diagram showing the contents of A6, No. 6
The figure shows envelope data E. - A diagram showing an example of the output of E5,
Figure 7 is musical tone data A. Figure 8 showing an example of the output of -A.
The figure shows a time chart of the signals of each part in FIG. 4, and FIG. 9 is a circuit diagram of the duty ratio control circuit 20 of the second embodiment.
FIG. 10 is a diagram showing a time chart of signals of each part in FIG. 9. DESCRIPTION OF SYMBOLS 1... Frequency generation circuit, 2... Duty ratio control circuit, 3... Exclusive OR gate, 4
...Gate circuit, Dl, D2...Decoder, 9 to 12...Shift register, 13.1
4.19.20.22... Latch, 21...
...N-ary counter, 23...M-ary counter. Patent applicant Casio Computer Co., Ltd. Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] a frequency generation circuit that outputs a plurality of frequency clocks as serial signals; a duty ratio control circuit that controls the duty ratio of the signal output from the frequency generation circuit;
A musical tone generation circuit comprising means for converting an output clock whose duty ratio is controlled from the duty ratio control circuit into noise data, and means for adding an envelope to the noise data output from the conversion means. .