JPS60260151A - Mos gate bipolar transistor - Google Patents
Mos gate bipolar transistorInfo
- Publication number
- JPS60260151A JPS60260151A JP11692784A JP11692784A JPS60260151A JP S60260151 A JPS60260151 A JP S60260151A JP 11692784 A JP11692784 A JP 11692784A JP 11692784 A JP11692784 A JP 11692784A JP S60260151 A JPS60260151 A JP S60260151A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- concentration
- bipolar transistor
- gate bipolar
- junction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 8
- 238000010894 electron beam technology Methods 0.000 abstract description 7
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 229910001385 heavy metal Inorganic materials 0.000 abstract description 4
- 238000010276 construction Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
Abstract
Description
【発明の詳細な説明】
(技術分野)
本発明はソースおよびドレインが半導体基体の縦方向に
配置されたパワーMO8)ランジスタに関する。TECHNICAL FIELD The present invention relates to a power transistor (MO8) whose source and drain are arranged in the vertical direction of a semiconductor body.
(従来技#)
よく知られているパワーMO8ITはスイッチングスピ
ードが速く、二次降伏が起らず並列接続が容易であシ、
ゲートの制御回路が簡単になるなど秀れた特長を持って
いる。しかし、ユニポーラデバイスであるため、特に高
耐圧素子においては、電界を緩オロするだめの低濃度層
の電圧降下が大きく、オン時の損失の増大と扱える電流
容量とが小さいという欠点も持っている。(Conventional technology #) The well-known power MO8IT has a high switching speed, does not cause secondary breakdown, and can be easily connected in parallel.
It has excellent features such as a simplified gate control circuit. However, because it is a unipolar device, especially in high-voltage devices, there is a large voltage drop in the low-concentration layer that is needed to soften the electric field, which also has the drawbacks of increased loss when it is on and a small current capacity that it can handle. .
これらの長所、短所を融和させる方法としてバイポーラ
動作を行わせるべく構造を少し変更したMOSゲートバ
イポーラトランジスタが捉案されている。MOSゲート
バイポーラトランジスタはNチャネルMOSゲートの場
合第1図に示す構造を持つ。すなわち、従来のパワーM
O8FETでは第1図の層1,3け夫々N+サブストレ
ート、N−)−1一層であったところ、これをPサフス
トレート、p++層にして、層2のN−電界緩和層との
間にpn接合が形成される様にしている。この構造は、
いわゆるエピタキシャル成長を行ってN−電界緩和暦2
を得る場合のN サブストレートをP サブストレート
1に変更し、また拡散プロセスを多少変更するだけで容
易に得られるものである。又この様に形成された場合の
最も平均的な不純物濃度プロファイルを第1図(b)に
示した。同、第1図a、bはソース、7はゲート、8F
!ドレインである。As a method to balance these advantages and disadvantages, a MOS gate bipolar transistor whose structure is slightly modified to perform bipolar operation has been proposed. The MOS gate bipolar transistor has the structure shown in FIG. 1 in the case of an N channel MOS gate. That is, the conventional power M
In the O8FET, layers 1 and 3 in Figure 1 were each an N+ substrate and an N-)-1 layer, but these were changed to a P sufflate layer and a p++ layer, and between them and the N- electric field relaxation layer of layer 2. A pn junction is formed. This structure is
N- electric field relaxation calendar 2 by performing so-called epitaxial growth
can be easily obtained by simply changing the N substrate to the P substrate 1 and slightly changing the diffusion process. Furthermore, the most average impurity concentration profile when formed in this manner is shown in FIG. 1(b). 1, a and b are sources, 7 is a gate, 8F
! It is a drain.
さて、第1図の構造を持つMOSゲートバイポーラトラ
ンジスタでは、この層1と2とで構成されるP+N+接
合より主にホールが拡散によ9戸層1からN一層2に注
入され、この注入量が大きいとN一層2が導電率変調を
起し大電流が流れ、又N一層2の抵抗が実効的に下るた
めオン時損失も小さくなる。しかし、当然のことながら
このN一層2の小数キャリアであるホールは寿命が長い
ため、このトランジスタのターンオフ時間は長くなり、
パワーMO8FETの最大の特徴であったスイッチング
スピードの高速性は失われる。このため、重金属のドー
プあるいは中性子線、電子線の照射などにより、N一層
2おホールライフタイムを下げることによシ、ターンオ
フ時間を短くしている。Now, in the MOS gate bipolar transistor having the structure shown in Fig. 1, holes are mainly injected from the layer 1 to the layer 2 by diffusion from the P+N+ junction composed of layers 1 and 2, and the amount of injection is When is large, conductivity modulation occurs in the N layer 2, causing a large current to flow, and since the resistance of the N layer 2 is effectively reduced, the on-state loss is also reduced. However, as a matter of course, holes, which are minority carriers in this N layer, have a long life, so the turn-off time of this transistor becomes long.
The high switching speed, which was the greatest feature of the power MO8FET, is lost. For this reason, the turn-off time is shortened by lowering the N-layer 2 hole lifetime by doping with heavy metals or irradiating with neutron beams or electron beams.
この結果、スイッチングスピードはパワーMO81Tよ
り遅いが通常のバイポーラトランジスタよシ速く、ゲー
ト制御はパワーMO8FETと同じく簡単であシ、小数
キャリアのベース注入によるコレクタ電流の制御でない
ため二次降伏が起9にくいといった特徴を持ち、まだ、
扱える電流は二次降伏が起らない分だけ大きくとれる。As a result, the switching speed is slower than the power MO81T, but faster than a normal bipolar transistor, the gate control is as simple as the power MO8FET, and secondary breakdown is less likely to occur because the collector current is not controlled by base injection of minority carriers. With such characteristics, still
The current that can be handled can be increased to the extent that secondary breakdown does not occur.
しかし、重金属ドープは通常のパワーMOSFETプロ
セスになじまず、中性子線、電子線照射ではMOSのゲ
ート酸化膜にダメージを与え好ましくない。However, heavy metal doping is not compatible with normal power MOSFET processes, and neutron beam or electron beam irradiation damages the gate oxide film of the MOS, which is not preferable.
(発明の目的および構成)
本発明は従来の重金属ドープ、中性子線、電子線照射に
よることなく、ターンオフタイムが短かく高速動作可能
なMOSゲートバイポーラトランジスタを提供すること
を目的とし、その特徴とするところけPN接合を構成す
る46.4の不純物濃度を低めたことにある。(Objects and Structure of the Invention) An object of the present invention is to provide a MOS gate bipolar transistor that has a short turn-off time and can operate at high speed without using conventional heavy metal doping, neutron beam, or electron beam irradiation, and has its characteristics. The reason is that the concentration of 46.4 impurities constituting the PN junction has been lowered.
(実施例)
図面に従って本発明を説明しよう。本発明は従来PN接
合の濃度がそれぞれ1019 の濃度の層と1014の
濃度層とで構成されていたものを101@と1014程
度のpn接合とするものである。具体的には、従来P
基板1上にそのままN一層2(第1図)をエピタキシャ
ル成長させたものを、第2図に示すように、上記の10
16程度のP−型エビタキクヤル層1′を成長させ、そ
の後N”−Wエピタキシャル層2を成長することKよる
。本発明の構造によると、従来P 層1から101@オ
ーダーで注入されていたホールが、層1′の存在によシ
101・オーダーに下がる。この様忙すると、例えば層
1′−2のpn接合を流れる電流をホールのみとして(
1)式のごとく表わせるため、I3が1011から10
16に下ることによシIsが10−3程度低下する。(Example) The present invention will be explained according to the drawings. In the present invention, the conventional PN junction is made up of a layer with a concentration of 1019 and a layer with a concentration of 1014, but is changed to a pn junction with a concentration of about 101@ and 1014, respectively. Specifically, conventional P
As shown in FIG. 2, the N layer 2 (FIG. 1) is epitaxially grown on the substrate 1 as it is, and the above 10 layers are grown as shown in FIG.
According to the structure of the present invention, a P-type epitaxial layer 1' of about 16 layers is grown, and then an N''-W epitaxial layer 2 is grown. is reduced to the order of 101 due to the presence of layer 1'.If this is the case, for example, if the current flowing through the pn junction of layers 1'-2 is assumed to be only holes (
1) In order to express it as shown in the formula, I3 changes from 1011 to 10
By dropping to 16, the Is decreases by about 10-3.
qv/に丁
■−Is(e −1) ・・・・(1)一方、同一のI
を得るために必要なPn接合層には(1)式よル指数関
数であるため高々0.2■にすぎない。図からもわかる
様に、この時のN一層1′内の小数キャリア量は本発明
の場合従来に比し10−3程となり、ターンオフタイム
がこのオーダーで減小する。又、従来に比しpn接合に
必要な電圧が0.2■程度増加するがこれはに11拡散
、中性子線照射、電子線照射を行ってもライフタイムの
低下によシこの程度増加する。以上のごとく、本発明に
よればAu拡散、中性子照射、電子線照J][トMO8
プロセスに有害ともいえるプロセスを含むことなく同等
性能のMO8ゲートハイホーラトランジスタを得ること
ができる。父上記説明中のP、 nの極性を逆にした逆
極性タイプのものを全く同様の効果を持つことは云うま
でもない。qv/niding ■-Is (e -1) ...(1) On the other hand, the same I
Since the Pn junction layer required to obtain the equation (1) is an exponential function, it is only 0.2■ at most. As can be seen from the figure, in the case of the present invention, the amount of minority carriers in the N layer 1' is about 10<-3> compared to the conventional case, and the turn-off time is reduced by this order. Further, the voltage required for the pn junction increases by about 0.2 .mu. compared to the conventional method, but this increase will continue due to the decrease in lifetime even if diffusion, neutron beam irradiation, and electron beam irradiation are performed. As described above, according to the present invention, Au diffusion, neutron irradiation, electron beam irradiation
An MO8 gate high hole transistor with equivalent performance can be obtained without including a process that can be said to be harmful to the process. It goes without saying that a reverse polarity type, in which the polarities of P and n in the above explanation are reversed, has exactly the same effect.
第1図(a)は従来のMOSゲートバイポーラトランジ
スタ概略断面図、第1図(b)は(a)の線9にそった
不純物分布図、第2図(a)は本発明の実施例によるM
OSゲートバイポーラトランジスタの概略断面図、第2
図(b)は(a)の線9にそった不純物分布図である。
1・・・・・・P サブストレート、1′、、、、、
P−エピタキシャル層、2・・・・・・N−エピタキシ
ャル層、3・・・・・・P+i、4・・・・・・P層、
5・・・・・・1層、6・・・・・・ソース電極(エミ
ッタ電極)、7・・・・・・ゲート電極、8・・・・・
・ドレイン電極(コレクタ電極)。
第2区((2) 第2区(b)FIG. 1(a) is a schematic cross-sectional view of a conventional MOS gate bipolar transistor, FIG. 1(b) is an impurity distribution diagram along line 9 in FIG. 2(a), and FIG. 2(a) is a diagram according to an embodiment of the present invention. M
Schematic cross-sectional diagram of an OS gate bipolar transistor, 2nd
Figure (b) is an impurity distribution diagram along line 9 in (a). 1...P Substrate, 1',...
P-epitaxial layer, 2...N-epitaxial layer, 3...P+i, 4...P layer,
5...1 layer, 6...source electrode (emitter electrode), 7...gate electrode, 8...
・Drain electrode (collector electrode). 2nd ward ((2) 2nd ward (b)
Claims (1)
て低濃度の第1半導体層を有し、この第1半導体層上に
低濃度の反対導電型の第2半導体層を有し、この第2半
導体層の表面にゲート電極とソースおよびドレインの一
方の電極とを有し、前記基板にソースおよびドレインの
他方の電極を有することを特徴とするMOSゲートバイ
ポーラトランジスタ。Comparatively, the conductivity of the cylinder impurity is the same conductivity on the mold substrate! a first semiconductor layer of a low concentration type and a low concentration, a second semiconductor layer of a low concentration and opposite conductivity type on the first semiconductor layer, and a gate electrode, a source and a source on the surface of the second semiconductor layer. 1. A MOS gate bipolar transistor having one electrode of a drain, and having the other electrode of a source and a drain on the substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11692784A JPS60260151A (en) | 1984-06-07 | 1984-06-07 | Mos gate bipolar transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11692784A JPS60260151A (en) | 1984-06-07 | 1984-06-07 | Mos gate bipolar transistor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60260151A true JPS60260151A (en) | 1985-12-23 |
JPH0466109B2 JPH0466109B2 (en) | 1992-10-22 |
Family
ID=14699128
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11692784A Granted JPS60260151A (en) | 1984-06-07 | 1984-06-07 | Mos gate bipolar transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60260151A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0657941A2 (en) * | 1993-12-08 | 1995-06-14 | Siemens Aktiengesellschaft | Gated power semiconductor device with buffer layer and method of fabrication |
-
1984
- 1984-06-07 JP JP11692784A patent/JPS60260151A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0657941A2 (en) * | 1993-12-08 | 1995-06-14 | Siemens Aktiengesellschaft | Gated power semiconductor device with buffer layer and method of fabrication |
EP0657941A3 (en) * | 1993-12-08 | 1995-10-25 | Siemens Ag | Gated power semiconductor device with buffer layer and method of fabrication. |
Also Published As
Publication number | Publication date |
---|---|
JPH0466109B2 (en) | 1992-10-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |