JPS60260150A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60260150A JPS60260150A JP11553684A JP11553684A JPS60260150A JP S60260150 A JPS60260150 A JP S60260150A JP 11553684 A JP11553684 A JP 11553684A JP 11553684 A JP11553684 A JP 11553684A JP S60260150 A JPS60260150 A JP S60260150A
- Authority
- JP
- Japan
- Prior art keywords
- field plate
- junction
- film
- concentration
- boron
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000012535 impurity Substances 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 abstract description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052796 boron Inorganic materials 0.000 abstract description 5
- 230000005684 electric field Effects 0.000 abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- 238000006243 chemical reaction Methods 0.000 abstract description 2
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 2
- 239000011574 phosphorus Substances 0.000 abstract description 2
- 239000005368 silicate glass Substances 0.000 abstract description 2
- 239000012808 vapor phase Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、半導体装置、とくに高耐圧のプレーナ形半
導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a high-voltage planar semiconductor device.
従来、プレーナ形半導体装置におけるＰＮ接合の逆耐電
圧を高くする方法の１つとして、フィールドプレートを
用いる方法が知られている。この方法は、例えばＮ形半
導体基板にボロンの選択拡散を行って形成したＰＮ接合
を例にとると、第１図に示した通りＰＮ接合の周縁を覆
うように、絶縁膜を介して金属電極（フィールドプレー
ト）を設け、このフィールドプレートをアノード電極へ
接続し、アノード電位が負になってＰＮ接合が逆バイア
ス条件になった場合に、フィールドプレートの下の半導
体基板表面が空乏領域となるようにしてＰＮ接合周縁の
電界集中を緩和させ、逆耐電圧を高くするものである。Conventionally, a method using a field plate has been known as one method for increasing the reverse withstand voltage of a PN junction in a planar semiconductor device. In this method, for example, taking a PN junction formed by selectively diffusing boron in an N-type semiconductor substrate, a metal electrode is placed through an insulating film so as to cover the periphery of the PN junction, as shown in Figure 1. (field plate) is provided, and this field plate is connected to the anode electrode, so that when the anode potential becomes negative and the PN junction becomes a reverse bias condition, the semiconductor substrate surface under the field plate becomes a depletion region. This reduces the electric field concentration around the PN junction and increases the reverse withstand voltage.
この場合、フィールドプレートは同電位でアノード電圧
がそのま＼印加されるために、耐圧が４００Ｖ以上の高
耐圧装置になると、フィールドプレートの端に電界が集
中してしまう。これを緩和するには、基板とフィールド
プレートとの間の絶縁膜厚を大きくすることが必要とな
るが、厚膜構造にすると、絶縁膜にクラツクが発生しゃ
すくなシ、電気的特性の劣化、信頼性の低下が起る。ま
た、厚膜構造にした場合は基板および基板上に形成した
各種拡散領域を含む配線を行う工程において、絶縁膜に
現われる大きな段差のために断線が起こシ易くなシ、歩
留も低下してしまう。In this case, the field plates are at the same potential and the anode voltage is applied as is, so if the device becomes a high voltage device with a breakdown voltage of 400V or more, the electric field will be concentrated at the edge of the field plate. In order to alleviate this problem, it is necessary to increase the thickness of the insulating film between the substrate and the field plate, but a thick film structure will prevent cracks from occurring in the insulating film and reduce the deterioration of electrical characteristics. Deterioration of reliability occurs. In addition, when a thick film structure is used, during the process of wiring including the substrate and various diffusion regions formed on the substrate, disconnection is less likely to occur due to the large step difference that appears in the insulating film, and the yield is reduced. Put it away.
この発明の目的は、上記したフィールドプレートを用い
たプレーナ構造の半導体装置を改善したもので、フロー
ティング・フィールドプレートを設け、従来技術による
絶縁膜を用い、高耐圧のプレーナ形半導体装置を提供す
るにある。An object of the present invention is to improve the above-described planar structure semiconductor device using a field plate, and to provide a planar semiconductor device with a high breakdown voltage by providing a floating field plate and using an insulating film according to the prior art. be.
フローティング・フィールドプレートとアノードおよび
半導体基板との容量をそれぞれＣ１およびＣ２とすると
、アノード電圧（カソードを接地）’Ｊｈは、それぞれ
の容量の逆数の比で分圧され、フローティング−フィー
ルドプレートの電圧ＶＦＦＰは、
Ｖ ＦＦＰ −−−−−９−１−−−−Ｖ Ａ０１＋０
２
となる。ＶＦＦＰは、Ｃ１およびＣ２で制御することが
出来、Ｖ＾よシ低くすることができるので、薄い絶縁膜
を用いて高耐圧のプレーナ形半導体装置を製造すること
ができる。If the capacitances of the floating field plate, anode, and semiconductor substrate are C1 and C2, respectively, the anode voltage (cathode is grounded)'Jh is divided by the ratio of the reciprocal of each capacitance, and the floating-field plate voltage VFFP is V FFP −−−−−9−1−−−−V A01+0
It becomes 2. Since VFFP can be controlled by C1 and C2 and can be made lower than V, a planar semiconductor device with high breakdown voltage can be manufactured using a thin insulating film.
以下、この発明による高耐圧半導体装置の実施例として
シリコンのＰＮ接合の場合について説明する。第２図は
その一実施例の構成を示す断面図である。Ｎ形半導体基
板２１はドナー不純物濃度がｌＸｌ０ （＋ｌＫ 、比
抵抗が５０Ω儂で、カソード側に高濃度のリンを拡散し
てｎ＋層２２を形成しである。つぎにアノード側主面に
Ｓ ｉ Ｏ，膜２４を形成し、この膜をマスクとして選
択的にボロンの拡散を行い、ｐ影領域２３を形成した。Hereinafter, a case of a silicon PN junction will be described as an embodiment of a high breakdown voltage semiconductor device according to the present invention. FIG. 2 is a sectional view showing the configuration of one embodiment. The N-type semiconductor substrate 21 has a donor impurity concentration of lXl0 (+lK) and a specific resistance of 50Ω, and is made by diffusing high concentration phosphorus on the cathode side to form an n+ layer 22. Next, Si is deposited on the main surface on the anode side. An O2 film 24 was formed, and boron was selectively diffused using this film as a mask to form a P shadow region 23.
このｐｎ接合の周縁近くで、曲率をもつ部分に起る電界
集中を緩和するためには接合の深さＸｊを大きくして曲
率半径を大きくすることが必要で、実験ではｘｊ＝ａＱ
μｍ、！＝した。フローティング・フィールドプレート
２５は、ボロンをドープした低抵抗のポリシリコン膜で
形成し、その上に気相化学反応によるシリケートガラス
２６を堆積したのち、アルミ電極２７および２８を形成
した。並行して試作した第１図に示した従来の構造の素
子の逆耐電圧が４５０ｖであったの忙対し、本発明によ
る第２図に示した構造の素子は同じ絶縁膜厚で、逆耐電
圧６００Ｖを得た。In order to alleviate the electric field concentration that occurs near the periphery of this pn junction, it is necessary to increase the junction depth Xj and the radius of curvature.In the experiment, xj = aQ
μm! =I did. The floating field plate 25 was formed of a low resistance polysilicon film doped with boron, on which silicate glass 26 was deposited by vapor phase chemical reaction, and then aluminum electrodes 27 and 28 were formed. The reverse withstand voltage of the device with the conventional structure shown in FIG. 1, which was prototyped in parallel, was 450 V, but the device of the present invention with the structure shown in FIG. A voltage of 600V was obtained.
以上の実施例においては、半導体のｐｎ接合の場合につ
いて説明したが、本発明は金属と半導体との接触によっ
て形成されるシ曽ットキ接合、異種の半導体同志の接合
であるペテロ接合に対しても同様な効果をもっている。In the above embodiments, the case of a pn junction of a semiconductor has been described, but the present invention also applies to a Schottky junction formed by contact between a metal and a semiconductor, and a Peter junction, which is a junction between different types of semiconductors. It has a similar effect.
また半導体装置についてもダイオードに限らず、トラン
ジスタ、サイリスタ等にも適用することができる。Furthermore, the present invention is applicable not only to diodes but also to transistors, thyristors, and the like for semiconductor devices.
また逆耐電圧が１００ＯＶ以上の半導体装置に対しては
、第３図に示したように互に絶縁された多重のフローテ
ィング・フィールドプレートを設は隣接する７０−テイ
ンク・フィールドプレートと容量で結合させて電圧と順
次低下させていく方法が適している。In addition, for semiconductor devices with a reverse withstand voltage of 100 OV or more, multiple floating field plates that are insulated from each other can be connected capacitively to an adjacent 70-ten field plate as shown in Figure 3. A suitable method is to gradually lower the voltage.
第１図はフィールドプレートを用いた従来の構造による
半導体ｐｎ接合の断面図、第２図は本発明の一実施例で
あるフローティング・フィールドプレートを用いた半導
体ｐｎ接合の断面図、第３図は本発明の他の実施例を示
す高耐圧ｐｎ接合の断面図である。
１１．２１．３１・・・ｎ形シリコン半導体基板、２２
＝・ｎ＋形拡散層、１３ 、２３ 、３３ ・−ｐ形
波散層、１４，２４，２６，３４．３６・・絶縁膜、２
５．３５３５′・・・ポリシリコンの７０−ティング・
フィールドプレート、１７，２７．３’７・・・アノー
ド、１８・・・フィールドプレート、２８ 、３８ 、
３８ ’・・フィールド電極、１９，２９．３９・ カ
ソード。
代理人 弁理士 則 近 憲 佑 （ほか１名）第１図
第２図FIG. 1 is a sectional view of a semiconductor pn junction with a conventional structure using a field plate, FIG. 2 is a sectional view of a semiconductor pn junction with a floating field plate according to an embodiment of the present invention, and FIG. 3 is a sectional view of a semiconductor pn junction with a conventional structure using a field plate. FIG. 7 is a cross-sectional view of a high voltage pn junction showing another embodiment of the present invention. 11.21.31...n-type silicon semiconductor substrate, 22
=・n+ type diffusion layer, 13, 23, 33・-p type wave diffusion layer, 14, 24, 26, 34.36・・insulating film, 2
5.3535'...Polysilicon 70-ting
Field plate, 17, 27.3'7... Anode, 18... Field plate, 28, 38,
38'...Field electrode, 19,29.39. Cathode. Agent Patent Attorney Kensuke Chika (and 1 other person) Figure 1 Figure 2
Claims (2)
選択的に拡散して第２の導電形を有する領域を形成して
得られ九ＰＮ接合面の周縁に沿って、ＰＮ接合面の端部
を取り囲むように設けられ、周囲を絶縁膜で囲まれたフ
ローティング・フィールドグレートと、このフローティ
ング・フィールドプレートの上に絶縁膜を介して設けら
れたフィールド電極とを有することを特徴とする半導体
装置。(1) A PN junction surface obtained by selectively diffusing impurities to form a region having a second conductivity type on a semiconductor substrate having a first conductivity type. A floating field plate is provided to surround an end of the field plate and is surrounded by an insulating film, and a field electrode is provided on the floating field plate via an insulating film. Semiconductor equipment.
件となる場合に半導体基板表面の空乏層が拡がる極性の
電位が印加されるようにしたことを特徴とする特許請求
の範囲第１項記載の半導体装置。(2) A potential having a polarity that expands a depletion layer on the surface of the semiconductor substrate when the PN junction is under a reverse bias condition is applied to the field electrode. Semiconductor equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11553684A JPS60260150A (en) | 1984-06-07 | 1984-06-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11553684A JPS60260150A (en) | 1984-06-07 | 1984-06-07 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60260150A true JPS60260150A (en) | 1985-12-23 |
Family
ID=14664959
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11553684A Pending JPS60260150A (en) | 1984-06-07 | 1984-06-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60260150A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4789886A (en) * | 1987-01-20 | 1988-12-06 | General Instrument Corporation | Method and apparatus for insulating high voltage semiconductor structures |
-
1984
- 1984-06-07 JP JP11553684A patent/JPS60260150A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4789886A (en) * | 1987-01-20 | 1988-12-06 | General Instrument Corporation | Method and apparatus for insulating high voltage semiconductor structures |
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