JPS60260144A - Semiconductor device - Google Patents

Abstract

PURPOSE:To check generation of latching up of a semiconductor device to be caused according to a parasitic thyristor by a method wherein a first conductive semiconductor substrate is constructed of an epitaxial growth layer of low resistance, and formed as to make the peak of impurity concentration thereof to be positioned at the deep position. CONSTITUTION:By implanting p type impurity ions, B ions for example, at an extremely high accelerating energy of 550keV, a p-well 4 is made to have a retrograde well construction, the betan of a parasitic n-p-n transistor can be made extremely small, moreover because a CMOS transistor is formed to an epitaxial growth layer 21 formed on an n type silicon substrate 1 of extremely low resistance of 0.01OMEGAcm, resistance RS is reduced sharply, consequently the voltage is reduced as IRSXRS<0.6(V) (IRS: a current to flow in RS), and a positive feedback is not applied to a parasitic p-n-p transistor. Because the distance (x) between the p-well 4 and the n type silicon substrate 1 is selected to about 1.0mum, Cj is extremely small, and especially generation of latching up at electric power source closing time can be checked.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a first semiconductor region of a second conductivity type formed in a semiconductor substrate of a first conductivity type; The present invention relates to a semiconductor device including a semiconductor region of a first conductivity type formed in a semiconductor region and a second semiconductor region of a second conductivity type formed in the semiconductor substrate of the first conductivity type.

BACKGROUND TECHNOLOGY AND PROBLEMS MO3 has various advantages such as low power consumption, high noise margin, wide operating power supply voltage range, and high load driving ability, so it will be the most suitable element for future VLSI. It is seen as promising. In this 0MO8, for example, as shown in FIG. 1, a source region 2 and a drain region 3 made of a p' layer are formed in an n-type silicon substrate 1. Further, a p-well 4 is formed in a portion of the n-type silicon substrate 1 adjacent to the drain region 3;
A source region 7 and a drain region 8 made of n' layers are formed therein. On the other hand, Si
A gate insulating film IO made of an O□ film is formed, and a gate electrode 11 made of a polycrystalline silicon film is formed on this gate insulating film 10. Similarly, a gate insulating film 14 made of a 5i02 film is formed on the p-well 4, and a gate electrode 15 made of a polycrystalline silicon film is formed on this gate insulating film 14. Then, a p-channel MO3FET 17 is formed from the gate electrode 11, gate insulating film 10, source region 2, and drain region 3, and an n-channel MO3FET is formed from the gate electrode 15, gate insulating film 14, source region 7, and drain region 8.
18 are configured, these p-channel MO'S FETs
17 and n-channel MO3FET 18 constitute 0MO3.

In the &Mos shown in FIG.
Since the p-well 4 and, for example, the n layer constituting the source region 7 have a pnpn structure, that is, a parasitic silicon structure, the following problems arise. That is, the above-mentioned parasitic silicon risk is turned on by a trigger current generated due to external noise, for example, and as a result, a through current flows from the power supply side to the ground side, destroying the transistor or blowing out the AN wiring. There are things to do. The relationship between the voltage VAK between the terminals A and the current IAI+ flowing between these terminals A in the above-mentioned parasitic silicon risk is shown in FIG. 2, and in this FIG. It is about 51.

The above-mentioned si-risk phenomenon, that is, the so-called latch amplifier is caused by a parasitic pnp transistor consisting of, for example, a p+ layer constituting the drain region 3, an n-type silicon substrate 1, and a p-well 4, and a parasitic pnp transistor comprising the n-type silicon substrate 1, p-well 4, and, for example, the source. It is known that this occurs when the parasitic npn (npn) transistor consisting of the 04 layer constituting region 7 is turned on at the same time. For this reason, the conventional 2μm rule of 0MO3
In this case, the junction depth of the p-well 4 is increased to about 3 to 6 μm, and the impurity concentration of the p-well 4 is increased to reduce βゎ of the above-mentioned parasitic npn) transistor, and the p-well 4 and drain region 3 are The latch amplifier can be It was being prevented. However, in 0MO3 of about 1.5 μm rule or less, it is difficult to prevent the occurrence of latch-a-knob by the method described above.

OBJECTS OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a semiconductor device that corrects the above-mentioned drawbacks of the conventional CMO8.

Summary of the Invention A semiconductor device according to the present invention includes a first semiconductor region of a second conductivity type (for example, a p-well) formed in a semiconductor substrate of a first conductivity type, and a first semiconductor region of the second conductivity type formed in a semiconductor substrate of the first conductivity type. A semiconductor region of a first conductivity type (for example, a source region and a drain region made of n layers) formed in the semiconductor region;
In a semiconductor device (for example, 0MO3 constituting an LSI) each comprising a second semiconductor region of a second conductivity type (for example, a source region and a drain region made of a p layer) formed in a semiconductor substrate of a conductivity type. , the semiconductor substrate of the first conductivity type is constituted by an epitaxial growth layer of the first conductivity type formed on the low resistance semiconductor substrate of the first conductivity type, and the semiconductor region of the first conductivity type and the second conductivity type
The first semiconductor region of the second conductivity type is formed such that the peak of its impurity concentration is located at a position deeper than the junction with the first semiconductor region of the second conductivity type. With this configuration, the second semiconductor region of the second conductivity type, the epitaxial growth layer of the first conductivity type, and the first semiconductor region of the second conductivity type are formed.
It is possible to effectively prevent a launch amplifier caused by a parasitic silicon risk formed by the semiconductor region of the first conductivity type and the semiconductor region of the first conductivity type.

Examples Below, a semiconductor device according to the present invention constitutes an LSI.
An example applied to O3 will be described with reference to the drawings. Note that in FIGS. 3A to 3G, the same parts as in FIG. 1 are designated by the same reference numerals, and description thereof will be omitted as necessary.

As shown in Figure 3A, first, for example, the specific resistance is 0.01Ω.
For example, a film with a thickness of 2.5 mm is formed on a low resistance n-type silicon substrate 1 of G.
Epitaxial growth layer 2 with resistivity of 20acm and 5μm
form 1.

Next, as shown in FIG. 3B, an epitaxial growth layer 21 is formed.
For example, a SiO film with a thickness of 300 nm is deposited on the surface of the
□After forming the film 22, a 5iJn film 2 with a thickness of 1000, for example, is formed on this Sin film 22 by, for example, the CVD method.
3 is deposited and formed.

Next, as shown in FIG. 3C, a predetermined portion of the SiJg film 230 is removed by etching to form a Si 3N film 23a with a predetermined shape.
, 23b. Next, for example, a thick photoresist is applied to the entire surface, and then a predetermined portion of this photoresist is removed to form a photoresist 24 having a predetermined shape.

Next, using the photoresist 24 as a mask, SL+N4 films 23a, 23b and 5i are formed in the epitaxial growth layer 21.
By ion-implanting a p-type impurity such as boron B through the O7 film 22 at an acceleration energy of 550 KeV, the epitaxial growth layer 2 is formed as shown in FIG. 3D.
A p-well 4 is formed in 1. Note that since the peak of the impurity concentration in the p-well 4 is located at the bottom of the p-well 4, protrusions 4a and 4b are formed at both ends of the bottom of the p-well 4.

Next, after removing the photoresist 24, as shown in FIG.
Xl013cm-2) and an n-type impurity, such as P (dose amount is, for example, 1.5x1012cm-2) in SiO
□ Ions are implanted into the epitaxial growth layer 21 using the film 22 and film type 2 (B in the epitaxial growth layer 21).
t−o, and P is represented by ・, respectively).

Next, by thermally oxidizing the epitaxial growth layer 21 using the 5iJ4 films 23a and 23b as an oxidation mask, the third F
As shown in the figure, a thick SiO□ film 22 film type 2
□Film 25 (field oxide film) is formed. Further, during this thermal oxidation, P and B ions implanted into the epitaxial growth layer 21 in the step shown in FIG. is formed, and the p-well 4 is annealed.

Next, after removing the Si3N4 films 23a and 23b by etching, as shown in FIG. ．． form 15. Next, using the gate electrode 11 as a mask, the 5i02 film 25a is
A p-type impurity, for example, B, is added to the epitaxial growth layer 21 between the
The source region 2 and drain region 3 made of the P layer are formed by ion implantation at a high concentration.
(By ion-implanting an n-type impurity, for example, P into the p-well 4 between the h-film 25c and the p-well 4 through the sing film 22, a source region 7 and a drain region 8 made of an n'' layer are formed.

In this way, CMO 8 consisting of p-channel MO3FET 17 and n-channel MO3FET 18 is completed. Note that the junction depth of the p-well 4 is approximately 1.5 μm, and the distance X between the p-well 4 and the n-type silicon substrate 1 is approximately 1 μm.
It is m.

FIG. 4 shows the impurity concentration distribution in the direction of arrow A in 0MO3 shown in FIG. 3G above. As is clear from FIG. 4, the peak of the impurity concentration of the p-well 4 is located deep in the epitaxial growth layer 21, and the p-well 4 having such an impurity concentration distribution is
It is called de well.

0MO3 shown in FIG. 3G produced according to the above-mentioned example
1. The through current I11 was determined by examining the relationship between vA and IAX in the same way as in Fig. 2. IH was 0. From this, it can be seen that the latch amplifier is almost completely prevented in the 0MO3 shown in FIG. 3G.

The first reason why launch amplifiers are prevented is that B
By implanting ions at an extremely high acceleration energy of 550 KeV, the p-well 4 is formed as shown in Figure 4.
Parasitic npn as retrograde well structure
This is because βn of the l-transistor could be made extremely small. Secondly, since 0MO3 is formed in the epitaxial growth layer 21 formed on the n-type silicon substrate 1, which has an extremely low resistance of 0.01acm, the resistance Rs (
(see Figure 3G) is significantly reduced, so Ii, xns
This is because <0.6 (v) (tit: current flowing through Rs), and positive feedback is no longer applied to the parasitic pnp transistor.

In addition, in the conventional manufacturing method of 0MO3, B is first ion-implanted into the epitaxial growth layer 21 at relatively low energy, and then heat treatment (drive-in diffusion) is performed at a high temperature of about 1200° C. for a predetermined period of time to obtain the required junction depth. Since the p-well 4 is formed in a large size, B diffuses in the horizontal direction by, for example, about 1.5 to 3 μm during the above heat treatment, which makes it difficult to reduce the planar size of the p-well 4. .

On the other hand, according to this embodiment, the p-well 4 having a desired junction depth can be formed by high-energy B ion implantation. There is no need for long-term heat treatment at high temperatures. Therefore, the lateral diffusion of B becomes substantially O, and therefore, the planar size of the p-well 4 can be made extremely small compared to the conventional one, so that miniaturization of 0 MO3 is possible.

Further, according to the above-described embodiment, there are also the following advantages.

That is, if the capacitance Cj between the p-well 4 and the epitaxial growth layer 21 is large, latch amplifier is likely to occur when the power is turned on for 0MO3, so the smaller C4 is, the better. Since the distance X (see FIG. 3G) with respect to the silicon substrate 1 is selected to be approximately 1.0 μm, C4 is extremely small as shown in FIG. 5, and is almost equal to the bulk value. Therefore, it is possible to effectively prevent latch-up from occurring particularly when the power is turned on. Note that the breakdown voltage between the p-well 4 and the epitaxial growth layer 21 is about 15V, which poses no practical problem.

The present invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of the present invention. For example, in the above embodiment, the acceleration energy during B ion implantation to form the p-well 4 is set to 550 KeV.
However, if the peak of the impurity concentration is located at a position deeper than the junction between the source region 7 and drain region 8 and the p-well 4, it is possible to change the acceleration energy as necessary. Further, the resistivity of the n-type silicon substrate 1 is not limited to the value used in the above embodiment, but if the resistivity is large, it is difficult to reduce Rs, so for example 0.
It is preferably 1Ω or less. Similarly, the film thickness and resistivity of the epitaxial growth layer 21 are not limited to the values used in the above embodiments, but if the film thickness is too large, the crystallinity of the film may deteriorate or protrusions may occur during film growth. It is preferable that the thickness of the film is 5 μm or less, since not only this may occur, but also the cost required to form the film increases. Also, the distance X between the p-well 4 and the n-type silicon substrate 1 can be changed as necessary, but if X is too small, CJ will be large.
is preferably 0.5 μm or more.

Although the p-well 4 was formed in the above embodiment,
It is also possible to reverse the conductivity type of each part of OMO3 shown in FIG. 3G to form an n-well structure.

Effects of the Invention According to the semiconductor device according to the present invention, the semiconductor substrate of the first conductivity type is constituted by an epitaxially grown layer of the first conductivity type formed on the low resistance semiconductor substrate of the first conductivity type, and the above-mentioned The first semiconductor region of the second conductivity type is formed such that the peak of its impurity concentration is located at a position deeper than the junction between the semiconductor region of the second conductivity type and the first semiconductor region of the second conductivity type. Therefore, it is composed of a second semiconductor region of the first conductivity type, an epitaxial growth layer of the first conductivity type, a first semiconductor region of the second conductivity type, and a semiconductor region of the first conductivity type. It is possible to effectively prevent launch-up caused by parasitic cyrisks.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view showing the structure of a conventional OMO3 constituting an LSI, Fig. 2 is a graph showing the relationship between VAK and IAX of parasitic silicon risk, and Figs. 3A to 3G are semiconductor devices according to the present invention. 0M constituting an LSI as an example of
4 is a cross-sectional view showing an example of an O3 manufacturing method in the order of steps; FIG. 4 is a graph showing the impurity concentration distribution in the direction of arrow A in FIG. 3G;
FIG. 5 shows the voltage V applied between the p-well and n-type silicon substrate using the distance X between them in FIG. 3G as a parameter.
It is a graph showing the relationship between and Cj. In addition, in the symbols used in the drawings, 11, 15.22------ Gate electrode 17---
−−−−−−−−・−−−−−p channel MO3FE
T18---------------n-channel MO
5FET21-1---------1---Epitaxially grown layer. Agent Yoshio Katsutsunekane Ueya

Claims (1)

[Claims] a first semiconductor region of a second conductivity type formed in a semiconductor substrate of a first conductivity type; a semiconductor region of a first conductivity type formed in the first semiconductor region of the second conductivity type; and a second semiconductor region of a second conductivity type formed in the semiconductor substrate of the first conductivity type, wherein the semiconductor substrate of the first conductivity type has a low resistance of a first conductivity type. an epitaxially grown layer of a first conductivity type formed on a semiconductor substrate of the present invention, and an epitaxial growth layer of a first conductivity type formed on a semiconductor substrate of the first conductivity type; A semiconductor device characterized in that the first semiconductor region of the second conductivity type is formed such that a peak of impurity concentration is located.