JPS60258958A - Charge transfer type solid-state image pickup element - Google Patents

Abstract

PURPOSE:To improve the manufacturing yield and the performance by a method wherein the threshold voltage which a transfer gate has is risen up to a required value by reducing the channel width of the transfer gate to less than a specific value. CONSTITUTION:In Figs. (a) and (b), the numeral 7' represents the transfer gate, 2-1 an electrode constituting a vertical CCD, and a thick one-point chain line 20 the channel region of the vertical CCD2, the transfer gate region 7'-1, and a photo diode region 1'. When the channel width (w) constituting the transfer gate 7'-1 exceeds 8mum, the threshold value is constant with little variation. However, the reduction in channel width to less than 8mum shows a gradual increase in threshold voltage, and the reduction to less than 3mum shows a rapid increase. Therefore, when the channel width of the transfer gate is reduced more than a value close to 3mum, the threshold voltage rises by the narrow channel effect: it becomes possible to obtain a necessary threshold voltage not by ion implantation as conventional.

Description

Detailed Description of the Invention [Field of Application of the Invention] The present invention relates to a photoelectric conversion element on a semiconductor substrate and a charge transfer element for extracting optical information of each element.
Upled device, hereinafter abbreviated as CCD (1). ) is related to a solid-state image sensor using

[Background of the invention]

Solid-state imaging devices require an imaging plate with a resolution comparable to that of the imaging electron tube used in current television broadcasting, and for this reason, 500 pieces in the vertical direction and 800 to 1 piece in the horizontal direction are required.
A matrix of 000 picture elements (photoelectric conversion elements) and a corresponding scanning element are required. therefore,
The above-mentioned solid-state image sensor is manufactured using MO8 large-scale circuit technology that requires high integration, and generally uses a CCD, a MOS transistor, or the like as a component.

FIG. 1 shows the basic configuration of a CCD-type solid-state image sensor, which is characterized by low noise. 1 is a photoelectric conversion element made of, for example, a photodiode; 2 and 3 are a vertical COD shift register and a horizontal shift register for taking out optical signals accumulated in the photoelectric conversion element group to an output terminal 4; 5 and 6 are clock pulse generators that generate clock pulses for driving the vertical shift register and the horizontal shift register, respectively. Although a two-phase clock pulse generator is illustrated here, (2) either a four-phase or three-phase clock format may be adopted. Further, numeral 7 indicates a transfer gate that sends the charge accumulated in the photodiode to the vertical shift register 2.

In its current form, this device becomes a monochrome image sensor, and when a color filter is laminated on top, each photodiode is provided with color information, making it a color image sensor.

As is well known, solid-state imaging devices have many advantages over electron tubes, such as being small, lightweight, maintenance-free, and low power consumption, and are expected to have a promising future as imaging devices.

However, the current CCD type image pickup device has problems as described below, which greatly hinders its mass production compared to the MO8 type device. In addition, although it has the advantage of low noise, it still has low light sensitivity, and smear (white stripes that appear vertically at the top and bottom of the optical image when exposed to strong light) occurs, reducing image quality. It has not reached a practical level.

Problems with the current device will be explained using the device structure diagram shown in FIG. In FIG. 2(a), (3) forms a photodiode 1 between a substrate (for example, p-type) 10 and a substrate with a different impurity layer (for example, n-type), and 2 is a vertical CCD shift register region. Yes, 2-1.2-2 is C
Electrodes that form an OD shift register (2-1 is made of polycrystalline silicon, for example, the first layer, 2-2 is made of polycrystalline silicon, for example, the second layer), and 2-3 makes the COD shift register an embedded type. A low concentration impurity layer (for example, n-type), 7 is a transfer gate region (here, the COD electrode 2-1 is also used), and 7-1 is a shallow impurity layer for increasing the threshold voltage of the transfer gate. (Implant the same type of impurity as the substrate, for example, p-type, near the surface by ion implantation), 8
9 is a thin oxide film (for example, SiOQ) formed between the gate electrode and the substrate, and 9 is a thick oxide film for electrically insulating and separating each pixel.

FIG. 5B shows the planar configuration of FIG. 1A, in which 1' is a photodiode region, 2-1 is an electrode region that also serves as a transfer gate 7-1, and 7-2 is an impurity implantation region. .

(4) (1) In order to form the impurity implantation region 7-2,
This method requires multiple photomasks, lowering the production yield. Furthermore, if the alignment of this photomask shifts to the right, the CCD channel will expand to the 11 area (a pocket area will occur).
Charge transfer efficiency decreases. Further, when shifted to the left, the width of the CCD channel at the portion 12 becomes narrower, so a potential wall is generated due to the narrow channel effect (that is, the threshold voltage at this portion increases), and the transfer efficiency also decreases.

(2) Charges generated on the photodiode side flow into the vertical CCD shift register 2 through the region 13 corresponding to the lower part of the transfer gate 7, generating smear.

(3) Since the channel width W of the transfer gate is large, the area for taking in light (so-called aperture ratio) decreases, resulting in poor photosensitivity.

Therefore, in order to improve the manufacturing yield and performance of CCD type devices and to put them into practical use, it is important to improve the configuration and structure of the transfer gate described above. (5) [Object of the Invention] An object of the present invention is to solve the above-mentioned problems, that is, to fundamentally improve the manufacturing yield and performance of CCD type image pickup devices.

[Summary of the invention]

In order to achieve the above object, the present invention eliminates the need to form an impurity injection layer under the transfer gate region, and narrows the channel width of the transfer gate to a few μm or less, thereby increasing the threshold voltage of the transfer gate to a predetermined value. It is intended to raise the value. This makes it possible to omit the manufacturing process of the impurity layer, which improves the manufacturing yield, and also makes it possible to improve the reduction in transfer efficiency, occurrence of smear, and reduction in the aperture ratio that were caused by the presence of the impurity injection layer. C.C.
The performance of the D-type element can be improved.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail using Examples.

FIG. 3 shows the configuration and structure of the CCD type image sensor of the present invention. In FIG. 3(a), 7' is a transfer gate, and in FIG. 3(b), 2-1 is an electrode (for example, the first layer of polycrystalline silicon) constituting the vertical CCD (6).
A thick one-dot chain line 20 indicates the channel region of the vertical CCD 2, the transfer gate region 7'-1, and the photodiode region 1'. The channel width W constituting the transfer gate 7'-1 shown in this embodiment is designed to be smaller than the channel width W of the transfer gate shown in the conventional example shown in FIG.
w < W).

The reason for reducing the channel width W of the transfer gate in the COD element of the present invention and its effects will be explained below with reference to FIG. FIG. 4 shows the results of fabricating a plurality of MoS transistors with different channel widths on the same semiconductor substrate and measuring the threshold voltage of each transistor. In the figure, the horizontal axis represents the channel width of the transistor, and the vertical axis represents the normalized threshold voltage when the threshold voltage of a transistor having a channel width of 10 μm or more is set to 1. From the same figure, the channel width) is 8 μm.
Beyond that, the threshold value remains constant with almost no change;
It can be seen that the threshold voltage gradually increases when the diameter becomes smaller than 8 μm, and increases rapidly when the diameter becomes smaller than 3 μm (7).

Hereinafter, the effect that this threshold voltage increases rapidly when the channel width narrows to a certain extent will be referred to as the narrow channel effect.

This result shows that when the channel width of the transfer gate is made smaller than around 3 μm, the threshold voltage increases due to the narrow channel effect, and it is not necessary to implant ions under the gate to increase the threshold voltage as in conventional transfer gates. For example, it becomes possible to obtain a threshold voltage of
Threshold voltage 1, which is very commonly used in conventional elements,
When trying to obtain 5 to 2V, the channel width can be set as follows. When designing a gate oxide film of 500 A using a p-type substrate of 5×10”/d, the threshold voltage of a non-doped MOS transistor (surface channel type, no ion implantation) is ~0.7 V. Therefore, When trying to obtain the above value (1,5~2V),
It is sufficient to set the channel width to about 2 μm (using 2.4 times the normalized threshold voltage for 2 μm, (
8) 0.7X2.4=1.7 (V)).

As explained above, many advantages can be obtained by obtaining the desired threshold voltage by making the transfer gate a narrow channel as in the present invention without implanting ions under the transfer gate as in the conventional case. This can solve the problems of conventional devices.

(1) By reducing the number of photomasks by one and the associated manufacturing steps, the manufacturing yield can be improved and the time required for manufacturing can be shortened. As a result, the cost of the device can be reduced.

(2) Vertical C due to the elimination of ion implantation
Pocket areas that occur in the OD can be eliminated, and vertical COD transfer efficiency is improved.

This results in improved vertical resolution. Furthermore, it is possible to prevent color mixture from occurring due to the mixing of the left-over front row signal charge and the new rear row signal charge.

(3) By narrowing the transfer gate region, it is possible to reduce the amount of smear charge that, in conventional devices, passes under the transfer gate and diffuses toward the vertical C0D(9) side.

As a result, the smear generated in the device of the present invention becomes extremely small.

(4) The area of the transfer gate region is reduced, and the aperture ratio is improved accordingly (light sensitivity is improved). Alternatively, it becomes possible to reduce the size of pixels, which is an effective means for realizing a high-resolution device.

(5) The electrode capacitance is reduced by the reduction in the transfer gate region, and the power consumption required for driving can be reduced.

In the embodiment shown in FIG. 3, the transfer gate electrode is vertically COD.
It is shared with the electrode and is formed of, for example, the first layer of polycrystalline silicon. The transfer gate electrode is vertical CC as shown in FIG.
It may be formed separately from the D electrode, for example, as a third layer electrode. In FIG. 5, 7#-2 is a third layer electrode (polycrystalline silicon, a metal such as AQ or Mo, or an alloy of silicon and metal, etc.) forming a transfer gate electrode, and is a transfer gate area. 7 “−1” (
10) The channel width W is set narrow as in the case of FIG. With this narrow channel structure, effects (1) to (4) obtained in the embodiment of FIG. 3 can be obtained.

Figure 6 shows that the photodiode is not of the junction type shown in Figure 3, but of the MIS type (jetal-type).
This is an example of the case where the 14 is a transparent electrode constituting the MIS type photodiode, and 15 is an oxide film (gate oxide film 8) that insulates and separates the substrate 10 and the electrode 14.
(The film thickness may be approximately the same as or slightly thicker.) When a predetermined voltage is applied to the transparent electrode 14, a depletion layer 16 is formed on the substrate surface, and optical signal charges are accumulated here (in this embodiment, the transparent electrode is described so as to cover the entire surface, but A depletion layer is not formed in region 9 where the oxide film is thick.

Furthermore, there is no problem in the COD region 2 and the transfer gate region 7'-1 since they are shielded by the electrodes). Even in this case, the configuration of the transfer gate and the advantages obtained
A9. □3. . □ months. -16Ah, I'll omit ゎ明.

(11) In the previous embodiments, we considered raising the transfer gate only by the narrow channel effect, but in the following, we will explain how to raise the transfer gate by the narrow channel effect and by thickening the gate oxide film of the transfer gate. When using ion implantation together, etc. will be explained. Even in these cases, if a mask for controlling the oxide film thickness or a mask for ion implantation is used, problems similar to those of conventional elements will arise, so in realizing the following embodiments, the same problems as those of the previous embodiments will be used. Similarly, masks shall not be used.

FIG. 7 shows a case in which not only the transfer gate has a narrow channel W but also the gate oxide film 8'-2 is thickened.

The transfer gate 7'' of this structure can be manufactured without using a special mask by forming it, for example, from the second layer of polycrystalline silicon 2-2.

(1) Gate oxide film 8 having a thin film thickness t&x on the substrate
'-1 is formed, and then a first layer of polycrystalline silicon is laminated. The polycrystalline silicon described in step (12) is processed into the shape of a CCD electrode pattern by photoetching. Furthermore, the gate oxide film is etched using this CCD electrode as a mask, and the oxide film 8'-- is etched only under the gate electrode.
Leave 1.

(2) Oxide film 8'- having the thicker film thickness T/I
2 is formed, and then a second layer of polycrystalline silicon is laminated. The second layer of polycrystalline silicon is etched by photo-etching.
Process into the shape of CD electrode and transfer gate electrode pattern. Furthermore, the gate oxide film is etched using this electrode as a mask. As a result, the gate oxide film under the transfer gate 7'' can be made thicker than in other regions (T,
This makes it possible to raise the threshold voltage beyond that obtained by the narrow channel effect.

Here, in addition to the transfer gate region 7N-1, the oxide film in the second layer electrode region of the vertical COD (that is, the region indicated by the dotted line 17) becomes thicker, and in the vertical CCD, the oxide film under the second layer electrode becomes thicker. Although the value voltage is higher than that under the first layer electrode, by adjusting the externally applied voltage applied to the first electrode 2-2 (13), the potential at the time of charge transfer to be formed under the main electrode is set to, for example, the first layer. There is no problem at all since it can be done in the same manner as under electrode 2-1.

Here, the two masks used were originally the first layer and the second layer.
This is necessary for processing the layered electrodes, and does not require a mask for forming the transfer gate.
The thickness of the oxide film under the transfer gate can be achieved by self-alignment using the second layer electrode as a mask (no photomask is required, so there is no misalignment). The aforementioned problem (1) does not occur either. Therefore, the five effects (advantages) described in the embodiment of FIG. 3 can be obtained also in the transfer gate of this structure.

FIG. 8 shows the structure of a transfer gate that uses a narrow channel W and ion implantation. Reference numeral 7' denotes a transfer gate formed of the second layer electrode, which is shared with the vertical CCD electrode 2-2. Reference numeral 18 denotes an ion implantation layer (for example, a p-type impurity of the same type as the substrate, (14) a layer made of boron atoms) implanted to raise the threshold voltage under the transfer gate. This ion implantation can be performed by self-alignment without requiring a photomask.

(1) Form the first layer electrode 2-1 constituting the vertical CCD.

(2) Before laminating the second layer of electrodes, p-type impurities are implanted into the region 18-1 indicated by solid diagonal lines.

Here, impurities are not implanted into the region 2-1 where the first layer electrode is formed and the region 9 where the oxide film is thick, with 2-1 and 9 serving as masks. Next, the second layer of electrodes is processed by photoetching to form the CCD electrode 2.
-2, transfer gate 7'-1 is formed 9 (3) Impurity atoms (for example, n-type, phosphorus atoms) for the photodiode are diffused. Here, the n-type impurity atoms are diffused only in a region 19 shown by dotted diagonal lines in a self-aligned manner. Other areas are electrodes 2-1 1, 2-2, 7'-1 punishment"
It is masked by the thick oxide film 9 and is not diffused. Since the amount of diffusion of these impurity atoms is usually much larger than the amount of p-type impurity implanted above (15), the p-type ion implantation layer in the photodiode region 1' disappears and becomes entirely an n-type diffusion layer.

Through the above steps (1) to (3), an ion-implanted layer of p-type impurity is eventually formed under the CCD electrode 2-2 and the transfer gate electrode 7'-1. Therefore, in this embodiment as well, in the vertical COD, the threshold voltage under the second layer electrode is higher than that under the first layer electrode, but for the same reason as mentioned above, it is completely difficult to operate the vertical COD. No problem. As described above, in the transfer gate of this structure, ion implantation can be performed without using a photomask, making it possible to raise the threshold voltage beyond that obtained by the narrow channel effect. Further, five advantages can be obtained as in the case of the embodiment shown in FIG.

〔Effect of the invention〕

As explained above in detail using the embodiments, by modifying the structure of the transfer gate as in the present invention, (i) improvement of production yield and reduction of production process time (16) realization of cost reduction; , (it) improvement in vertical resolution and prevention of color mixture, and (iii) reduction in smear and improvement in photosensitivity.

[Brief explanation of drawings]

Figure 1 shows the basic configuration of a CCD type image sensor, Figure 2 shows the basic configuration of a CCD type image sensor.
The figures show a conventional transfer gate structure constituting the CCD type element shown in Fig. 1, Fig. 3 is a sectional view and a plan view of essential parts showing the structure of a transfer gate according to an embodiment of the present invention, and Fig. 4 is a graph explaining the narrow channel effect, and FIGS. 5 to 8 are cross-sectional views of main parts of transfer gate structures according to other embodiments of the present invention, and (17) J (%J

Claims (1)

[Claims] A group of photoelectric conversion elements on the same semiconductor substrate, a transfer gate that reads out the signal charge accumulated in the element, a group of vertical COD shift registers and a horizontal COD that sends the read out charge toward the output.
In a charge transfer solid-state image sensor with an integrated shift register, the channel width of the transfer gate is 3 μm.
smaller and the transfer gate is of surface channel type (
A charge path is formed on the surface of the semiconductor substrate, thereby making the threshold voltage of the transfer gate region higher than the threshold voltage of the vertical COD shift register region. Transportable solid-state image sensor.