JP2001308310A - Photoelectric conversion element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that a low voltage and low power consumption cannot be achieved since a substrate voltage is increased when the impurity concentration profile of a P-type region is changed to increase the inclination of knee characteristics while the substrate voltage and the inclination of the knee characteristics of a photoelectric conversion element in vertical-type overflow drain structure are expressed by the function of an impurity concentration profile such as the impurity concentration and thickness of the P-type region for forming a VOD barrier. SOLUTION: Directly below the center part of an N-type region 103 of a photoelectric conversion element 201, the impurity concentration of a P-type region 122 that is buried into an N-type silicon substrate 101 for forming is set higher than that of a P-type region 102 around the P-type region 122, or the thickness of the P-type region 122 is set thicker than that of the P-type region 102. Influence to the VOD barrier in the P-type region 122 by a P+ channel stopper 105 and the P-type region 107 is reduced, the inclination of knee characteristics is increased, at the same time the substrate voltage is decreased, the power consumption in a solid-state image pickup element such as a CCD image pickup is reduced, at the same time, the dynamic range of the quantity of light is expanded, and gradation can be fined.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric conversion element used for a solid-state imaging device and the like, and more particularly, to a photoelectric conversion device capable of reducing power consumption and fine gradation when applied to a solid-state imaging device. It relates to a conversion element.

[0002]

2. Description of the Related Art FIG. 11 is a schematic plan view of a conventionally used solid-state imaging device. Figure 11 shows an interline type CC
4 shows a D image sensor. A vertical CCD 202 is arranged adjacent to each row of the two-dimensionally arranged photoelectric conversion elements 201, and is connected to the photoelectric conversion elements 201 via a transfer gate 203. A lower end of each of the vertical CCDs 202 is connected to a horizontal CCD 204, and an amplifier 205 is connected to an end of the horizontal CCD 204. In addition, between the photoelectric conversion elements 201, between the photoelectric conversion element 201 and the vertical CCD 202,
There is a P ⁺ channel stopper 206 between the photoelectric conversion element 201 and the horizontal CCD 204. In such a CCD image sensor, the photoelectric conversion element 201
The signal charges photoelectrically converted by the transfer gate 2
After being read out to the vertical CCD 202 via the line 03, the data is transferred by the vertical CCD 202 and the horizontal CCD 204, amplified by the amplifier 205, and output.

FIG. 12 shows a conventional unit pixel of the CCD image sensor. FIG. 12 (a) is a schematic plan view of the unit pixel, and FIG. 12 (b) is a schematic sectional view taken along line X1-X1 of FIG. It is. However, for the sake of simplicity, FIG. 1A does not show a gate electrode, a light shielding film and the like, and FIG. 2B does not show a cover film and a micro lens. In this figure, the stored charges are electrons. As shown in FIG. 3A, the unit pixel is composed of a photoelectric conversion element 201, a vertical CCD 202, a transfer gate 306, and a P ⁺ channel stopper 305. In FIG. 3B, a P-type region 302 is formed in an N-type silicon substrate 301 in a buried state. The photoelectric conversion element 201 has an N-type region 303 for storing signal charges photoelectrically converted on the N-type silicon substrate 301 on the substrate surface side of the P-type region 302.
P ⁺ is located above the N-type region 303, that is, on the substrate surface.
A region 304 is formed to suppress generation of dark current via an interface state between the region 304 and an insulating film such as an oxide film. P wherein P ⁺ region 304 is formed around the N-type region 303 ⁺
It is connected to the channel stopper 305, and its Fermi level is fixed to the ground potential. Further, a transfer gate region 306 (transfer gate 203 in FIG. 11) of P type is formed between the photoelectric conversion element and the vertical CCD.

On the other hand, the vertical CCD 202 has a charge transfer region composed of an N-type region 308 formed on a P-type region 307 formed in the N-type silicon substrate 301, and a gate insulating film 309 above the charge transfer region. And a gate electrode 310 formed in this way. The P-type region 307 is electrically connected to the P ⁺ channel stopper 305,
The Fermi level is fixed at the ground potential. Then, an interlayer insulating film 312 is formed so as to cover the gate electrode 310 or the photoelectric conversion element.
On the interlayer insulating film 312, a light-shielding film 31 opened only at the upper part of the photoelectric conversion element so that light is incident only on the photoelectric conversion element.
1 is formed.

In such a CCD image sensor, light enters the photoelectric conversion element 201 and signal charges generated by the photoelectric conversion element 201 are accumulated in the N-type region 303, and a high voltage is applied to the gate electrode 310 at a desired timing. Is applied, the transfer gate region 306 is turned on, and the signal charges are read out to the vertical CCD 202. At this time N
The type region 303 is depleted, and the voltage is set so that the potential of the on state of the transfer gate region 306 and the potential of the N-type region 308 to be read out are higher than the potential. After that, the transfer charge is transferred by the vertical CCD 202 with the transfer gate region 306 turned off.

FIG. 13 schematically shows a potential distribution when the N-type region 303 of the photoelectric conversion element 201 and the N-type region 308 of the vertical CCD 202 are depleted. FIG. 13 corresponds to the cross-sectional structure of FIG. FIG.
In FIG. 14, the transfer gate region 306 is off, and the potential distribution along the lines X2-X2 and X3-X3 in FIG. 13 is schematically shown in FIG.
Indicated by SB. Although it does not appear in FIG. 14 for a vertical CCD,
The silicon substrate 301 and the gate insulating film 3 along the depth direction
The potential increases from the interface 09 toward the inside of the N-type region 308, and reaches a maximum at a certain depth. After that, the potential decreases toward the P-type region 307 and the P-type region 307
Then, the Fermi level is at the ground potential. Thereafter, as shown by the SB line in FIG. 14, the potential increases toward the substrate voltage applied to the N-type silicon substrate 101. In the photoelectric conversion element 201, as indicated by the SA line, the Fermi level of the P ⁺ region 304 on the surface is at the ground potential, and the N-type region 303 extends along the depth direction.
The potential increases inward, and reaches a maximum at a certain depth. Thereafter, the potential is minimized in the P-type region 302 and increases toward the substrate voltage applied to the N-type silicon substrate. Here, a potential barrier formed substantially at the center of the P-type region 302 buried in the N-type silicon substrate 301 is referred to as a VOD barrier. The VOD barrier can be controlled by the substrate voltage, and the blooming suppression operation of sweeping excess charge exceeding the saturation signal amount to the substrate and the electronic shutter operation of sweeping charge accumulated in the N-type region 303 of the photoelectric conversion element 201 to the substrate. (The substrate voltage at this time is called the substrate extraction voltage.)
Can be performed. The structure of the photoelectric conversion element 201 is called a vertical overflow drain structure.

[0007]

The VOD barrier is P
The impurity concentration profile of the ⁺ region 304, the N-type region 303, the P-type region 302, and the N-type substrate 301, that is, the potential distribution determined by the one-dimensional impurity concentration profile in the depth direction and the substrate voltage. And the photoelectric conversion element 2
When the dimension of “01” is large, the VOD barrier has a region where the potential is flat in the horizontal direction. However, when the dimensions of the photoelectric conversion element 201 are reduced, the VOD barrier is accordingly changed to the P ⁺ channel stopper 305.
And the potential of the P-type region 307,
The region where the potential of the D barrier is flat is reduced. That is, as described above, the P ⁺ channel stopper 3
This is because the Fermi level of the P-type region 05 and the P-type region 307 is 0 V, which is lower than the VOD barrier potential. Therefore, when the size of the photoelectric conversion element 201 is reduced, the potential at the end of the VOD barrier region is reduced. . Then, as the miniaturization further proceeds, the flat region of the potential of the VOD barrier disappears, and the potential of the VOD barrier also decreases. The situation at this time is shown in FIG. FIG. 15 is a schematic diagram of the potential distribution along the line X4-X4 in FIG. 13, which is maximum at the VOD barrier. That is, in FIG. 13, the VOD barrier is a saddle point of the potential.

As the photoelectric conversion element 201 is miniaturized in this way, the electrical connection between the P ⁺ channel stopper 305 and the P-type region 307 with respect to the VOD barrier becomes stronger, so that the VOD barrier potential varies with the substrate voltage. It becomes difficult to do. That is, the rate of change of the VOD barrier potential with respect to the substrate voltage decreases. This results in an increase in the substrate withdrawal voltage for the electronic shutter operation, and the CCD
This leads to an increase in power consumption of the image sensor.

The easiness of the change of the VOD barrier potential with respect to the substrate voltage also affects the knee characteristics. The knee characteristic refers to a characteristic in which the inclination changes at a certain point in the relationship between the amount of signal charge stored in the photoelectric conversion element 201 and the amount of light. FIG. 16 shows the relationship between the light amount and the signal charge amount of the photoelectric conversion element 201 having the vertical overflow drain structure shown in FIG. 12 on a semilog scale. Up to the saturation signal amount, the signal charge amount changes linearly with respect to the light amount (it becomes a curve on the logarithmic scale in the figure), and is proportional to the logarithm of the light amount above the saturation signal charge amount. The latter region in which the signal amount changes with the logarithm of the light amount is referred to as a knee region, and the change amount of the signal charge amount with respect to the logarithm of the light amount in the knee region is referred to as a knee characteristic slope. The slope of the knee characteristic is related to the amount of change in the VOD barrier potential with respect to the substrate voltage. The smaller the amount of change, the smaller the slope of the knee characteristic. As described above, as the photoelectric conversion element 201 is miniaturized,
Since the electrical connection of the VOD barrier to the P ⁺ channel stopper 305 and the P-type region 307 becomes stronger, the amount of change in the VOD barrier potential with respect to the substrate voltage becomes smaller. Therefore, the slope of the knee characteristic becomes smaller.

As described above, since the signal charge amount in the knee region is proportional to the logarithm of the light amount, a wider range of light amount can be imaged within a certain signal charge amount than when it changes linearly. That is, the dynamic range of the light amount can be expanded, so that a high-contrast subject can be imaged. In recent years, there has been an increasing demand for image sensors having an increased dynamic range for use in vehicles and industries such as FAs. To meet this demand, the use of knee regions has been performed. In this case, the greater the slope of the knee characteristic, the greater the difference in the signal amount corresponding to the difference in the light amount, and the gradation of the light amount can be reduced. Further, when a single-plate color image sensor is formed by laminating on-chip color filters, a color signal is obtained by adding and subtracting the signal charge amount of each color in the knee region where the logarithm changes, so that the gradation of the light amount is small. Problems such as false colors are less likely to occur. Therefore, it is desired to increase the inclination of the knee characteristic for use in expanding the dynamic range.

However, in the conventional solid-state imaging device (CCD image sensor) shown in FIG. 12, the substrate extraction voltage and the slope of the knee characteristic are functions of the impurity concentration profile of the P-type region 302 and the size of the photoelectric conversion element. As the impurity concentration of the P-type region 302 is increased or the thickness of the P-type region 302 (the width in the depth direction of the substrate) is increased, the substrate extraction voltage and the slope of the knee characteristic increase. Therefore, in the conventional CCD image sensor, P
The impurity concentration of the mold region 302 is increased or increased to increase the slope of the knee characteristic. However, in this case, the substrate withdrawal voltage is increased, and lower voltage and lower power consumption are required. The problem of not being able to do so arises.

According to the present invention, a p-type region having a higher impurity concentration or a thicker region than a peripheral region is formed immediately below a central portion of a photoelectric conversion element, thereby reducing a substrate pull-out voltage and improving knee characteristics. It is an object of the present invention to provide a photoelectric conversion element having an increased inclination.

[0013]

The photoelectric conversion element of the present invention is a vertical overflow drain type photoelectric conversion element for sweeping surplus electric charges generated in the photoelectric conversion element to a semiconductor substrate. , A first barrier region of a second conductivity type and a second barrier region of a second conductivity type are provided.
The photoelectric conversion element and at least an element isolation region are formed on the barrier region, the first barrier region is formed below the photoelectric conversion element, and the second barrier region is formed in a region other than the first barrier region. And wherein the first barrier region is formed to have a higher impurity or a larger thickness than the second barrier region.

As the first photoelectric conversion element of the present invention, the first barrier region and the second barrier region adopt any one of the following application forms. That is, as a first application form, the first barrier region and the second barrier region are formed continuously in a plane. As a second application form, the first barrier region and the second barrier region are formed. As a third application mode, the first and second barrier regions are formed apart from each other.
Is 1.1 to 3 times higher than the second barrier region.
As a fourth application mode having a high impurity concentration, the first
Is 1.1 to 3 times higher than the second barrier region.
As a fifth application mode, the photoelectric conversion element is
As a sixth application mode, the photoelectric conversion element includes a photoelectric conversion element including a charge accumulation region of a first conductivity type that accumulates photoelectrically converted charges, wherein the first barrier region has a plane area equal to the charge accumulation region. A charge storage region of the first conductivity type for storing the converted charge is included, and the first barrier region has a smaller plane area than the charge storage region.

A second photoelectric conversion element according to the present invention is a vertical overflow drain type photoelectric conversion element for sweeping surplus electric charges generated in the photoelectric conversion element to a semiconductor substrate, wherein the photoelectric conversion element is provided in a first conductivity type semiconductor substrate. A conversion element and at least an element isolation region are formed, and a first barrier region of a second conductivity type is formed below the photoelectric conversion element.

As the second photoelectric conversion element of the present invention, the first barrier region adopts the following application mode. That is, the photoelectric conversion element includes a charge accumulation region of a first conductivity type that accumulates photoelectrically converted charges, and the first barrier region has a plane area equal to the charge accumulation region. The photoelectric conversion element includes a charge accumulation region of a first conductivity type for accumulating photoelectrically converted charges, and the first barrier region has a smaller planar area than the charge accumulation region;
As a third application mode, a region where the first barrier region is not formed due to an influence of a potential from the element isolation region and the first barrier region has a higher charge accumulation than the first barrier region. The electric barrier to the region is large, and the excess charge flows only to the semiconductor substrate.

According to the first photoelectric conversion device of the present invention, the first barrier region is formed to have a higher impurity concentration or a higher impurity concentration than the second barrier region, so that an element isolation region or the like to the VOD barrier can be formed. And the potential of the VOD barrier at the center of the photoelectric conversion element becomes a value determined by the one-dimensional impurity concentration profile in the depth direction, a flat region of the potential is formed, and the change of the VOD barrier potential with respect to the substrate voltage. Increases, the substrate pull-out voltage decreases, and the slope of the knee characteristic increases.

Further, according to the second photoelectric conversion element of the present invention, when the distance between adjacent first barrier regions is reduced due to the miniaturization of the unit pixel size, the region where the first barrier region is not formed is formed. Is equivalent to the presence of the second barrier region in the first photoelectric conversion element, and the VOD barrier at the center of the photoelectric conversion element can reduce the influence of the element isolation region. Thereby, VO with respect to the substrate voltage is obtained.
The rate of change in the D barrier potential increases, and the slope of the knee characteristic increases as the substrate pull-out voltage decreases.

[0019]

Embodiments of the present invention will now be described with reference to the drawings. In the following, a case will be described in which all accumulated charges are electrons. (First Embodiment) FIG. 1 shows a solid-state image pickup device according to the present invention, in which the inclination of the knee characteristic is increased while reducing the substrate pull-out voltage, here corresponds to the unit pixel of the CCD image sensor shown in FIG. It is sectional drawing of 1st Embodiment. Although FIG. 1 shows a cross-sectional structure of a portion corresponding to line X1-X1 in FIG. 12A, a cover film, a microlens, and the like are not shown. In the figure, an N-type silicon substrate 101
P-type regions 102 and 122 are formed in a buried state. Here, the P-type region 122 is formed only in a region immediately below the photoelectric conversion element 201 according to the present invention, and the P-type region 102 is formed in a surrounding region. The photoelectric conversion element 201 is provided in the P-type region 10.
An N-type region 103 for accumulating signal charges photoelectrically converted is formed on the substrate surface side of the N-type region 1.
A P ⁺ region 104 is formed in the upper portion of the substrate 03, that is, on the surface of the N-type silicon substrate 101, and suppresses generation of dark current via an interface state between the substrate and an insulating film such as an oxide film.
Further, the P-type region 122 has a smaller planar area projected onto a plane corresponding to FIG. 12A than the N-type region 103, and the width w 1 of the P-type region 122 is smaller than that of the N-type region 103 in FIG.
Is smaller than the width W1. Also, the P-type region 122
Have a higher impurity concentration than the P-type region 102. The P ⁺ region 104 on the surface of the N-type region 103 is connected to a P ⁺ channel stopper 105 formed around the N-type region 103, and the Fermi level is fixed at the ground potential.

Further, the photoelectric conversion element 201 and the vertical CC
A transfer gate region 106 (203) of P type is formed between D202. On the other hand, the vertical CCD 202 has a charge transfer region including an N-type region 108 formed on a P-type region 107 formed on a surface side region of the N-type silicon substrate 101, and a gate insulating film 109 thereon. The gate electrode 110 is formed through the gate electrode 110. The P-type region 107 is electrically connected to the P ⁺ channel stopper 105, and its Fermi level is fixed at the ground potential. In addition, an interlayer insulating film 112 is formed on the entire surface, and a light-shielding film 111 having an opening only at an upper portion of the photoelectric conversion element is formed on the interlayer insulating film 112 so that light is incident only on the photoelectric conversion element.

According to the above configuration, the photoelectric conversion element 201
Are generated in the N-type region 103, a high voltage is applied to the gate electrode 110 at a desired timing to turn on the transfer gate region 106, and the signal charge is read out to the vertical CCD 202. At this time,
The N-type region 103 is depleted, and the voltage is set so that the potential of the transfer gate region 106 in the ON state and the potential of the N-type region 108 to be read out are higher than the potential. After that, the transfer gate region 106
Is turned off, and signal charges are transferred by the vertical CCD 202.

Here, the CCD image sensor shown in FIG.
A method for manufacturing the semiconductor will be described. First, 10¹⁴/ C
m^ThreeSurface of N-type silicon substrate 101 with phosphorus concentration
A thermal oxide film having a thickness of 20 to 60 nm is formed on the
0.5 to 3 MeV, 0.5 to 5 × 1 in the area corresponding to 2
0¹¹/ Cm^TwoOf boron is ion-implanted. Next,
In the region corresponding to the P-type region 122 by the lithography technology
Open the photoresist and use the same energy as the P-type region 102
Ion implantation of boron at a dose of 1.1 to 3 times
And heat treatment at 900-980 ° C for 30 minutes to 2 hours.
P-type regions 102 and 122 are formed. However,
Consider the spread of boron due to heat treatment when opening the photoresist.
Decide with consideration. Next, lithography technology and ion implantation
20 to 40 KeV, 1 to 5 × 10
¹³/ Cm^TwoP by ion implantation of boron⁺Channels
The topper 105 is set to 200 to 500 KeV, 1 to 5 × 10
¹²/ Cm^TwoRegion 103 by ion implantation of phosphorus
From 20 to 60 keV, 10¹² / Cm^TwoTwo boron i
Shallow P on surface due to on-implantation⁺The area 104 is set to 70 to 1
50 KeV, 1-5 × 10¹²/ Cm^TwoPhosphorus ion injection
Input, the N-type region 108 is set to 200 to 400 KeV, 1
~ 5 × 10¹²/ Cm^TwoP type by boron ion implantation
The region 107 is set at 40 to 100 KeV, 0.5 to 3 × 10
¹²/ Cm^TwoTransfer by boron ion implantation
Form gate region 106, 900-980 ° C., 30 minutes
Ion implantation by heat treatment in nitrogen atmosphere for ~ 1 hour
The activated dopant is activated. Next, the thermal oxide film is
After wet etching with the gate insulating film 109 (this
Here, a 50 to 100 nm thick gate acid is formed by wet oxidation.
Film), and then lithography and etching
The polysilicon gate electrode 110 mixed with the dopant is
Form. Further, an interlayer insulating film 112 is formed, and photoelectric conversion is performed.
Lithography and etching
The CCD image sensor shown in FIG.
To achieve.

FIG. 2 shows the N-type region 1 of the photoelectric conversion element 201.
The potential distribution when the N-type region 03 and the N-type region 108 of the vertical CCD 202 are depleted is schematically shown in a cross section in FIG. The figure shows a state where the transfer gate region 106 is off. FIG. 3 schematically shows the potential distribution along the line A3-A3 in FIG. Here, the P-type region 10
Nos. 2 and 122 have their respective impurity concentrations adjusted so that the VOD barrier potential is equal to that of the conventional example.
As a result, a P-type region 122 having a higher impurity concentration than the surrounding P-type region 102 is formed in the region including the central portion of the photoelectric conversion element 201 as compared with the conventional potential distributions shown in FIGS. Therefore, it can be seen that a region with a flat potential is formed as the VOD barrier.

The reason will be described with reference to FIG. FIG. 4 schematically shows a potential distribution along the line A4-A4 in FIG. 2 using the impurity concentration of the P-type region 122 as a parameter. As can be seen from the figure, even when the same substrate voltage is applied to the N-type silicon substrate 101, the potential of the VOD barrier is higher in the P2 region S2 having the lower impurity concentration than in the S1 having the higher impurity concentration. P ⁺ channel stopper 105
And P-type region 107 have no effect, P
VO in a cross section along line A2-A2 passing through the mold region 102
The D barrier potential Vb2 is higher than A1 passing through the P-type region 122.
It becomes higher than the VOD barrier potential Vb1 in the cross section along the -A1 line. As described in the conventional example, Vb2 actually decreases due to the influence of the P ⁺ channel stopper 105 and the P-type region 107, but the low impurity concentration of the P-type region 102 adjacent to the P-type region 122 , Photoelectric conversion element 2
01 can reduce or eliminate the influence of the P ⁺ channel stopper 105 and the P-type region 107 on the VOD barrier potential Vb1 at the center. However, the amount of decrease in Vb2 is V
The amount must not affect b1. This can be controlled by the impurity concentration difference between the P-type region 122 and the P-type region 102. If the impurity concentration difference is too small, the effect of increasing the knee characteristic is small, and if the impurity concentration difference is too large, the VOD barrier potential is more likely to be along the A2-A2 line. Is higher than the one along the A1-A1 line,
Excess charge is discharged through a narrow region of the P-type region 102 around the photoelectric conversion element 201, and the effect of increasing the knee characteristic is lost.

The reason why the effect of increasing the knee characteristic is lost when the impurity concentration difference is large is as follows. The VOD barrier potential in the area where the surplus charge is swept out is P
Due to the VOD barrier potential in the mold region 122 and the influence of the P ⁺ channel stopper 105 and the P-type region 107, a region having a flat potential disappears as in the conventional example. Therefore,
The VOD barrier potential does not easily change with respect to the substrate voltage, and the slope of the knee characteristic decreases. As a result of the experiment, the P-type region 122
The impurity concentration of P-type region 102 to 1.1.
It has been found that the inclination of the knee characteristic can be increased by increasing the concentration to about three times. This indicates that the influence of the P ⁺ channel stopper 105 and the P-type region 107 on the VOD barrier is reduced. Under the optimum condition among these conditions, the potential of the VOD barrier at the center of the photoelectric conversion element 201 has a value determined by the one-dimensional impurity concentration profile in the depth direction, and a region with a flat potential is formed. As described above, the VOD barrier is formed by the P ⁺ channel stopper 105 and the P ⁺
Since the influence of the mold region 107 can be reduced, the rate of change of the VOD barrier potential with respect to the substrate voltage increases, and the slope of the knee characteristic increases as the substrate pull-out voltage decreases.

(Second Embodiment) FIG. 5 shows a cross-sectional structure of a second embodiment. Note that the same structures as those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. In the second embodiment, instead of the P-type region 122 formed immediately below the photoelectric conversion element of the first embodiment, the P-type region 122 is formed immediately below the central region of the photoelectric conversion element 201, and the P-type region is formed therearound. A P-type region 132 separated from the region 102 is provided. The P-type region 102 and P
The space L between the mold regions 132 is designed to be about 1 μm or less. Further, the method of manufacturing the CCD image sensor shown in FIG.
A photoresist is opened in a region corresponding to each by a photolithography technique, and boron is ion-implanted. The opening position of the photoresist, the energy and dose amount at the time of boron ion implantation, and the method of forming other regions are the same as those in the first embodiment.

According to the second embodiment, FIG.
Along the 2-B2 line, the P-type region 132 and the P-type region 102
Is not formed, a VOD barrier cannot be formed with a one-dimensional profile along this line. However, since the distance L of the region where the P-type region is not formed is about 1 μm, the potential of that region is the P-type region 132 and the P-type region 1.
02, P ⁺ channel stopper 105, and P-type region 1
07, a two-dimensional and three-dimensional effect of these potentials forms a VOD barrier, and the VOD barrier potential Vb1 passes through the P-type region 132 along the line B1-B1 in FIG. It can be designed to be equal to or slightly lower than the potential Vb2. Therefore, as in the above-described first embodiment,
Under optimal conditions, the VO at the center of the photoelectric conversion element 201
The potential of the D barrier has a value determined by the one-dimensional impurity concentration profile in the depth direction, and a region having a flat potential is formed. As described above, since the influence of the P ⁺ channel stopper 105 and the P-type region 107 is reduced in the VOD barrier, the rate of change of the VOD barrier potential with respect to the substrate voltage is increased. To increase.

(Third Embodiment) FIG. 6 shows a cross-sectional structure of a third embodiment. The same structures as those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and detailed description will be omitted. P-type region 1 formed immediately below photoelectric conversion element 201
42 is similar to the P-type region 122 of the first embodiment, and is formed around the P-type region 102 around the periphery thereof.
The plane area projected on the plane corresponding to (a) is equal to the N-type region 103 of the photoelectric conversion element 201. In the method of manufacturing the CCD image sensor shown in FIG. 6, the size of the P-type region 142 is different from that of the P-type region 122 of the first embodiment shown in FIG. The description is omitted because it is the same as that of the first embodiment.

According to the third embodiment, when the N-type region 103 of the photoelectric conversion element 201 and the N-type region 108 of the vertical CCD 202 are depleted, the lines C1-C1 and C2-C2 in FIG. The outline of the potential distribution along the line is indicated by lines S11 and S21 and S22 in FIG. Regarding the potential distribution of the S11 line, S21, and S22 lines along the C2-C2 line, the impurity concentration of the P-type region 102 is shown as a parameter. When the impurity concentration of the P-type region 102 is lower,
The potential curve along the line C2-C2 changes in the direction of higher potential. That is, the potential of the P-type region 102 near the depth where the VOD barrier is formed along the line C1-C1 is higher in the S22 where the impurity concentration of the P-type region 102 is lower than in the S21 where the impurity concentration is higher. In this embodiment, the P-type region 102 has a lower impurity concentration than the P-type region 142,
The P ⁺ channel stopper 10 via the P-type region 102 can be used instead of making the entire P-type regions 102 and 142 have a high impurity concentration.
5 and the effect of the P-type region 107 on the VOD barrier can be reduced. Therefore, the ratio of the change in the VOD barrier potential to the substrate voltage increases, and the slope of the knee characteristic increases as the substrate pull-out voltage decreases.

(Fourth Embodiment) FIG. 8 shows a sectional structure of a fourth embodiment. The same structures as those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and detailed description will be omitted. The P-type region 152 immediately below the photoelectric conversion element 201 is the first type.
This embodiment is the same as the above-described embodiment, and is formed around the P-type region 102 around the periphery thereof. Here, the thickness of the P-type region 152 is larger than that of the P-type region 102. However, the centers of the P-type region 152 and the P-type region 102 in the thickness direction coincide. Further, the P-type region 152
Is formed at the center of the photoelectric conversion element 201, and has a plane area projected on a plane corresponding to FIG. 12A smaller than that of the N-type region 103, and the width w2 of the P-type region 152 in FIG.
Are smaller than the width W2 of the N-type region 103.

A method of manufacturing the CCD image sensor shown in FIG. 8 is as follows. First, a thermal oxide film having a thickness of 20 to 60 nm is formed on the surface of an N-type silicon substrate 101 having a phosphorus concentration of the order of 10 ¹⁴ / cm ³ . A photoresist is opened in a region corresponding to the P-type region 152 by a photolithography technique,
Boron of 0.5 to 3 MeV and 0.5 to 5 × 10 ¹¹ / cm ² is ion-implanted. However, the opening of the photoresist
It is determined in consideration of the spread of boron due to the subsequent heat treatment. After that, boron is diffused by a heat treatment at 900 to 1200 ° C. for 30 minutes to 2 hours to form a P-type region 152. Next, the P-type region 1 is formed by photolithography technology.
02 is ion-implanted with boron having the same energy as that of the P-type region 152 and a dose of 0.25 to 0.8 times, and a heat treatment at 900 to 980 ° C. for 30 minutes to 2 hours is performed. To form When forming the P-type region 102, boron ions may be implanted over the entire surface of the unit pixel. The boron ion-implanted into the P-type region 152
Since the heat treatment is performed more frequently than the mold region 102, the heat is diffused widely, and the P-type region 152 becomes thicker than the P-type region 102. P ⁺ channel stopper 105 other than the above, N-type region 103, P ⁺
The type region 104, the N type region 108, the P type region 107, the transfer gate region 106, the light shielding film 111, etc.
The description is omitted because it is the same as that of the first embodiment.

FIG. 9 shows an outline of the potential distribution along the line D1-D1 in FIG. 8 when the impurity concentration of the P-type region 152 is fixed and its thickness is used as a parameter. It is shown. However, the center of the P-type region in the thickness direction is made coincident to change the film thickness. Even if the same substrate voltage is applied to the N-type silicon substrate 101, the thinner the P-type region 152, the higher the potential of the VOD barrier. P
⁺ Assuming that there is no influence of the channel stopper 105 and the P-type region 107, D2-D passing through the P-type region 102
The VOD barrier potential Vb2 'in the cross section along the line 2 is higher than the VOD barrier potential Vb1' in the cross section along the line D1-D1 passing through the P-type region 152. As described in the conventional example, the P ⁺ channel stopper 105 is actually used.
Vb2 ′ is reduced due to the influence of the P-type region 107, but the VOD barrier potential Vb1 ′ at the center of the photoelectric conversion element 201 due to the thin impurity concentration P-type region 102 adjacent to the P-type region 152. P ⁺ channel stopper 1 to
05 or the P-type region 107 can be reduced or eliminated. However, the amount of decrease of Vb2 'is Vb1'
It must be an amount that does not affect the This is the P-type region 15
2 and the P-type region 102 can be controlled, but if the thickness difference is too small, the effect of increasing the knee characteristic is small. If the difference is too large, the VOD barrier potential along the line D2-D2 becomes D
It becomes higher than that along the 1-D1 line, and the surplus electric charge is discharged through a narrow area around the photoelectric conversion element 201 in the P-type area 102, and the effect of increasing the knee characteristic is lost.

The reason why the effect of increasing the knee characteristic is lost when the difference in the thickness of the P-type region 152 is large is as follows. The VOD barrier potential in the region where the surplus electric charge is swept is the same as the VOD barrier potential in the P-type region 152.
^{Due to} the influence of the ⁺ channel stopper 105 and the P-type region 107, a region having a flat potential is eliminated as in the conventional example. Therefore, the VOD barrier potential hardly changes with respect to the substrate voltage, and the slope of the knee characteristic decreases. results of the experiment,
The thickness of the P-type region 152 is set to be 1.times.
It has been found that the inclination of the knee characteristic can be increased by increasing the thickness by 1 to 3 times. This indicates that the influence of the P ⁺ channel stopper 105 and the P-type region 107 on the VOD barrier is reduced. Under the optimal conditions among the above conditions, the potential of the VOD barrier at the center of the photoelectric conversion element 201 has a value determined by the one-dimensional impurity concentration profile in the depth direction, and a region with a flat potential is formed. As described above, the VOD barrier can reduce the influence of the P ⁺ channel stopper 105 and the P-type region 107, so that the ratio of the change of the VOD barrier potential to the substrate voltage increases, the substrate pull-out voltage decreases, and the knee characteristic slope decreases. To increase.

In the present embodiment, the centers of the P-type region 152 and the P-type region 102 in the thickness direction are aligned. Since the VOD barrier is formed almost at the center of the thickness of the P-type region,
When the thickness is changed while keeping the center of the thickness of the mold region constant, the depths of the VOD barriers substantially match as shown in FIG. The essence of the present invention is to prevent the potential of the VOD barrier formed in the P-type region from being affected by the P ⁺ channel stopper 105 and the P-type region 107, so that their influence is formed around the VOD barrier. As a result, a high potential region is formed when it is assumed that there is no potential. Therefore, it is not necessary to match the centers of the P-type region 152 and the P-type region 102 in the thickness direction. However, the P ⁺ region 152 and the P-type region 10
It is more desirable to make the centers of the two in the thickness direction coincide because the influence of process variations such as ion implantation on the knee characteristics and variations in the thickness of the surface oxide film can be reduced.

Here, considering also the first embodiment,
The degree of the effect of the P ⁺ channel stopper 105 and the P-type region 107 on the VOD barrier is determined by the ratio between the impurity concentration and the thickness of the P-type region 152 with respect to the P-type region 102. Therefore, the P ⁺ channel stopper 105 and the P ⁺
In order to reduce the influence of the mold region 107, the P-type region 152 and the P-type region 10 in the manufacturing method of the fourth embodiment are reduced.
Dose and heat treatment temperature of boron ion implantation into
Control the time. That is, in the fourth embodiment, depending on the relationship between the dose of the impurities in the P-type region 152 and the P-type region 102 and the heat treatment temperature and time, the P-type region
2 is considered to be higher than the P-type region 102, but even if the impurity concentration of the P-type region 152 is formed to be approximately equal to or lower than that of the P-type region 102,
By forming the P-type region 152 to be thicker than the P-type region 102, it is possible to reduce the above-described substrate withdrawal voltage and increase the slope of the knee characteristic.

As described in the fourth embodiment, the thickness of the P-type region 152 forming the VOD barrier and the impurity concentration thereof both control the potential of the VOD barrier. Therefore, in the second and third embodiments, even if the thickness of the P-type regions 132 and 142 below the center of the photoelectric conversion element is increased as in the fourth embodiment, the second and third Obviously, the same effects as those of the embodiment can be obtained.

(Fifth Embodiment) FIG. 10 shows a sectional structure of a fifth embodiment. The same structures as those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals. Although P-type region 162 is equal plane area projected on a plane corresponding to the N-type region 103 and Figure 12 (a) directly under the photoelectric conversion element 201 is formed, the P ⁺ channel stopper 105 and P-type region 107 Immediately below the P-type region 10 of the first embodiment
No P-type region corresponding to No. 2 was formed. The method of manufacturing the photoelectric conversion element shown in FIG. 10 is the same as that of the first embodiment, such as forming the P-type region 162 by lithography technology and ion implantation technology.

The reason why the P-type region 102 is not formed in the present embodiment is as follows. That is, the unit pixel size has been miniaturized for the purpose of increasing the number of pixels and reducing the size, and some vertical CCDs have a width of about 1 μm. In such a case, the distance between the adjacent P-type regions 162 is about 1 μm, and the potential of the region where the P-type region 102 is not formed is affected by the potential of the P-type region 162. It can be equivalent to having a mold area. This state corresponds to the case of the low impurity concentration in FIG. 7 (see line S22), and the influence of the P ⁺ channel stopper 105 and the P-type region 107 on the VOD barrier can be reduced. Therefore, VOD with respect to the substrate voltage
The rate of change in the barrier potential increases, and the slope of the knee characteristic increases as the substrate pull-out voltage decreases.

In the fifth embodiment, the P-type region 16
2 is formed so that the plane area projected on the plane corresponding to FIG. 12A is equal to that of the N-type region 103. However, as in the first embodiment shown in FIG. May be smaller than the N-type region 103. That is, as described above, the region where the P-type region between the P-type regions 162 is not formed functions as a low-impurity-concentration P-type region.
As described in the first embodiment, when it is assumed that there is no influence of the P ⁺ channel stopper 105 and the P-type region 107, the VOD barrier potential of the region where the P-type region 162 is not formed becomes the P-type region 162 The potential becomes higher than the VOD barrier potential formed therein, and the VOD barrier at the center of the photoelectric conversion element can reduce the influence of the P ⁺ channel stopper 105 and the P-type region 107. Therefore, the ratio of the change in the VOD barrier potential to the substrate voltage increases, and the slope of the knee characteristic increases as the substrate pull-out voltage decreases.

The above description is based on X1-X1 in FIG.
Although a cross section is used, the same applies to a direction orthogonal to the cross section. The reason is the same as the reason why the present invention described below can be applied to a MOS image sensor. Further, the above description shows a case where the present invention is applied to a CCD image sensor in which a photoelectric conversion element and a vertical CCD are formed.
Instead, the present invention can be similarly applied to a MOS image sensor in which readout wiring is formed or a single photoelectric conversion element. Because, even in such a device, in order to sufficiently perform element isolation, the potential around the photoelectric conversion element is made lower than at least the VOD barrier potential by a P ⁺ channel stopper or the like. Therefore, when the photoelectric conversion element is miniaturized, V
The present invention, which has an essential purpose of reducing the influence of the OD barrier from such a low potential region, can be applied.

Although the above description has been given of the case where the present invention is applied to a buried photoelectric conversion element, the present invention can be similarly applied to a photoelectric conversion element in which the P ⁺ region 104 is not formed on the N-type region 103. Although the case where the signal charge is an electron has been described, the same description can be applied to a case where the signal charge is a hole by exchanging the N-type and P-type impurities and reversing the direction of the voltage.

[0042]

As described above, in the first photoelectric conversion element of the present invention, the first barrier region is formed to have a higher impurity concentration and / or a larger thickness than the second barrier region. Alternatively, in the second photoelectric conversion element of the present invention, by forming the first barrier region only directly below the photoelectric conversion element, the influence of the element isolation region and the like on the VOD barrier can be reduced. A flat region of the potential of the VOD barrier is formed. As a result, the ratio of the change in the VOD barrier potential to the substrate voltage is increased, and a photoelectric conversion element in which the substrate withdrawal voltage is reduced and the slope of the knee characteristic is increased can be obtained. Therefore, a solid-state imaging device using the photoelectric conversion device of the present invention, for example, CC
When the D image sensor is configured, it is possible to reduce the power consumption of the CCD image sensor, expand the dynamic range of the light amount, and reduce the gradation.

[Brief description of the drawings]

FIG. 1 shows a first application of the present invention to a CCD image sensor.
FIG. 4 is a schematic sectional view of a unit pixel according to the embodiment.

FIG. 2 is a schematic potential distribution diagram of the cross section shown in FIG.

FIG. 3 is a diagram showing an outline of a potential distribution along a line A3-A3 in FIG. 2 in comparison with a conventional example.

FIG. 4 schematically shows a potential distribution along a line A4-A4 in FIG. 2 using the impurity concentration of a P-type region 122 as a parameter.

FIG. 5 is a schematic sectional view of a unit pixel according to a second embodiment of the present invention.

FIG. 6 is a schematic sectional view of a unit pixel according to a third embodiment of the present invention.

FIG. 7 is a schematic diagram of a potential distribution along lines C1-C1 and C2-C2 in FIG.

FIG. 8 is a schematic sectional view of a unit pixel according to a fourth embodiment of the present invention.

9 schematically shows the potential distribution along the line D1-D1 in FIG. 8 when the impurity concentration of the P-type region 152 is fixed and the thickness is used as a parameter.

FIG. 10 is a schematic sectional view of a unit pixel according to a fifth embodiment of the present invention.

FIG. 11 is a schematic plan view of a conventional CCD image sensor.

12A is a schematic plan view of a unit pixel of a conventional CCD image sensor, and FIG. 12B is a schematic view of a cross section taken along line X1-X1.

FIG. 13 is a schematic potential distribution diagram of the cross section shown in FIG.

14 is a schematic diagram of a potential distribution along lines X2-X2 and X3-X3 in FIG.

FIG. 15 is a schematic diagram of a potential distribution along the line X4-X4 in FIG.

FIG. 16 is a diagram showing the relationship between the amount of signal charge and the amount of signal charge in a photoelectric conversion element having a vertical overflow drain structure on a log-log scale.

[Explanation of symbols]

101, 301 N-type silicon substrate 102, 302 P-type region 103, 303 N-type region 104, 304 P ⁺ region 105, 305 P ⁺ channel stopper 106, 306 Transfer gate region 107, 307 P-type region 108, 308 N-type region 109, 309 Gate insulating film 110, 310 Gate electrode 111, 311 Light shielding film 112, 312 Interlayer insulating film 122, 132, 142, 152, 162 P-type region (immediately below N-type region) 201 Photoelectric conversion element 202 Vertical CCD 203 Transfer Gate 204 Horizontal CCD 205 Amplifier 206 P ⁺ Channel stopper

Claims (8)

[Claims] 1. A vertical overflow drain type photoelectric conversion element for sweeping surplus charge generated by a photoelectric conversion element to a semiconductor substrate, wherein a first barrier region of a second conductivity type is formed in a first conductivity type semiconductor substrate. A second barrier region of a second conductivity type is provided, and the photoelectric conversion element and at least an element isolation region are formed on the first barrier region and the second barrier region; A region is formed below the photoelectric conversion element, the second barrier region is formed other than the first barrier region, and the first barrier region has a higher impurity concentration than the second barrier region; And / or the first barrier region is thicker than the second barrier region. 2. The photoelectric conversion element according to claim 1, wherein the first barrier region and the second barrier region are formed continuously in a plane. 3. The photoelectric conversion device according to claim 1, wherein the first barrier region and the second barrier region are formed apart from each other. 4. The photoelectric conversion element according to claim 1, wherein the first barrier region has an impurity concentration that is 1.1 to 3 times higher than that of the second barrier region. 5. The photoelectric conversion device according to claim 1, wherein the first barrier region is 1.1 to 3 times thicker than the second barrier region. 6. A vertical overflow drain type photoelectric conversion element for sweeping surplus electric charges generated in a photoelectric conversion element to a semiconductor substrate, wherein the photoelectric conversion element and at least an element isolation region are formed in a first conductivity type semiconductor substrate. And a first barrier region of a second conductivity type is formed under the photoelectric conversion element. 7. The photoelectric conversion element includes a charge accumulation region of a first conductivity type for accumulating photoelectrically converted charges, wherein the first barrier region has a plane area equal to the charge accumulation region, or 7. The photoelectric conversion element according to claim 1, wherein the photoelectric conversion element has a smaller plane area than the storage area. 8. The photoelectric conversion element includes a charge accumulation region of a first conductivity type that accumulates photoelectrically converted charges, and the charge conversion region is formed by the influence of a potential from the element isolation region and the first barrier region. 8. The photoelectric conversion device according to claim 6, wherein a region in which the first barrier region is not formed has a larger electric barrier to the charge accumulation region than the first barrier region, and the surplus charge flows only to the semiconductor substrate. Conversion element.