JPS60258919A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60258919A JPS60258919A JP59114561A JP11456184A JPS60258919A JP S60258919 A JPS60258919 A JP S60258919A JP 59114561 A JP59114561 A JP 59114561A JP 11456184 A JP11456184 A JP 11456184A JP S60258919 A JPS60258919 A JP S60258919A
- Authority
- JP
- Japan
- Prior art keywords
- polysilicon
- oxide film
- boron
- base electrode
- polysilicon layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体装置の製造方法に係り、特にベース電極
をポリシリコンにより素子分離領域の酸化膜上に引きだ
した構造のバイポーラトランジスタの平坦化に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to planarization of a bipolar transistor having a structure in which a base electrode is extended by polysilicon onto an oxide film in an element isolation region.
従来バイポーラトランジスタのベース配線はベース拡散
層上に形成されていたが、最近素子寸法を小さくして高
速化するためにベース電極をポリシリコンにより素子分
離用の厚い酸化膜上に引き(1)
だした後、アルミなどにより配線を行なう方法が提案さ
れている。Traditionally, the base wiring of bipolar transistors was formed on the base diffusion layer, but recently, in order to reduce the device size and increase speed, the base electrode has been placed on a thick oxide film for device isolation using polysilicon (1). A method has been proposed in which wiring is then done using aluminum or the like.
この方法は第1図に示すように半導体基板lに厚い酸化
膜2を形成し、ポリシリコンを全面に被着後ホトエツチ
ング技術により、ベースポリシリコン電極4を形成し、
その一部を酸化して酸化膜5を形成する。このポリシリ
コンにはベース領域と同じ不純物が添加されており、酸
化等の熱処理゛により、基板シリコンとポリシリコンが
接触している領域には拡散層3が形成される。As shown in FIG. 1, this method involves forming a thick oxide film 2 on a semiconductor substrate l, depositing polysilicon on the entire surface, and then forming a base polysilicon electrode 4 by photo-etching.
A part of it is oxidized to form an oxide film 5. This polysilicon is doped with the same impurities as the base region, and by heat treatment such as oxidation, a diffusion layer 3 is formed in the region where the substrate silicon and polysilicon are in contact.
これらの方法では厚い酸化膜上でポリシリコンの端部に
形成される段差が大きくなり、この上に微細な配線パタ
ーンを形成することは配線が断線するために困難であっ
た。In these methods, the step formed at the end of the polysilicon on the thick oxide film becomes large, and it is difficult to form a fine wiring pattern thereon because the wiring breaks.
本発明の目的は上記従来の問題を解決し微細配線が可能
なように半導体装置表面を平坦化することのできる半導
体装置の製造方法を提供することである。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can solve the above-mentioned conventional problems and flatten the surface of the semiconductor device to enable fine wiring.
(2)
上記のようにポリシリコンを用いたベース電極の引出し
はトランジスタの活性領域を小型化し、高速化に効果的
であるが、単にポリシリコンをエツチングし、酸化した
場合には周辺部に大きな段差が発生し、その上に配線を
行なうと断線が発生する可能性がある。(2) As mentioned above, drawing out the base electrode using polysilicon is effective in reducing the size of the active region of the transistor and increasing its speed, but if the polysilicon is simply etched and oxidized, the peripheral area will become larger. If a level difference occurs and wiring is performed on top of it, there is a possibility that a disconnection will occur.
本発明はベース電極周辺にポリシリコンを薄く残してお
き、ベース電極表面を酸化して酸化膜を形成する工程に
おいて上記残されたシリコンを同時に酸化し、段差の発
生を少なくすると同時に段差部における形状をなだらか
にするものである。In the present invention, a thin layer of polysilicon is left around the base electrode, and in the step of oxidizing the base electrode surface to form an oxide film, the remaining silicon is simultaneously oxidized, thereby reducing the occurrence of steps and at the same time shaping the shape of the steps. It is something that makes it gentle.
以下1本発明の一実施例を第2図〜第4図により説明す
る。An embodiment of the present invention will be described below with reference to FIGS. 2 to 4.
第2図に示すようにシリコン基板1を選択酸化して厚い
素子分離用の酸化膜2を形成したシリコン基板に第1の
ポリシリコン層6を形成し、ボロ+j :y&ml″t
6・′“J′“7°yM#(QJI;Ht200nmで
ボロンの拡散は950℃で20分間行ないボロンを高濃
度に拡散した。次に第2のポリシリ(3)
コン層7を被着する。膜厚は500nmである。As shown in FIG. 2, a first polysilicon layer 6 is formed on a silicon substrate 1 on which a thick oxide film 2 for element isolation has been formed by selectively oxidizing the silicon substrate 1.
6・'"J'"7°yM# (QJI; Ht200nm, boron diffusion was carried out at 950°C for 20 minutes to achieve a high concentration of boron. Next, the second polysilicon (3) layer 7 was deposited. The film thickness is 500 nm.
次に適当なマスクを用いて第2ポリシリコンをエツチン
グする。マスクとしては5inQ膜を20nm被着して
使用した。The second polysilicon is then etched using a suitable mask. A 20 nm thick 5inQ film was used as a mask.
ポリシリコンのエツチングは普通の弗化水素酸と硝酸系
の液やCF4系のガスを用いたプラズマエッチ等ではす
べてのポリシリコンがエツチングされるために第2ポリ
シリコンだけを除去することは困難である。このために
P型不純物濃度によってエッチ速度に差があるアルカリ
系のエッチ液を採用した。この液では固溶限界までボロ
ンを添加したシリコンはほとんど溶解しないため第2ポ
リシリコン7のみを除去することが可能である。When etching polysilicon, it is difficult to remove only the second polysilicon because all the polysilicon is etched using ordinary hydrofluoric acid and nitric acid solutions or plasma etching using CF4 gas. be. For this purpose, an alkaline etchant whose etch rate varies depending on the P-type impurity concentration was used. In this liquid, silicon to which boron has been added up to the solid solution limit hardly dissolves, so that only the second polysilicon 7 can be removed.
本実施例においてはエッチ液は水酸化カリウムの40%
水溶液を用い、25℃でエツチングを行なった。ポリシ
リコンのエッチ速度は不純物を添加していない場合が2
5 n m/winで、ボロンを高濃度に添加した場合
が1〜2nm/耐nである。In this example, the etchant was 40% potassium hydroxide.
Etching was performed at 25°C using an aqueous solution. The etch rate of polysilicon is 2 when no impurities are added.
5 nm/win, and when boron is added at a high concentration, the resistance is 1 to 2 nm/n.
したがって、エッチ速度比は10:1以上になり、不純
物の濃度差によって選択エッチが可能である。Therefore, the etch rate ratio is 10:1 or more, and selective etching is possible due to the difference in impurity concentration.
(4)
第3図は5inQをマスクに第2ポリシリコン7の所望
部分を選択エッチし、マスクに使用したStO,膜を形
除去した状態を示す。次にポリシリコンを酸化する。酸
化膜厚はベース電極部以外の部分に露出している第1ポ
リシリコンロが完全に酸化膜になる厚さで、200nm
のポリシリコンに対しては450nmの酸化膜を形成し
た。この酸化によりベース電極部にも酸化膜5が形成さ
れ第4図に示す構造が完成する。なお、酸化は比較的低
温で厚い酸化膜が形成できる高圧酸化がボロンの拡散を
浅くおさえるために効果がある。また、ボロンを高濃度
に添加したポリシリコンは酸化速度が速く、ベース電極
部より厚い酸化膜が形成でき、平坦化上効果が大きい。(4) FIG. 3 shows a state in which a desired portion of the second polysilicon 7 is selectively etched using a 5inQ mask, and the StO film used as the mask is removed. Next, the polysilicon is oxidized. The oxide film thickness is 200 nm, which is the thickness at which the first polysilicon layer exposed in areas other than the base electrode part is completely oxidized.
A 450 nm thick oxide film was formed on the polysilicon. As a result of this oxidation, an oxide film 5 is also formed on the base electrode portion, completing the structure shown in FIG. Note that high-pressure oxidation, which can form a thick oxide film at a relatively low temperature, is effective because it suppresses the diffusion of boron to a shallow level. Further, polysilicon doped with boron at a high concentration has a fast oxidation rate, and can form an oxide film thicker than the base electrode portion, which is highly effective in terms of planarization.
本発明によればポリシリコンによるベース電極周辺の段
差を約1/2以下に減少することができ、微細なアルミ
配線を行なう上でその効果は非常に大きい。According to the present invention, the level difference around the base electrode made of polysilicon can be reduced to about 1/2 or less, which is very effective in forming fine aluminum wiring.
本発明はボロン添加ポリシリコンと濃度差によ(5)
る選択エツチングを組合わせ、均一な厚さにポリシリコ
ンを残せる方法を開発することによって、段差部におけ
る形状の良好な平坦化を可能としたものでその効果は大
きい。The present invention combines boron-doped polysilicon with selective etching based on the concentration difference (5) and develops a method that leaves polysilicon with a uniform thickness, thereby making it possible to achieve good flattening of the shape at stepped portions. The effect is great.
第1図は従来の構造を示す断面図、第2図〜第4図は本
発明を説明するための工程図である。
1・・・シリコン基板、2・・・素子分離などの厚い酸
化膜、3・・・ベースコンタクト用拡散層、4,6.7
・・・ポリシリコン層、5・・・ポリシリコンを酸化し
た(6)FIG. 1 is a sectional view showing a conventional structure, and FIGS. 2 to 4 are process diagrams for explaining the present invention. 1... Silicon substrate, 2... Thick oxide film for element isolation, etc., 3... Diffusion layer for base contact, 4,6.7
... Polysilicon layer, 5... Oxidized polysilicon (6)
Claims (1)
形成した後、その表面に実質的に不純物を含まない第2
のポリシリコン層を重ねて形成し、上記第2のポリシリ
コン層を選択除去し、さらに上記ポリシリコン層を酸化
して酸化膜を形成することを特徴とする半導体装置の製
造方法。After forming a first polysilicon layer doped with boron on a semiconductor substrate, a second polysilicon layer substantially free of impurities is formed on the surface of the first polysilicon layer doped with boron.
1. A method of manufacturing a semiconductor device, comprising: forming polysilicon layers one on top of the other, selectively removing the second polysilicon layer, and further oxidizing the polysilicon layer to form an oxide film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59114561A JPS60258919A (en) | 1984-06-06 | 1984-06-06 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59114561A JPS60258919A (en) | 1984-06-06 | 1984-06-06 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60258919A true JPS60258919A (en) | 1985-12-20 |
Family
ID=14640889
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59114561A Pending JPS60258919A (en) | 1984-06-06 | 1984-06-06 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60258919A (en) |
-
1984
- 1984-06-06 JP JP59114561A patent/JPS60258919A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS5946107B2 (en) | Manufacturing method of MIS type semiconductor device | |
JPH01165172A (en) | Manufacture of thin film transistor | |
JPS5912021B2 (en) | Manufacturing method of semiconductor device | |
JPS60258919A (en) | Manufacture of semiconductor device | |
JPS63289820A (en) | Manufacture of semiconductor device | |
JPS6262457B2 (en) | ||
JPS60258964A (en) | Manufacture of semiconductor device | |
JPS6123363A (en) | Semiconductor device and manufacture of the same | |
JPS6220711B2 (en) | ||
JPS6134255B2 (en) | ||
JPH0335528A (en) | Manufacture of semiconductor device | |
JPH0230124A (en) | Manufacture of semiconductor device | |
JPS62206873A (en) | Manufacture of semiconductor device | |
JPH0542817B2 (en) | ||
JPH0448624A (en) | Manufacture of semiconductor device | |
JPH07183530A (en) | Manufacture of thin film transistor | |
JPH0297057A (en) | Manufacture of semiconductor device | |
JPH01232737A (en) | Manufacture of semiconductor element | |
JPS61147550A (en) | Manufacture of semiconductor device | |
JPH01251658A (en) | Manufacture of semiconductor device | |
JPH0629521A (en) | Manufacture of mos field-effect transistor | |
JPS62235783A (en) | Manufacture of field-effect transistor | |
JPS58158968A (en) | Manufacture of semiconductor device | |
JPS61129869A (en) | Manufacture of semiconductor device | |
JPS60258965A (en) | Manufacture of semiconductor device |