JPS60257174A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60257174A
JPS60257174A JP59112634A JP11263484A JPS60257174A JP S60257174 A JPS60257174 A JP S60257174A JP 59112634 A JP59112634 A JP 59112634A JP 11263484 A JP11263484 A JP 11263484A JP S60257174 A JPS60257174 A JP S60257174A
Authority
JP
Japan
Prior art keywords
gate
source
oxide film
protection diode
inductors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59112634A
Other languages
Japanese (ja)
Inventor
Yoshito Ogawa
義人 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59112634A priority Critical patent/JPS60257174A/en
Publication of JPS60257174A publication Critical patent/JPS60257174A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08Modifications for protecting switching circuit against overcurrent or overvoltage

Landscapes

  • Amplifiers (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Protection Of Static Devices (AREA)

Abstract

PURPOSE:To improve device capabilities to withstand external surges by a method wherein elements equipped with inductance is inserted between IGFET gate electrodes and a gate-protecting diode. CONSTITUTION:Diodes 25, 26, connected in contactenation reverse to each other, are provided between the gate 22 and source 21 and between the gate 23 and source 21, respectively, of an FET20, provided with a source terminal 21, gate terminals 22, 23, drain terminal 24. Further, between a protecting diode and gate electrodes located on a gate oxide film, inductors 27, 28 are connected, respectively. The inductors 27, 28 should use Al lines and have an inductance of approximately 3mH. In a device structured as such, external surges are stopped before entering the gate oxide film, which augments the device in terms of its capabilities to withstand breakdown voltages.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は半導体装置に関し、特にMO8構造を有する絶
縁ゲート型電界効果トランジスタを含む半導体装置に関
する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and particularly to a semiconductor device including an insulated gate field effect transistor having an MO8 structure.

近年、高周波用の電界効果トランジスタはその高周波特
性、例えば電力利得、雑音指数等を向上させる為ますま
すパターンの微細化が進んでいる、特にUH1i’帯で
優れた高周波特性を示すMO8Wt造を有する双ゲート
型電界効果トランジスタ(以下、MO8双ゲートFET
と記す)はテレビジョンやビデオテープレコーダ等のチ
ューナ部分に。
In recent years, high-frequency field-effect transistors have increasingly finer patterns in order to improve their high-frequency characteristics, such as power gain and noise figure.The MO8Wt structure exhibits excellent high-frequency characteristics, especially in the UH1i' band. Twin-gate field effect transistor (hereinafter referred to as MO8 twin-gate FET)
) is used in the tuner part of televisions, video tape recorders, etc.

又、ケーブルテレビシロンのコンバータ等に多用されて
いる。そして、このMO8双ゲートFETの電力利得、
雑音指数等の高周波特性をさらに向上させるに当り、ま
すますゲート長を短かくし、ゲート酸化膜厚を薄くして
いる。
It is also widely used in cable TV Chiron converters, etc. And the power gain of this MO8 twin gate FET,
In order to further improve high-frequency characteristics such as noise figure, the gate length is increasingly shortened and the gate oxide film thickness is made thinner.

一般にMOS FFtTのゲート静電破壊強度は、その
ゲート酸化膜がシリコンの熱酸化膜の場合、膜厚10n
m当りIOVと言われている。このような高周波用MO
8双ゲートF’F’rのゲート酸化膜は通常数十nmを
採用しており、例えばゲート酸化膜厚が60nmの場合
第1図の如く約60Vの静電破壊強度しか得られない。
Generally, the gate electrostatic breakdown strength of MOS FFtT is determined by the gate oxide film having a film thickness of 10 nm when the gate oxide film is a silicon thermal oxide film.
It is said to be IOV per m. This kind of high frequency MO
The gate oxide film of the 8-twin gate F'F'r is usually several tens of nanometers thick, and for example, when the gate oxide film thickness is 60 nm, an electrostatic breakdown strength of only about 60 V can be obtained as shown in FIG.

従って従来よりとの様なMO8双ゲートF’F’[’に
対してはゲート保護用のダイオードを設けてゲート酸化
膜を保護していた。
Therefore, for the conventional MO8 double gate F'F'[', a gate protection diode was provided to protect the gate oxide film.

第2図は従来の保護用ダイオード付きMO8O8−)F
gTの一例の等価回路図である。第2図において1はソ
ース、2は第1ゲート、3は第2ゲート、4はドレイン
の各端子で5及び6は保護ダイオードでゲート・ソース
間に接続されている。
Figure 2 shows a conventional MO8O8-)F with a protection diode.
It is an equivalent circuit diagram of an example of gT. In FIG. 2, 1 is a source, 2 is a first gate, 3 is a second gate, 4 is a drain, and 5 and 6 are protection diodes connected between the gate and the source.

保護ダイオード5,6は互いに逆方向特性となる様に縦
続接続した2個のダイオードの組から成り、第1ゲート
・ソース間及び第2ゲート・ソース間にそれぞれ接続し
である。
The protection diodes 5 and 6 consist of a set of two diodes connected in cascade so as to have opposite characteristics, and are connected between the first gate and the source and between the second gate and the source, respectively.

第3図は第2図に示す保護ダイオード付きMO8双ゲー
)FF3Tのゲート番ソース間の電流−電圧特性図であ
る。第3図に示す様に、各バイアス方向とも逆方向特性
を示す。
FIG. 3 is a current-voltage characteristic diagram between the gate and source of the MO8 dual-gate FF3T with a protection diode shown in FIG. As shown in FIG. 3, each bias direction exhibits reverse direction characteristics.

第4図はこの従来のMO8双ゲート];”E’rの破壊
に至る電圧の実測値である。ここでは第1ゲート・ソー
ス間のみのデータであるが、第2ゲート・ソース間もほ
ぼ同様の値を示す。
Figure 4 shows the actual measured value of the voltage that leads to the breakdown of this conventional MO8 double gate];" Shows similar values.

以上の様にゲート参ンース間に保護ダイオードを接続す
ると第1ゲート・ソース間もしくは第2ゲート・ソース
間に入るサージ電力に対しては静電破壊強度はゲート酸
化膜厚5+1nmでも1oo〜120■に向上する。こ
こで接続した保護ダイオードは1個当り逆方向耐圧15
V、印加電圧o■の時の容量0.5PFのものを用いて
いる。
As mentioned above, when a protection diode is connected between the gate and the source, the electrostatic breakdown strength against the surge power that enters between the first gate and source or between the second gate and source is 1oo~120cm even with a gate oxide film thickness of 5+1 nm. improve. Each protective diode connected here has a reverse breakdown voltage of 15
A capacitance of 0.5 PF is used when the applied voltage is 0.

ところで第5図のMO8FF!Tのゲートサージ破壊強
度試験装置によシ、容量値11を変化してゲート破壊強
度を測定すると、第6図の様になり線で示す)よシ傾き
が小さい。このことは、従来例の保護ダイオードのみで
はダイオードで十分で外来サージエネルギーを吸収でき
ず一部がゲート酸化膜の方へ流れていることを示す。ち
なみに保護ダイオードのみの破壊強奪は第7図に示す如
く容量に対し1/2乗の傾きをもっている。
By the way, MO8FF in Figure 5! When the gate breakdown strength is measured by changing the capacitance value 11 using a gate surge breakdown strength testing device of T, the result is as shown in FIG. 6 (shown by the line), and the slope is smaller. This indicates that the conventional protection diode alone is sufficient to absorb external surge energy, and a portion of it flows toward the gate oxide film. Incidentally, the destruction of only the protection diode has a slope of 1/2 power with respect to the capacitance, as shown in FIG.

(発明が解決しようとする問題点) 本発明の目的は外来サージ電力が保護ダイオードで十分
吸収されず一部がゲート酸化膜の方へ流れるという従来
の欠点を除去し、ゲート酸化膜が破壊することのない様
に改善した絶縁ゲート型電界効果トランジスタを含む半
導体装置を提供することにある。
(Problems to be Solved by the Invention) The purpose of the present invention is to eliminate the conventional drawback that external surge power is not sufficiently absorbed by the protection diode and a portion flows toward the gate oxide film, thereby destroying the gate oxide film. It is an object of the present invention to provide a semiconductor device including an insulated gate field effect transistor which is improved so as not to cause problems.

(問題点を解決するだめの手段) 本発明によれば、ゲート保護ダイオードと絶縁ゲート型
電界効果トランジスタのゲート電極間にインダクタンス
成分をもつ回路素子を挿入した半導体装置を得る。
(Means for Solving the Problems) According to the present invention, a semiconductor device is obtained in which a circuit element having an inductance component is inserted between a gate protection diode and a gate electrode of an insulated gate field effect transistor.

(実施例) 次に、本発明の詳細について図面を用いて説明する。(Example) Next, details of the present invention will be explained using the drawings.

第8図は本発明の一実施例の等価回路図である。FIG. 8 is an equivalent circuit diagram of an embodiment of the present invention.

ソース端子21.第1ゲート端子22.第2ゲート端子
23.ドレイン端子14を有するNチャンネル型のMO
8双ゲートF’E’r20の第1ゲート・ソース間及び
第2ゲート・ソース間にそれぞれ互いに逆方向特性とな
る様に縦続接続した2個のダイオードの組25.26を
接続し更に保護ダイオードとゲート酸化模上のゲート電
極間にインダクター27.28をそれぞれ接続する。
Source terminal 21. First gate terminal 22. Second gate terminal 23. N-channel MO with drain terminal 14
Two sets of cascaded diodes 25 and 26 are connected between the first gate and source and the second gate and source of the 8-twin gate F'E'r 20 so as to have opposite direction characteristics, and a protection diode is further connected. Inductors 27 and 28 are connected between the gate electrode and the gate electrode on the gate oxide pattern, respectively.

具体的数値例を挙げるとインダクター27.28はAl
配線を用い、そのインダクタンスは約3nHで5− ある。このインダクター27.28により外来サージエ
ネルギーはMOSのゲート酸化膜に流れ込むことなく、
阻止される。
To give a specific numerical example, inductors 27 and 28 are made of Al
A wire is used, and its inductance is approximately 3 nH. These inductors 27 and 28 prevent external surge energy from flowing into the gate oxide film of the MOS.
blocked.

第9図は本実施例によるMO8双ゲートpti:’rの
破壊に至る電圧の実測値で容量値を変化させた場合を示
している。第6図の従来例と比較し100PFの時約1
00■向上している。
FIG. 9 shows the case where the capacitance value is changed according to the actually measured value of the voltage that causes the destruction of the MO8 twin gate pti:'r according to this embodiment. Approximately 1 at 100PF compared to the conventional example shown in Figure 6
00 ■Improved.

本発明ではNチャンネル型について説明したがPチャン
ネル型でも可能である。又、シリコンのみならずG a
 A s等の化合物半導体材料でも良い。
In the present invention, an N-channel type has been described, but a P-channel type is also possible. In addition to silicon, Ga
A compound semiconductor material such as As may also be used.

第8図の等価回路上インダクターの記号をコイルで表わ
したが実際は分布定数回路であることはいうまでもない
Although the inductor symbol in the equivalent circuit of FIG. 8 is represented by a coil, it goes without saying that it is actually a distributed constant circuit.

(発明の効果) 以上、説明した様に本発明によればMO8双ゲ−)F’
B’rの破壊強度を大きく向上させることが可能となる
(Effect of the invention) As explained above, according to the present invention, MO8 double game) F'
It becomes possible to greatly improve the fracture strength of B'r.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はMOSの破壊電圧を示すグラフ、第26− 図は従来の保護ダイオード付MO8双ゲー) F’Fi
Tの一例の等価回路図、第3図は上記のダイオード耐圧
を示すグラフ、第4図は上記の破壊に至る電圧を示すグ
ラフ、第5図は破壊強度を測定する試験装置の回路図、
第6図は上記試験装置による破壊強度の容量特性を示す
グラフ、第7図はダイオードのみによる破壊強度の容量
特性を示すグラフである。 第8図は本発明の一実施例の等価回路図、第9図は本実
施例の破壊強度の容量特性を示すグラフである。 1・・・・・・ソース端子、2・・・・・・第1ゲート
端子、3・・・・・・第2ゲート端子、4・・・・・・
ドレイン、5・・・・・・保護ダイオード、6・・・・
・・保護ダイオード、27,28・・・・・・インダク
ター。 石皮璋1:至る電圧(V) 第1 図 第3図 100 10SII0 115 720石皮璋1=り−
るt灰 (V) 第4図 1 第5図 100 300 7000 容量(PF) 第6図 +00 300 7000 客量(PF) 夢7図 700 300 1000 番量(P「) 第9図 第8図
Fig. 1 is a graph showing the breakdown voltage of MOS, Fig. 26 is a graph showing the conventional MO8 double gate with protection diode) F'Fi
An equivalent circuit diagram of an example of T, FIG. 3 is a graph showing the above-mentioned diode withstand voltage, FIG. 4 is a graph showing the voltage leading to the above-mentioned breakdown, and FIG. 5 is a circuit diagram of a test device for measuring breakdown strength.
FIG. 6 is a graph showing the capacitance characteristics of the breaking strength using the above-mentioned test apparatus, and FIG. 7 is a graph showing the capacitance characteristics of the breaking strength using only diodes. FIG. 8 is an equivalent circuit diagram of one embodiment of the present invention, and FIG. 9 is a graph showing the capacitance characteristics of the breaking strength of this embodiment. 1... Source terminal, 2... First gate terminal, 3... Second gate terminal, 4......
Drain, 5...Protection diode, 6...
...protection diode, 27,28...inductor. Shipi 1: Voltage (V) 1 Figure 3 100 10SII0 115 720 Shipi 1 = Ri-
(V) Figure 4 1 Figure 5 100 300 7000 Capacity (PF) Figure 6 +00 300 7000 Customer volume (PF) Dream 7 Figure 700 300 1000 Volume (P") Figure 9 Figure 8

Claims (1)

【特許請求の範囲】[Claims] 絶縁ゲート型電界効果トランジスタの絶縁ゲートの外来
サージによるゲート破壊を防止する為のゲート保護ダイ
オードを含む半導体装置において、ンス成分をもつ回路
素子を挿入したことを特徴とする半導体装置。
1. A semiconductor device including a gate protection diode for preventing gate destruction due to an external surge of an insulated gate of an insulated gate field effect transistor, characterized in that a circuit element having an ance component is inserted therein.
JP59112634A 1984-06-01 1984-06-01 Semiconductor device Pending JPS60257174A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59112634A JPS60257174A (en) 1984-06-01 1984-06-01 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59112634A JPS60257174A (en) 1984-06-01 1984-06-01 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60257174A true JPS60257174A (en) 1985-12-18

Family

ID=14591632

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59112634A Pending JPS60257174A (en) 1984-06-01 1984-06-01 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60257174A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5348487A (en) * 1976-10-14 1978-05-01 Fujitsu Ltd Semiconductor device
JPS56114373A (en) * 1980-02-14 1981-09-08 Matsushita Electric Ind Co Ltd Protection circuit of fet

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5348487A (en) * 1976-10-14 1978-05-01 Fujitsu Ltd Semiconductor device
JPS56114373A (en) * 1980-02-14 1981-09-08 Matsushita Electric Ind Co Ltd Protection circuit of fet

Similar Documents

Publication Publication Date Title
US4777518A (en) Semiconductor device including gate protection circuit with capacitor under input pad
USRE38319E1 (en) Dual-node capacitor coupled MOSFET for improving ESD performance
US5508548A (en) General protection of an integrated circuit against permanent overloads and electrostatic discharges
US20030117206A1 (en) High-frequency semiconductor device
US6351364B1 (en) Electrostatic discharge protection circuit
US5227327A (en) Method for making high impedance pull-up and pull-down input protection resistors for active integrated circuits
US6236073B1 (en) Electrostatic discharge device
US6091592A (en) Protective circuit and electric circuit using the protective circuit
JPH0653497A (en) Semiconductor device equipped with i/o protective circuit
JPS60257174A (en) Semiconductor device
US7054122B2 (en) VDDCORE to VSS ESD clamp made of core device
JP3025373B2 (en) Semiconductor integrated circuit
JP2970826B2 (en) Protection circuit built-in IC and display device driving IC
JPS58162065A (en) Gate prpotecting circuit
JPS6269660A (en) Electrostatic protective circuit
JPS622704B2 (en)
JPH0550146B2 (en)
US6420762B1 (en) Integrated electrostatic protective resistor for metal oxide semiconductor field effect transistors (MOSFETs)
JPS62109354A (en) Semiconductor integrated circuit
JP3178855B2 (en) Semiconductor element
JPS6151877A (en) Semiconductor device
JPS62279675A (en) Protective circuit for semiconductor integrated circuit
DE69432662T2 (en) Protection device for a series-connected MOSFET
JPH0370378B2 (en)
JPH0334712A (en) Shielded transistor device