JPH0550146B2 - - Google Patents
Info
- Publication number
- JPH0550146B2 JPH0550146B2 JP57232396A JP23239682A JPH0550146B2 JP H0550146 B2 JPH0550146 B2 JP H0550146B2 JP 57232396 A JP57232396 A JP 57232396A JP 23239682 A JP23239682 A JP 23239682A JP H0550146 B2 JPH0550146 B2 JP H0550146B2
- Authority
- JP
- Japan
- Prior art keywords
- gate
- drain
- source
- voltage
- double
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005669 field effect Effects 0.000 claims description 12
- 230000015556 catabolic process Effects 0.000 description 20
- 238000010586 diagram Methods 0.000 description 12
- 239000004065 semiconductor Substances 0.000 description 9
- 238000012360 testing method Methods 0.000 description 5
- 239000008186 active pharmaceutical agent Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置に関し、特にMOS構造を
有しノーマリー・オフ型の回路動作をする双ゲー
ト型電界効果トランジスタを含む半導体装置に関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a double-gate field effect transistor having a MOS structure and operating as a normally-off circuit.
近年、高周波用の電界効果トランジスタは、そ
の高周波特性、例えば電力利得、雑音指数等を向
上させる為、ますますパターンの微細化が進んで
いる。特に、UHF帯で優れた高周波特性を示す
MOS構造を有する双ゲート型電界効果トランジ
スタ（以下MOS双ゲートFETと記す）はテレビ
ジヨンやビデオテープレコーダ等のチユーナ部分
及びケーブルテレビジヨンのコンバータ等に多用
されている。そして、このMOS双ゲートFETの
電力利得、雑音指数等の高周波特性をさらに向上
させるに当りますますゲート長を短かくし、ゲー
ト酸化膜厚を薄くしている。 In recent years, the patterns of high-frequency field-effect transistors have become increasingly finer in order to improve their high-frequency characteristics, such as power gain and noise figure. In particular, it shows excellent high frequency characteristics in the UHF band.
BACKGROUND ART Double-gate field effect transistors (hereinafter referred to as MOS double-gate FETs) having a MOS structure are widely used in tuner parts of televisions, video tape recorders, etc., and converters of cable televisions. In order to further improve the power gain, noise figure, and other high-frequency characteristics of this MOS dual-gate FET, the gate length is increasingly shortened and the gate oxide film thickness is made thinner.
一般に、MOS、FETのゲート静電破壊強度は
そのゲート酸化膜がシリコンの熱酸化膜の場合、
膜厚10nｍ当り10Vと言われており、上記の高周
波用MOS双ゲートFETのゲート酸化膜厚は通常
数十ｎｍを採用しており、例えばゲート酸化膜厚
が60nｍの場合約60Vの静電破壊強度しか得られ
ない。従つて、従来はこのようなMOS双ゲート
FETに対してはゲート保護用のダイオードを設
けて保護していた。 In general, the gate electrostatic breakdown strength of MOS and FET is determined by the following when the gate oxide film is a silicon thermal oxide film:
It is said to be 10V per 10nm of film thickness, and the gate oxide film thickness of the above-mentioned high-frequency MOS double-gate FET is usually several tens of nanometers.For example, if the gate oxide film thickness is 60nm, the electrostatic breakdown will be about 60V. You can only gain strength. Therefore, conventionally, such MOS double gate
The FET was protected by providing a gate protection diode.
第１図は従来の保護用ダイオード付きMOS双
ゲートFETの一例の等価回路図である。 FIG. 1 is an equivalent circuit diagram of an example of a conventional MOS double-gate FET with a protection diode.
第１図において１はソース、２は第１ゲート、
３は第２ゲート、４はドレインの各電極で、５及
び６は保護ダイオードでゲート・ソース間に接続
されている。保護ダイオード５，６は互いに逆方
向特性となる様に縦続接続した２個のダイオード
の組から成り、第１ゲート・ソース間及び第２ゲ
ート・ソース間にそれぞれ接続してある。 In FIG. 1, 1 is the source, 2 is the first gate,
3 is a second gate electrode, 4 is a drain electrode, and 5 and 6 are protection diodes connected between the gate and source. The protection diodes 5 and 6 consist of a pair of cascade-connected diodes so as to have opposite characteristics, and are connected between the first gate and the source and between the second gate and the source, respectively.
第２図は第１図に示す保護ダイオード付き
MOS双ゲートFETのゲート・ソース間の電流−
電圧特性図である。 Figure 2 shows the protection diode shown in Figure 1.
Current between gate and source of MOS double gate FET -
It is a voltage characteristic diagram.
第２図に示すように、各バイアス方向とも逆方
向特性を示す。 As shown in FIG. 2, each bias direction exhibits reverse direction characteristics.
以上の様にゲート・ソース間に保護ダイオード
を接続すると第１ゲート・ソース間もしくは第２
ゲート間に入るサージ電力に対しては静電破壊強
度はゲート酸化膜厚50nｍでも100〜120Vに向上
する。ここで接続した保護ダイオードは１個当り
逆方向耐圧15V、印加電圧0Vの時の容量0.5pFの
ものを用いている。ここで保護ダイオード６，７
の耐圧は、ドレイン・ソース間の動作中の降伏電
圧を考慮しドレイン・ソース間最大定格電圧23V
以下でかつ第１、第２ゲートに入力するゲート信
号の電圧の最大値以上の値として15Vを採用して
いる。なおドレイン・ソース間最大定格電圧と
は、一般にドレイン・ソース間降伏電圧は回路動
作中の発熱・温度上昇の影響で常温での降伏電圧
よりも低くなるので、十分に余裕をとつて低く
し、回路動作状態も含めてトランジスタ破壊の起
きないことを保証する電圧である。 As described above, if a protection diode is connected between the gate and source, the protection diode between the first gate and source or the second
Against surge power that enters between the gates, the electrostatic breakdown strength improves to 100 to 120 V even with a gate oxide film thickness of 50 nm. The protection diodes connected here each have a reverse breakdown voltage of 15V and a capacitance of 0.5pF when the applied voltage is 0V. Here protection diodes 6, 7
The withstand voltage is the maximum rated drain-source voltage of 23V, taking into account the breakdown voltage during operation between the drain and source.
15V is adopted as the value below and greater than the maximum value of the voltage of the gate signal input to the first and second gates. The maximum rated voltage between the drain and source means that the breakdown voltage between the drain and source is generally lower than the breakdown voltage at room temperature due to the effects of heat generation and temperature rise during circuit operation. This is a voltage that guarantees that the transistor will not be destroyed, including the circuit operating state.
所で、MOS双ゲートFETがゲート・バイアス
電圧0Vでドレイン電流が流れないタイプ、すな
わちノーマリーオフ型の場合は、ドレイン・ソー
ス間にサージ電力が入つた場合に第２ゲート酸化
膜が静電破壊を起しやすい。これはノーマリーオ
フ型の場合、ドレイン・ソース間のインピーダン
スが非常に高く（１×1014Ω以上）、逆に第１、
第２ゲートとソース間インピーダンスが低いの
で、ドレイン・ソース間に入つたサージ電力はこ
れらインピーダンス比によつて分圧されてすべて
ドレイン・第２ゲート間にあるゲート酸化膜に加
わる為である。従つて従来のノーマリー・オフ型
FETの双ゲート型電界効果トランジスタは第２
ゲートの破壊による不良が主であつた。 By the way, if the MOS double-gate FET is of the type in which no drain current flows when the gate bias voltage is 0V, that is, it is a normally-off type, the second gate oxide film will become static when a surge power enters between the drain and source. Easy to cause destruction. This is because in the case of a normally-off type, the impedance between the drain and source is very high (more than 1×10 14 Ω);
Since the impedance between the second gate and the source is low, the surge power that enters between the drain and the source is divided by the impedance ratio and is all applied to the gate oxide film between the drain and the second gate. Therefore, the conventional normally-off type
The FET double-gate field effect transistor is the second
The main defects were due to broken gates.
またノーマリー・オン型FETの場合でも、第
１ゲートに逆バイあス信号が印加されてドレイン
電流が流れないカツトオフの回路動作状態におい
ては、ドレイン・ソース間にサージ電力が入つた
場合にノーマリー・オフ型に準じた回路動作をす
るので、前述と同様な第２ゲートの酸化膜が破壊
するモードとなる。 Furthermore, even in the case of a normally-on FET, in a cut-off circuit operating state where a reverse bias signal is applied to the first gate and no drain current flows, the normally-on FET will Since the circuit operates in accordance with the off-type, it becomes a mode in which the oxide film of the second gate is destroyed as described above.
本発明の目的は上記欠点を除去し、ドレイン・
ソース間にサージ電力が入つても第２ゲートの破
壊が起き難いノーマリー・オフ型の回路動作をす
る双ゲート電界効果トランジスタを含む半導体装
置を提供することにある。 The purpose of the present invention is to eliminate the above drawbacks and to
An object of the present invention is to provide a semiconductor device including a double-gate field effect transistor that operates as a normally-off type circuit in which the second gate is unlikely to be destroyed even if a surge power is applied between the sources.
本発明は、ソース、第１ゲート、第２ゲート、
ドレインの４電極よりなりノーマリー・オフ型の
回路動作をする双ゲート電界効果トランジスタを
含む半導体装置において、前記電界効果トランジ
スタのドレインと第２ゲート間に互いに逆方向特
性となる様に縦続接続した２個のダイオードを接
続したことを特徴とする。 The present invention provides a source, a first gate, a second gate,
In a semiconductor device including a double-gate field effect transistor having four drain electrodes and operating as a normally-off type circuit, two gates are connected in cascade between the drain and the second gate of the field effect transistor so as to have opposite direction characteristics. It is characterized by connecting diodes.
上記ダイオードの逆方向耐圧はノーマリー・オ
フ型の回路動作をする双ゲート電界効果トランジ
スタにおいて、前述の従来の第２ゲート・ソース
間のダイオード逆方向電圧の選定と同様に、ドレ
イン・ソース間最大定格電圧よりも低いものを使
用する。 The reverse breakdown voltage of the above diode is determined by the maximum rating between the drain and source in a double-gate field effect transistor that operates in a normally-off type circuit, similar to the selection of the diode reverse voltage between the second gate and the source in the prior art. Use something lower than the voltage.
次の本発明の実施例について図面を用いて説明
する。 The following embodiments of the present invention will be described with reference to the drawings.
第３図は本発明の一実施例の等価回路図であ
る。 FIG. 3 is an equivalent circuit diagram of an embodiment of the present invention.
ソース電極１１、第１ゲート電極１２、第２ゲ
ート電極１３、ドレイン電極１４を有するＮチヤ
ンネル型のMOS双ゲートFET10の第１ゲード・
ソース間及び第２ゲート・ソース間にそれぞれ互
いに逆方向特性となるように縦続接続した２個の
ダイオードの組１５，１６を第１図と同様に接続
し、更に第２ゲート・ドレイン間にも互いに逆方
向特性となる様に縦続接続した２個のダイオード
の組１７を接続する。ダイオードの組１５，１
６，１７はほぼ同等の特性を有する様に選ぶもの
とする。 The first gate and
A set of two diodes 15 and 16 connected in cascade between the sources and between the second gate and the source so as to have opposite direction characteristics are connected in the same manner as in FIG. 1, and also between the second gate and the drain. Two sets 17 of cascaded diodes are connected so that they have opposite characteristics. Diode set 15,1
6 and 17 shall be selected so that they have approximately the same characteristics.
具体的数値例を挙げると、MOS双ゲートFET
１０は第１及び第２ゲート酸化膜厚がそれぞれ
60nｍのＮチヤンネル型で、VDS＝5V、VG2S＝＋
4V、IDS＝10μAの条件のときVTH＝＋0.3Vのノー
マリオフ型で、ゲートのMOS容量は約3.2pFであ
り、ドレイン・ソース間最大定格電圧は23Vとす
る。このFET１０はゲート酸化膜厚が60nｍであ
るのでゲート・ソース間あるいはゲート・ドレイ
ン間の静電破壊強度は約60Vである。 To give a specific numerical example, MOS double gate FET
10 has the first and second gate oxide film thicknesses, respectively.
60nm N-channel type, V DS = 5V, V G2S = +
It is a normally-off type with V TH = +0.3V under the conditions of 4V and I DS = 10μA, the gate MOS capacitance is approximately 3.2pF, and the maximum rated voltage between drain and source is 23V. Since the gate oxide film thickness of this FET 10 is 60 nm, the electrostatic breakdown strength between the gate and source or between the gate and drain is about 60V.
これに使用する保護ダイオードの組１５，１
６，１７の各１個のダイオードは、前述の理由で
FET１０のソース・ドレイン間最大定格電圧23V
以下でかつ第１、第２のゲート・ソース間の保護
ダイード１５，１６の形成と同時に形成するよう
に耐圧15Vのものを用いる。また、各１個のダイ
オードの容量は、印加電圧0Vのとき0.5pFであ
る。 Protective diode set 15,1 used for this
One diode each for 6 and 17 is
Maximum rated voltage between source and drain of FET10 23V
A diode with a withstand voltage of 15 V is used in the following and so as to be formed simultaneously with the formation of the protection diodes 15 and 16 between the first and second gates and sources. Further, the capacitance of each diode is 0.5 pF when the applied voltage is 0V.
次に、本発明の効果を説明するために、静電破
壊に至るまでの電圧についての測定結果について
説明する。 Next, in order to explain the effects of the present invention, measurement results regarding the voltage up to electrostatic breakdown will be explained.
第４図はMOS FETのゲートの静電破壊強度
試験装置の回路図である。 Figure 4 is a circuit diagram of a MOS FET gate electrostatic breakdown strength testing device.
この試験装置は、容量1000pFのコンデンサに
電圧可変電源２２より電荷を供給し、定常状態に
なつた所でスイツチ２３を被測定端子２４側に切
換え、被測定素子２５にサージ電力を与え、被測
定端子２５のドレイン・第２ゲート間がシヨート
破壊しているかどうかを調べるものである。 This test device supplies charge to a capacitor with a capacity of 1000 pF from a variable voltage power supply 22, and when a steady state is reached, switches the switch 23 to the terminal under test 24, applies surge power to the element under test 25, and This is to check whether there is shot damage between the drain and second gate of the terminal 25.
第５図は第１図に示す従来の保護ダイオード付
きMOS双ゲートFETのゲート静電破壊強度の一
例を示す分布図、第６図は第３図に示す本発明の
一実施例のゲート静電破壊強度の一例を示す分布
図である。 FIG. 5 is a distribution diagram showing an example of the gate electrostatic breakdown strength of the conventional MOS double-gate FET with a protection diode shown in FIG. 1, and FIG. FIG. 3 is a distribution diagram showing an example of breaking strength.
被測定のMOS双ゲートFETは、耐圧その他の
特性の揃つたものを２つに分けたものを用いてい
る。具体的には第３図の所で説明したゲート酸化
膜厚が60nｍで、ドレイン・ソース間最大定格電
圧が23Vのものを用い、保護ダイオードは耐圧
15Vのものを用いている。 The MOS double-gate FET to be measured is divided into two parts with the same breakdown voltage and other characteristics. Specifically, we used a gate oxide film with a thickness of 60 nm and a maximum rated voltage of 23 V between the drain and source as explained in Figure 3, and a protection diode with a withstand voltage of 23 V.
I am using a 15V one.
第５図に示すように、従来品では静電破壊強度
は66Vをピークにして55〜70Vの間に分布してい
る。これに対して本発明品は115Vをピークにし
て105〜120Vの間に分布している。この差は、ノ
ーマリーオフ状態のMOSFETのドレイン・第２
ゲート間に保護ダイオード１７を接続したことに
よるもので、ドレイン・ソース間に印加された外
来サージ電力が、インピーダンスの低いソース・
第２ゲートを介して保護ダイオード１７に吸収さ
れていることを示す。このように、本発明によれ
ばゲートの静電破壊強度を約２倍に向上させるこ
とができる。 As shown in FIG. 5, in the conventional product, the electrostatic breakdown strength peaks at 66V and is distributed between 55 and 70V. On the other hand, the product of the present invention has a peak of 115V and is distributed between 105 and 120V. This difference is due to the difference between the drain and second MOSFET in normally off state.
This is due to the protection diode 17 connected between the gates, so that external surge power applied between the drain and source is transferred to the source with low impedance.
It shows that it is absorbed by the protection diode 17 via the second gate. As described above, according to the present invention, the electrostatic breakdown strength of the gate can be approximately doubled.
上記実施例ではノーマリーオフ型について説明
したが、ノーマリーオン型、すなわち第１ゲー
ト・バイアス電圧が0Vのときにドレイン電流IDS
が流れるタイプにおいても、動作状態で特に
AGC（自動利得調整）動作によつて逆バイアスが
かかつた場合の様にドレイン電流が微小な値の時
は、ドレイン・ソース間のインピーダンスが高く
なりドレイン側から外来サージ電力が入射された
場合、殆んどドレイン・第２ゲード間に印加され
るため本発明の保護ダイオード接続を有効であ
る。又、ゲート構造はMOS型に限らず、接合型、
シヨツトキ・バリヤ型等においても有効である。
もちろん、チヤンネルの導電型はＮ型でもＰ型で
も可能で、半導体材料はシリコンのみならず
GaAs等の化合物半導体でも良い。なお、シング
ルゲード型のFETでは、ドレイン・ゲート間に
保護ダイオードを接続すると帰還容量が大きくな
り、VHF帯もしくはUHF帯で利得の低下、回路
の安定性を損う場合があるが、本発明の様に双ゲ
ート型では第２ゲート電位は一般に高周波的に接
地に等しくなるのでこの様な心配はない。 In the above embodiment, the normally-off type was explained, but in the normally-on type, that is, when the first gate bias voltage is 0V, the drain current I DS
Even in the type where the current flows, the
When the drain current is a small value, such as when reverse bias is applied due to AGC (automatic gain adjustment) operation, the impedance between the drain and source becomes high, and external surge power is input from the drain side. , is applied mostly between the drain and the second gate, so the protection diode connection of the present invention is effective. In addition, the gate structure is not limited to MOS type, but also junction type,
It is also effective for shotgun barrier types.
Of course, the conductivity type of the channel can be N type or P type, and the semiconductor material is not limited to silicon.
A compound semiconductor such as GaAs may also be used. In addition, with a single-gade type FET, connecting a protection diode between the drain and gate increases the feedback capacitance, which may reduce the gain in the VHF or UHF bands and impair the stability of the circuit. Similarly, in a double-gate type, the second gate potential is generally equal to ground at high frequencies, so there is no such concern.
以上説明した様に、本発明によれば、ノーマリ
ー・オフ型の回路動作をする双ゲート型電界効果
トランジスタの第２ゲートの破壊強度を大きく向
上させることが可能となり、ノーマリー・オフ型
の回路動作をする双ゲート型電界効果トランジス
タを含む半導体装置そのものの製造工程、特に選
別、検査工程中における静電気的又は測定系から
入るサージ電力等に起因するゲート破壊を防止す
ることができ、更に、これらの半導体装置を用い
たチユーナ等のセツトの製造工程中にたまたま起
るゲート破壊も防止でき、さらにセツトの市場に
おける稼動中のこれら半導体装置のゲート破壊も
防止できるという効果が得られる。 As explained above, according to the present invention, it is possible to greatly improve the breakdown strength of the second gate of a double-gate field effect transistor that operates in a normally-off type circuit, and It is possible to prevent gate breakdown caused by static electricity or surge power entering from the measurement system during the manufacturing process of the semiconductor device itself, including the double-gate field effect transistor, especially during the sorting and inspection process. It is possible to prevent gate breakage that happens to occur during the manufacturing process of sets such as tuners using semiconductor devices, and furthermore, it is possible to prevent gate breakage of these semiconductor devices during operation in the set market.
第１図は従来の保護ダイオード付きMOS双ゲ
ートFETの一例の等価回路図、第２図は第１図
に示す保護ダイオード付きMOS双ゲートFETの
ゲート・ソース間の電流−電圧特性図、第３図は
本発明の一実施例の等価回路図、第４図は
MOSFETのゲートのゲートの静電破壊強度試験
装置の回路図、第５図は第１図に示す保護ダイオ
ード付きMOS双ゲートFETの静電破壊強度の一
例を示す分布図、第６図は第３図に示す一実施例
のゲート静電破壊強度の一例を示す分布図であ
る。
１，１１……ソース、２，１２……第１ゲー
ト、３，１３……第２ゲート、４，１４……ドレ
イン、５，６，１５，１６，１７……保護ダイオ
ード、１０……MOS双ゲートFET、２１……コ
ンデンサ、２２……電圧可変電源、２３……スイ
ツチ、２４……被測定端子、２５……被測定素
子。
Figure 1 is an equivalent circuit diagram of an example of a conventional MOS double-gate FET with a protection diode, Figure 2 is a current-voltage characteristic diagram between the gate and source of the MOS double-gate FET with a protection diode shown in Figure 1, and Figure 3 The figure is an equivalent circuit diagram of one embodiment of the present invention, and Figure 4 is
A circuit diagram of the electrostatic breakdown strength testing device for the gate of a MOSFET. Figure 5 is a distribution diagram showing an example of the electrostatic breakdown strength of the MOS double-gate FET with a protection diode shown in Figure 1. FIG. 3 is a distribution diagram showing an example of gate electrostatic breakdown strength of the example shown in the figure. 1, 11... Source, 2, 12... First gate, 3, 13... Second gate, 4, 14... Drain, 5, 6, 15, 16, 17... Protection diode, 10... MOS Twin gate FET, 21... Capacitor, 22... Voltage variable power supply, 23... Switch, 24... Terminal to be measured, 25... Element to be measured.
Claims (1)
インの４電極よりなりノーマリー・オフ型の回路
動作をする双ゲート型の電界効果トランジスタ
と、前記ドレインと前記第２ゲートとの間に互い
に逆方向に縦続接続されて挿入されかつ前記電界
効果トランジスタのドレイン・ソース間最大定格
電圧よりも低い逆方向耐圧を有する２個のダイオ
ードとを含むことを特徴とする半導体装置。1. A double-gate field effect transistor that operates as a normally-off circuit and consists of four electrodes: a source, a first gate, a second gate, and a drain; two diodes inserted in cascade connection and having a reverse withstand voltage lower than the maximum rated voltage between the drain and source of the field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23239682A JPS59117165A (en) | 1982-12-23 | 1982-12-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23239682A JPS59117165A (en) | 1982-12-23 | 1982-12-23 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59117165A JPS59117165A (en) | 1984-07-06 |
| JPH0550146B2 true JPH0550146B2 (en) | 1993-07-28 |
Family
ID=16938578
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23239682A Granted JPS59117165A (en) | 1982-12-23 | 1982-12-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59117165A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0646964B1 (en) * | 1993-09-30 | 1999-12-15 | Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno | Integrated structure active clamp for the protection of power devices against overvoltages, and manufacturing process thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5611437A (en) * | 1979-07-09 | 1981-02-04 | Toshiba Corp | Liquid crystal display element |
-
1982
- 1982-12-23 JP JP23239682A patent/JPS59117165A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5611437A (en) * | 1979-07-09 | 1981-02-04 | Toshiba Corp | Liquid crystal display element |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59117165A (en) | 1984-07-06 |
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