JPS60256282A - Signal generator for video printer - Google Patents

Abstract

PURPOSE:To attain print without deflection by providing a comparator comparing the phase of a horizontal synchronizing signal and an output of 1/2 frequency divider, an oscillator and a circuit discriminating odd/even number field to obtain a frame signal based on the original signal. CONSTITUTION:The oscillator 5 is oscillated in a frequency of 525fV in synchronization with a vertical synchronizing signal frequency fV. The output of the oscillator 5 is subjected to 1/2 frequency division (6) and the result is outputted to a phase comparator section 8. A composite synchronizing signal C of a video signal inputted from the input terminal is extracted by a synchronizing separator circuit 7 and the result is outputted to a comparator section 8. Then the comparator section 8 compares inputs B and C, and when the phase of the signals is identical, a positive signal is outputted and when the phase is opposite to each other, a negative signal is outputted. Further a discriminating section 9 counts the signal for each positive/negative period and only when the positive or negative mode for a prescribed period or over is consecutive, the code is fed to a discriminating output section 10, from which a discriminating signal is outputted. When the mode is a mode below the prescribed period, the preceding mode signal is outputted consecutively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a video printer that uses a television signal as input information to print a television screen, and particularly relates to a signal generating device suitable for field discrimination.

[Background of the invention]

Conventional devices, for example, as described in Japanese Patent Application Laid-Open No. 50-67515, use a signal triggered by a horizontal pulse signal to generate the first or second pulse within the vertical 1α retrace period and the vertical pulse. A method is known in which an odd field and an even field are determined by detecting a phase difference with a synchronizing signal. However, with this method, the horizontal synchronization signal is missing when the electric field is weak.1. No consideration was given to cases such as when noise is superimposed on the horizontal synchronization signal, or when the input video signal is discontinuous due to jitter or the like. For this reason, a video printer that prints one frame screen corresponding to one screen on a television screen may not be able to print a screen that is faithful to the original image.

This will be explained briefly. In order to obtain a resolution higher than that of a television screen, video printers usually convert all the signal information of the video parts of the two field images that make up one frame picture into A/D at high speed, store it in memory, and read it out at low speed. Print. Therefore, if the two fields, that is, the odd and even fields, are mistakenly determined, a printed image as shown in FIG. 1(a) will result, which will be greatly different from the correct flag image shown in FIG. 1(b).

Furthermore, when only one of the odd-even fields can be discriminated, a printed image may be obtained in which the signal is missing for each line, or a printed image in which two screens are overlapped.

[Purpose of the invention]

An object of the present invention is to be able to obtain a frame signal based on the original signal even in a weak electric field or when the input video signal is discontinuous including jitter, etc., and to print without blur or double contours. An object of the present invention is to provide a frame signal generating device for a video printer that can generate a frame signal for a video printer.

[Summary of the invention]

In the present invention, the even/odd discrimination of the input signal is performed not only by the vertical synchronizing signal section but also by using the 525 fv (fv
is the horizontal synchronization signal frequency of the input signal and the horizontal synchronization signal of the input signal.
Fields are determined to be even or odd by comparing the phase of each horizontal synchronization signal, and for a determination output that is sufficiently shorter than one field, the polarity of the determination output is inverted or maintained by counting the period of the determination signal. Moreover, if the above determination also shows indeterminacy, a device is added that focuses on one arbitrary field and outputs an interlaced pseudo frame signal.

[Embodiments of the invention]

Hereinafter, a block diagram showing one embodiment of the present invention will be explained with reference to FIG. 1 is a vertical synchronization signal input terminal, 2 is a video signal input terminal, Sa, 5t) is a field discrimination output terminal, 4 is a frame signal output terminal, 5 is a vertical synchronization signal input terminal, and 525
An oscillator that oscillates at a frequency of fv, 6 an i frequency divider 97, a synchronous separation circuit, 8 a phase comparison section, 9 a determination section, 10 a discrimination output section, and 11 a pseudo frame generation circuit. FIG. 6 shows a timing chart of the block diagram of FIG. 2, and the operation of the blocks will be explained. The vertical synchronizing signal A inputted from the input terminal 1 is inputted to the oscillator 5. This oscillator is 525 fv synchronized with the input vertical synchronization signal frequency fv.
It oscillates at a frequency of . For example, P L L
(Phase Locked Loop) V of the circuit
CO (Voltaque Controlled Osc)
illustrator). The output of the oscillator 5 is divided by i while being synchronized with the vertical synchronization signal from the input terminal 1 by the frequency divider 6 and 7, and becomes a signal B with a frequency of 262.5 fv, which is the 0 phase signal that is output to the phase comparator 8. In addition, the comparator 8 extracts a composite synchronization signal C of the video signal input from this input terminal by the synchronization separation circuit 7 and outputs it to the phase comparator 8 . The phase comparator 8 compares inputs B and C and outputs a positive signal (or negative signal) when they are in phase, and a negative signal D (or a positive signal) when they are in opposite phase. The determination unit 9 counts the period of each positive input signal 1), and outputs each mode only when the positive and negative modes continue for a period of, for example, 10H() (one horizontal period) or more. is output to the discrimination output section 10. MafC
For periods less than 10H, the previous mode output continues to be output. The discrimination output section 10 outputs an even field discrimination signal to the V output terminal 5a when the output of D is positive.

When the output of D is negative, that is, an odd field discrimination signal is outputted to the output terminal 5b. In addition, the output of the phase comparator 8 randomly outputs a signal to be judged as an even-odd field like D'. The outputs of the section 9 are all negative, and the output of the discrimination output section 10 is 3a'.

It becomes negative together with 3h'. At this time, the output to the pseudo frame generation circuit 11 becomes positive, and a pseudo frame signal is output from the output terminal 4. As described above, according to this embodiment, it is possible to perform field even/odd discrimination even in a signal in which a part of the synchronization signal of the input video signal is missing or in a video signal in which noise is superimposed on the synchronization signal. Also S/H
Since it automatically creates and outputs a pseudo-frame signal even for degraded signals or signals where it is impossible to distinguish whether the field is even or odd, it is extremely effective for video printers that print based on the information of one frame. It is.

FIG. 4 shows an embodiment of the determination section 9 in FIG. 2.

21 is an input terminal 92 for the horizontal synchronization signal from the synchronization separation circuit 7
2 is the input terminal of the output of the phase comparator 8, 25.27 is S-
R-type flip-flop (hereinafter abbreviated as S RF, F)
, 24.32 is AND game), 25.55 is 10
It constitutes a decimal counter and counts consecutive 10H periods, which serve as a reference for determining whether the field is an odd-even field in the determining section 9. 26, 61 and 34#'i0R
28 is the output terminal of the determining section 9, 29 is a differential circuit, and 0 is an inverter. The operation will be explained using the timing chart shown in FIG.

The output signal of the phase comparator 8 from the input terminal 22 is 5-R.
F, F, 25 generates a pulse to gate the horizontal synchronizing signal input from the input terminal 21 from the Q output section, and the A
ND gates 24 and 32 gate the horizontal synchronization signal and output e and f as clock inputs to counters 25 and 33, respectively. Counters 25 and 3'5 count the clock input, and when it is 1o pulse or more, output a pulse, and the 5th
In the figure, the counter 25 outputs an output pulse g. This output pulse g is input to the S-RF, F, 27, and the output from the Q output terminal is outputted to the output terminal 28. That is, the Q output state of Te5-RF, F' changes for the first time due to the output pulse g. Furthermore, in order to change the state of the output terminal 28, an output pulse from the counter is similarly required. ○ Connecting the F outputs of the counters 25 and 33 to the R input via the OR gates 26 and 34 is the clock input. This is because when the number of pulses is 10 or more, the counter continues to operate 7 and outputs the entire set of pulses, so as not to erroneously output the determination unit 9. In addition, inputting the input signal of the phase comparator at the input end 22 to the same R input end via the differentiating circuit 29 is advantageous in that when the number of clock pulses is small, the counter operation does not stop in the middle, and the counter reaches the zero state. This is to start the counter operation from. Further, for the same reason, 5-RF, F, which generates a signal to gate the horizontal synchronization signal from the input terminal 21,
The F outputs of the counters 25 and 33 are also input to the R input terminal of the counter 23. When the output signal of the phase comparator 8 from the input terminal 22 has a fixed polarity period, the input terminal 2 is connected to the R input of S/RF, F, via the inverter 30 and the OR gate 51.
The signal No. 2 propagates and turns off the Q or low output pulse which is the gate output of 5-RF, F, and turns off the clock input to the counter circuit. The determination unit can be configured using the circuit configuration example described above.

FIG. 6 shows an example of a pseudo frame generation circuit.

2.4.11i This is the same block as in FIG. 12 is a control signal input terminal of the discrimination output section 10 shown in FIG. 3; 13 is a pseudo frame creation switching signal input terminal; 14-digit 1H delay line; 15 is an adder; 16 is a ->H delay line; 17
and 18 are signal switching circuits. Pseudo frame generation circuit 1
1, the signal switching circuit 18 is connected to the b side and the pseudo frame signal is output to the output terminal 4 only when it is impossible to discriminate between odd and even fields according to the control signal of the discrimination output section 10. Normally, it is connected to side a and the video signal from input terminal 2 is output. The pseudo frame signal is created as follows. 1 field of video signal from input end 2
Pass through H delay line 14 and delay by 1H and adder 15
The signal added to the original signal is delayed by -H delay line 16 by 15H, and the signal is switched by signal switching circuit 17 using a pseudo frame creation switching signal from input terminal 13 and output. The reason for the 1H delay is that one field period is 262.5H and 1H.
This corresponds to the fact that an offset is added. The reason for adding the signal after passing through the 1H delay line and the original signal is as follows.
This is to reduce the signal difference between lines in one field signal by utilizing the correlation between the video signals before and after IH, and to soften the roughness of the screen.

〔Effect of the invention〕

As explained above, by using the present invention in a video printer, even when the horizontal synchronization signal is missing, discontinuous video signals including jitter, etc., and video No. 18 with superimposed noise can be used. Information equivalent to one frame can be obtained, making it possible to print faithfully to the original image.

[Brief explanation of the drawing]

Fig. 1 is a pattern diagram showing an example of printing errors; Fig. 2 is a block diagram showing an embodiment of the present invention; Fig. 3 is a flowchart of Fig. 1; and Fig. 4 is a specific example of the determination section. FIG. 5 is a timing chart diagram of FIG. 4, and FIG. 6 is a circuit diagram of a pseudo frame signal generation circuit. 5... Elevator 8... Phase comparator 10... Discrimination output unit 11... Pseudo frame signal generation circuit agent yP engineer Akio Takahashi 1 Figure 1 - ~ To' (Figure 5 6th

Claims (1)

[Claims] 1. An oscillator with an oscillation frequency of 525 fV (fv is the vertical synchronization signal frequency) synchronized with a vertical synchronization signal, and an oscillator that combines the output of the oscillator with the rising edge of the vertical synchronization signal and the Yu branching unit. A means for comparing the phases of outputs, and a means for discriminating between even and odd fields in a video signal based on the output of the comparing means, and a discrimination output detecting means for detecting that the output of the discriminating means does not change for a predetermined period of time; 1. A signal generating device for a video printer, comprising means for switching and controlling a discrimination output based on a detection output. 2. means for detecting an uncertain change in the output of the field discriminating means;
Signal generation for a video printer according to claim 1, comprising means for extracting only a field, and frame signal generation means for generating a pseudo frame signal from the extracted one field signal. Device.