JPS60256226A - Signal selection circuit - Google Patents

Abstract

PURPOSE:To attain ease of circuit integration by inputting an output of a signal selection circuit via a frequency division counter and inputting an output of a synchronizing circuit to the selection circuit as a control signal to reduce malfunctions when the phase shift between a switching signal and the control signal is large. CONSTITUTION:Pulses N1, N2 of opposite phase from a 1/2 counter 101 are inputted to the signal selection circuit 100, the 1st control input 123 is fed to a NAND gate 118 via an inverter 103 of the circuit 100 and also fed directly to a NAND gate 113. The circuit 100 consists of the combination of the NAND gate and inverter controlled by the clocks N1, N2 and an output N3 of the circuit 100 is processed by 1/2 and 1/10 counters 102, 120. An output N5 of the counter 120 is fed to a synchronizing circuit 121 and plural inverters of the circuit 121 are controlled by the clock. Then an output N6 of the circuit 121 is inputted to gates 113, 118 of the circuit 100 as the 2nd control signal to prevent malfunctions due to phase shift between the switching signal and the control signal.

Description

[Detailed description of the invention]

Industrial Field of Application The present invention is directed to PLL (Phase Locked
A two-coefficient frequency divider used in the (LOQp) circuit, especially (2N
The present invention relates to a signal selection circuit having 1 to 4 switching units of 1/2N (N is an integer) of 1/2N (N is an integer). Structure of the conventional example and its problems FIG. 1 shows the structure of the conventional example. 1 is a first counter, 2 is a second 1A counter, 3 is a 1 counter, and 4 is a signal selection circuit. 5-8.32rJ, inverter, 9
16.31 is a NAND gate, 17.18 is an AND gate, and 19 is a NOR gate. First bow Kaunota 1
The output with the opposite phase to 11-2) is the signal 1. J selection 17 (connected to circuit 4, Jl, selected tl output is connected to second lh counter 2, output of second lh counter 2 is connected to martyr counter 3, and NAND gate 9 -) j is connected to the input 71, and the other input is connected to the output of the mouse counter 3 at h. Output i1 of NAND gate 9, inverter 5
is one of the switching control inputs of the signal 11<circuit 4. 26 is another 1ilJ exchange control large control. The configuration of the reliability selection circuit 4 will be explained below. The NAND gate 16.16 forms a set/reset flip flow knob. The AND gate 17.18° and the OR gate 19 form a selector. 9 exchange control human power 26
is connected to NAND gate 10-\ via NAND gate 11 and inverter 6. The output of inverter 5 is connected to NAND gate 10.11
ing. The outputs of NAND gates 10 and 11 are connected to NAND gates 18 and 31 via inverters 7 and 8, respectively. NAND gate 1
3 and 31 outputs (11, Furinobuno's NAND gates 1-15 and 16' forming the J knob are connected respectively. The output of the flip-flop is 1, and the output 29 of the NAND gate 15 is Continue, NAN
The output 28 of the D gate 1-16 is connected to the AND gate 18-\tl. AND gate 17.18 and N0F
The output of the I gate 1-19"7' configured selector, that is, the output of the NOR gate 19, is connected to the NA[l gate 13.31 via the inverter 32. The first A counter 1 mutually antiphase outputs 21 and 2 of
2 is connected to the AND game (17 and 18) that constitutes the selector. Switching control input 26: and other switching control inputs, i.e.
The output of the inverter 6 and the output of the lA counter 1 having opposite phases to rj are selected by the signal selection circuit 4 and output. The conventional example shown in FIG. 1 is a two-coefficient prescaler, and as a whole constitutes a counter with coefficient switching of 1/40.1/41 iiT fE. Next, the operation of the conventional example will be explained using the timing chip \--1-. The second diagram is a timing chart showing the timing of the main parts. 20 is the input pulse of the first A counter -C, 21.22 is the input pulse of the first A counter, and 21.22 is the inverse 11
This is the output of the on-phase. 23 is the output of the reliability selection circuit 4, and 30 is the output of the inverter 32. 24 is the output of the second duck counter 2, and 25id1/
This is the output of the 1o counter 3. 26 and 27 are switching control inputs. 28 and 29 are the outputs of the flip-flops. Flip-flop output 28
9 is at the IPA level, one output signal 21 of the first A counter 1 is output as the output of the signal selection circuit tl, and the output 23 is the inverted phase thereof. At the timing of tl, the output 25 of the death counter 3 becomes “...
At the timing t2, the output 24 of the counter 2 of the second A becomes the "NO\I" level, and at the timing t3, the output 30 of the inverter 32 becomes the "HIGH" level. ,25.The logical product of 30 is taken tl,
The input 27 of the flip-flop goes to a low level. At this time, the output 28 of the Flinopf I'lJ knob becomes ``hyper level''. Further, the output 29 of the other force of the flip-flop becomes a low level at timing t4, delayed by the width of the output pulse of the first 1, 4 counter. To control the outputs 28 and 29 of the flip-flop, 1, the output signal 23 of the selector is switched from the output 21 of the first lA counter 1 to the output 22 of the opposite phase. During the period T1, the output signal 21 is selected and its inverted signal is output to the output 23 of the selector, and during the period T2, the output signal 22 is selected and its inverted signal is output to the output 23 of the selector.
Output to. During the operation of T3, selector output signal 2
3 n "low level. Paying attention to the output signal 23 of the selector, at the timing t4, the output 21.22 of the first A counter 1 has been switched, and the "low level" has been repeated twice, and then the second The output 23 of the filleter is / for one pulse of the input 2o of the A counter 1 of
The pulse count of the entire system is 41.
Therefore, the 141st station stop j・j (I is present. The restriction on the operation on the main-east side is that the signal selection circuit 4 is output 7
1, then the delay of the second A counter 2, or r61,
Ko/re delay, O': Hi, NAND gate 9. Inverter 6, and NAND gate 11NAND gate 10. Inverter 8. Alternatively, the sum 81 of the delay times of the inverter 7 and the NAND gate 31 or the NAND gate 13 is the output 21.2 of the first A counter 1.
It must be within the period of 2. The negative voltage of the flip-flop composed of (-t, NAND game) 15.18 inside the signal selection circuit is heavy, and is a factor that determines the speed of the switching operation. This makes it difficult for relatively low-speed devices such as 0MO3 (complementary field effect transistors) to operate at high speeds. The disadvantages of this conventional example at operating frequencies where delay time is a problem as described in section 1-1 will be described below. FIG. 3 shows a timing chart when the frequency is high. The timing shows the same points as in Figure 2,
Use the same number. When the frequency increases and the phase of the output of the second A/R2 changes at timing t5 of the trailing edge of the "high" level of the output 30 of the inverter 32, the output 27 of the NAND gate 31 changes at timing t5. °1

[It becomes JI+ level, and from this point on, the output 28 of Furinobuf IJ Nozo...
I°rubell'\transition. At this time, the output 23 of the signal selection circuit 4 is already at "hyper level", and the output 28 of the flip-flop is "high level".
Until the anti-phase output 29 of the "Norinobuf 1" knob reaches the "lower level", the output signal 23 of the selector becomes "low".
Since the level -C is present, it becomes the "low'9 level at timing t6. At this point, the output 21 of the first A counter 1
Then, the signal is switched to the opposite phase output 22, and the output of the signal selection circuit generates a pulse at the timing between t5 and t6, as shown in FIG. 3, and +P! cause an action. The frequency becomes higher and the second 112 counter 2
FIG. 4 shows a timing chart when the phase of the inverter 32 is located at the trailing edge of the "..." level of the output 30 of the inverter 32. In this figure, as in FIG. 3, the timings indicate the same locations as in FIG. 2, and the same numbers are used. In this case, the output 27 of the NAND gate 31 is “low”.
``The time width of the level becomes smaller, the flip-flop cannot be inverted during this time, the output 28, 29 does not change, and signal switching becomes impossible. 0MO3
If the operating speed of the device itself is slow, it will malfunction at high frequencies and eventually become inoperable. FIG. 6 shows the frequency characteristics when a conventional selection circuit is made of a CMO8 integrated circuit. 4o is the frequency characteristic of the minimum operating voltage, and the shaded area 41 is the malfunction area. Purpose of the Invention The present invention eliminates malfunctions and malfunctions at high frequencies, which are the drawbacks of the conventional example, and provides a reliable selection system that can obtain good frequency characteristics when implemented in an integrated circuit such as a CMOS device. It provides a circuit. Structure of the Invention To summarize, the present invention comprises: an input terminal to which two types of pulses having mutually opposite phases are applied; first to fourth HAND gates; and first to fourth HAND gates. a second inverter, a selector, and a synchronization circuit, the first control input is connected to the first inverter and the first NAND gate, and the output of the first inverter is connected to the second NAND gate. and the first NAND
The output of the gate is connected to the third NAND gate, the output of the second and third NAND gate is connected to the fourth NAND gate, and the output of the fourth NAND gate is connected to the second inverter and the third NAND gate. Connect the NAND gate to one control input of the selector, connect the output of the second inverter to the other control input of the selector, and connect the input terminals of two types of pulses with mutually opposite phases to the controlled input of the selector. Then, connect the second control input to the same 1g1 circuit (with a synchronous circuit, the second control input's 19]'Th
and set the output to 1st. Connect the output of the second NAND gate to the output of the second inverter, connect the output of the second inverter to the output of the second inverter, and connect the output of the second inverter with the opposite phase pulse. It is constructed so as to be controlled by (Le×).In this J+, a signal selection circuit that does not malfunction even in high frequency operation is realized.'Left fb7) Explanation FIG. 6 shows the configuration of an embodiment of the present invention. 101°10
2 is the L duck counter, 103 to 108 are in・(-ta, 1
Reference numerals 09 to 112 designate inverters whose outputs are controlled by a clock.When the clock is at a low level, the inverter outputs are 1, and when the clock is at a "low" level, the inverters are in a high impedance state. 113-11 are NAND gates, 118,1
19 is a NAND gate whose output is controlled by a gate; when the clock is at the high level, the NAND output becomes tl; when the low level is 11, the impedance becomes low. . At 12 degrees, the mouse counter 121 has the same 191 circuit. 122 is the input signal of the counter 101, N
1 and N2 are pulse outputs of the 1.4 counter 101 having mutually opposite phases. First control human power 123, inverter 103, i, ・
and NAND gate 113-\connection, Inno 2-
The output of the gate 103 is connected to a NAND gate 118 which is controlled by a clock. The output of NAND gate 113 is connected to clocked NAND gate 119, which is connected to clocked NAND gate 118,1.
1 to the output of 19, connected to NAND gate 1114, 1
1 for the output of 14, and inverter 1 controlled by the I cock.
09, NAND gate 116, and clock-controlled NAND gate 119. The output of the inverter 119 controlled by the clock and the output N1 of the intestine counter 101 are connected to the N A N D gate 11
6, the output of the NAND gate 114 and the output N2 of the rare counter 101 are connected to the NAND gate (NAND gate) 115.
The output of the NAND gate 116°116 is
Connected to NAND gate 117 71.117 output signal 1. Output N of J board selection circuit 1o○,) set. Out) J believe do [, connected to the intestine counter 102 t'+
, the output of the counter 102 is connected to the counter 120, and the output N5 of the counter 120 is another control input of the confidence selection circuit. Output of mouse counter 120 N 5 r, I, inverter 1
The output of the inverter 108 is connected to the clock-controlled inverter 112, and the output of the inverter 112 is connected to the clock-controlled inverter 111 via the inverter 107 and 106. t
l, the output of the inverter 111 is the inverter 105'
(!--via the clock-controlled inverter 110
The output of 110 is connected to inverter 104 . The output of inverter 104 is connected to Nfi method NAND gate 113 and clock controlled NAND gate 118. NAND gate (controlled by clock) 118°119
The control clock input of is the output N1 of the μ counter 101.
is connected. clock controlled inverter, 11
1, the output N+ of the IA counter 101 is connected to the control clock 101. The output N2 of the A counter 101 is connected to the control clock inputs of the inverters 109, 110, 111 and 112 which are controlled by the clock. Inverters 104, 106, 106, 107, 108 and inverters 110, 111 .
112 constitutes a synchronous circuit 121. NAND gates 116, 116, and 117 constitute a selector. The overall system shown in FIG. 6 has a frequency division ratio of 1//4o. It constitutes a counter that performs 1/41 switching. Next, the operation of this embodiment will be explained using a timing chart. FIG. 7 shows the timing of the main part of the L of this embodiment by 7 dots, and the indicated points are indicated with the same symbols as in FIG. 6. 123 is the manual switching control (7
') 1-)-('Al. N:+ is the output of the signal [/J selection circuit 100, N4i, [X+, 4 counter 10
The output of No. 2, N5, is the output of the mouse counter 120, and is the switching control input of the signal selection circuit 100. N6(', L, the same J9+ is the output of the 1111 path 121, N'zVi is the output of the NAND gate 118 which is also controlled by the clock tI, and N8 is the output of the NAND gate 118 which is also controlled by the clock t
This is the output of the HAND gate 119. Nqi is the output of the clock-controlled inverter 109;
Neo is the output of the NAND gate 114, Ne,
NIO is controlled by a selector that selects pulses N+ and N2 of opposite phase to tl. First, the switching control human power 123 is at the high level, and the output N9 of the inverter 109 controlled by the clock is "high".
level, when the output N of the HAND gate 114 is at the low level, the signal is selected [output N3 of the 4-way 100].
In this case, N1 is selected and outputted as rl and i+. At the tI-th timing, the switching control human power 123 becomes "low"
level, and at the timing of tlo2, the output of the fortune counter, that is, the other switching control input N5 becomes the "high'° level. N5 is input to the same N] circuit 121, and the A
The same Ig1 is taken by the outputs Nl and N2 of the counter 101, and the output N6 goes to the "high" level fx after repeating L times to N2 at timing t+o:+. N6J7j, rz
NAND game day 18 controlled by Tsuk, and NANI
NA controlled by Kuronokuchi via lr'-to 119
Applied to ND gate 119. The control clock input of 118 and 119 is connected to the output of A color/101 (L+), and at timing t104 when N1 becomes "hyper level", the outputs Nr and Ns become "low level". . At this time, the output NIO of the NAND game 1114 becomes "low" level. NIO is an inverter 109-\input that is controlled by a clock, and the output N2 of the counterfeit counter 101 is input to the control clock input of 109, and the timing t+o when N2 becomes "high" level.
The output N9 of sf, 109 is "low" level tonal. With this, Ne becomes low N level and Neo becomes high I level, and the output N3 of the input circuit switches from Ne to N2. During the period from timing t4 to t5, Ne, Both Neo and N1 have °high' level, and N2 has °high' level.
Although the level is 'low', the NAND gate 116
The output of the 116 is at the "high" level, and the output N3 of the reliability selection circuit is at the "high" level. At t105, when the switch from N1 to N2 is fc, the level of N2 is 0 high'' level, the ``high'' level is output to N3, and the ``hyper level'' is output twice. tAnother thing happens.This t′+ is A
Based on the input 122 of the counter 101, one pulse is passed through, and one extra count is counted. At timing t106, switching control input N5 becomes "high"
When the level changes to “low” level, the synchronization circuit 12
1's output N6 is synchronized with N2 at timing t+o
(C becomes "low" level, and N7 becomes "high" level at timing t108'c in synchronization with Ne.) Next, the switching operation 8 from the output N2 of the A counter to N1 will be explained. At timing t108. , when the switching control human power 123 reaches the "hyper level" and at timing t, 09, the other switching control human power N5 reaches the "high level", at timing t+10, N6 becomes "high" in synchronization with N2. N6 is applied to clocked NAND gate 118 and clocked NAND gate 119 via clocked NAND gate 113. Output N of clocked NAND gate 118
7, the control human power 123 is at the "high" level and is already "high." Since it is a level, it does not change. On the other hand, the output N8 of the NAND gate 119 controlled by the clock becomes the "high" level at timing tll1 in synchronization with Ml, and the output N + of the NAND gate 1-114. Ha “Lo” Rehe/L= Tofz Le. When the output signal NIO reaches the "low" level, Ne reaches the "high" level at the timing t I when N2 becomes the "high" level. At this timing, Ne reaches the "hyper level". NHIF warehouse A becomes 'ν;゛・-゛ level, and the output of the trust selection circuit old) J19 is changed to N2 or C, Ne・＼ t); I. Timing t111 or C), tl, 2. 191 minutes [, Nq, N
Both eo are "low" rebeno l-(al), NAND game)
The outputs of 116 and 116 become [both ``...Iparebeno'', and N and 1 become ``low'' level I31. At timing t1.2, from N2 to N1-\switching') 11.'
1, N+il'''l'J-'' level, N,) is
II,, -11, Beno 1 is output twice in succession. This i+ is 1:,! ! , similarly, when looking at the input 122 of the A counter 101 as a reference, the result is a 1 pass/l pass, and an extra 1 count is counted. Timing t10. Then, when the switching control input) Jl becomes the 1' low level, the output N6 of the same 1g1 circuit is at the timing t.
At 114, the same 1υ) is applied to N2, resulting in a low level. y
Perform 4o frequency division. 1-7 or [-7, 1-1 small, etc., Ne. Each time you switch to N2, there is one pulse, S/L-, so
When switching is performed in row 4 and 2-C, the frequency is divided by 1/41, thereby performing coefficient switching of 140 and 1'41. Next (' (high) 1' d wave operation (at -), ・); bell. The timing at which the output N5 of the 1/i 0 counter changes is the same as the timing at which the output N5 of the 1/i 0 counter becomes the "roll bell" of N2, and the timing at which the output N5 of the 1/i 0 counter changes.
1, the output of the clock-controlled controller 112 is high
The value will be in the middle of the level. At this time 1, impark 1
07. Amplify with 106, °゛high°°−1, “′
Any value of the low level level (, 1) is set to 111, which is controlled by the clock to C2, and synchronized at N1, and 110 is set to ,1
``1, N6'\output 7 through the input 104
'do. . In other words, regardless of the position of N5 and N2 and Jl, you can obtain the switching control reliability you have determined.Furthermore, internally, Nl, N2, IJ knock,
In the conventional example (1), it is possible to synchronize without creating an H extension, and to reduce the negative C11 of the NAND game 1-114, thereby achieving high-speed operation. ). Figure 8 shows the circuit of this example.
Frequency characteristics when configured with a circuit 'fr/Jk. The signal selection circuit of the present invention has a Q as described above and operates well even at high frequencies. Effects of the Invention According to the present invention, the phase difference between the switched signal and the control signal can be reduced: #
Even at frequencies where 1 is high, it is possible to obtain good characteristics without malfunction by using a relatively slow device such as a CMOS device, and it is especially suitable for integrated circuits. A selective IK circuit can be provided.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a conventional example, FIG. 2, FIG. 3, and FIG. 4 are timing charts of a conventional example. FIG. 6 is a frequency characteristic of a conventional example. FIG. 6 is an example of an embodiment. FIG. 7 is a timing diagram of the embodiment. Figure 8 shows the frequency characteristics of the embodiment.
D gate, 121 synchronous circuit. Name of agent tr Rito Toshi Nakao Male and 1 other person Figure 1 Figure 2 tlGz 03 'c4 T3 T? Figure 3 1 et6 Figure 4 9 Figure 5

Claims (1)

[Claims] Two types of HAND gates having mutually opposite phases are applied, first, second, third and fourth HAND gates, a selector, and first and second input terminals.・(-Yuto, synchronous circuit,
1st. A second control input terminal is provided to input the control input of "-glycoside 1" to the first input terminal (-(-ta) and "disaccharide 1").
The output of the 1-glycoside 1 inverter is connected to the second NAND gate, the output of the first NAND gate is connected to the third ONAND gate, and the second The output of the NAND gate is connected to the fourth NA
ND gate, and the output of the fourth NAND gate,
the second inverter and the third NAND gate;
The output of the second inverter is connected to one control input of the selector, and the output of the second inverter is connected to the other control input of the selector. Connect the input terminal of , and the second control input terminal of ! 6 [[Input to the same 191 circuit, synchronize with upper pressure distribution even if the pulse is of opposite phase -), l-circulation Ju
The output of one circuit is connected to the 1st and 2nd NAND gates of l-8[: 2nd. The output of the third NAND gate is controlled by one side of the pulse of reverse phase, and the output of the second inverter is controlled by the other side of the pulse of reverse phase. A signal selection circuit characterized by 1.