JPS60256199A - Voice synthesizer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to speech control of a speech synthesizer, and particularly relates to a technique for selecting and controlling one-time speech or continuous speech.

[Prior art]

It has become common practice to synthesize speech and use it for various services. Since speech synthesis equipment deals with natural language, it must be realized by a complex combination of various circuits, but the cost of the equipment can be reduced significantly through higher integration of IC memory and the development of LSIs for speech synthesis. This has made it possible to apply it to a wide range of fields.For example, it has come to be used for transfer notifications by telephone and balance checking by automatic deposit/withdrawal machines. It is also important to have a technology for selecting and controlling single utterances or continuous utterances, and an example of this type of circuit is the utterance start signal generating circuit shown in FIG.

This circuit consists of a NOR circuit 5 whose input terminals are connected to the input terminals 1, 2.3 of the word selection input signal, and whose input signal is the output signal of a NOR circuit 4, and an inverter circuit which inverts the output of a delay circuit 6. According to I, a NAND circuit 'N18 uses the output signal of the NOR circuit 5 as one input signal and its inverted signal as the other input signal, and the output signal of the NAND circuit 8 is used for speech synthesis (not shown). It consists of an output terminal 10 which is supplied as a voice start signal or a start signal of the LSI, and an input terminal 11 to which a signal indicating the state of a voice synthesis LSI (not shown), that is, a busy number 16 is applied. The busy signal is the other input signal of the NOR circuit 5. Therefore,
The operation will be explained with reference also to the time chart of FIG. 5 showing signal waveforms of each part of this generating circuit. Figure 5 (
, ) indicates a word selection input signal for either input terminal 1, 2.3, (b) indicates a busy signal for input terminal 11, and (C) indicates a star) for output terminal 12. In addition, logical symbol 11〃,
'OI corresponds to high level and low level voltages, respectively. First, if the word selection input signals are all 0, the input signal to one of the NOR circuits 4 and 5 is 11N, but since the speech synthesis LSI (not shown) is on standby, the NOR circuit 5 is The other input signal becomes this busy signal "0", so the output signal of the NOR circuit 5 becomes XX0I, which becomes one input signal of the NAND circuit 8. Also, the output signal of the NOR circuit 5 becomes After being delayed by the delay circuit 6 for a predetermined time, the other input signal 11 is supplied to the NAND circuit 8 via the inverter 7. Therefore, the output '4' of the NAND circuit 8 is inverted by the inverter circuit 9. In this state, any word selection input signal becomes the start signal 10'.
Then, one input signal of NOR circuit 5 becomes %Of due to NOR circuit 4, but the other input signal, that is, the busy signal, remains %0#, so the output signal of NOR circuit 5 becomes %1. becomes one input signal of the NAND circuit 8, but at this time, since the other input signal remains as %Ql, the output signal of the NAND circuit 8 becomes %Ql, and the output terminal 1
0 starting month - 1 is obtained. However, the output signal bundle 1 of the NOR circuit 5 is delayed for a predetermined time in the delay circuit 6, and then is passed through the inverter 7 to the other input signal 1 of the NAND circuit 8.
0, the output signal of the NAND circuit becomes 1, and the start signal at the output terminal 10 becomes 10'. That is, the start signal becomes a pulse signal. Then, in response to the start signal '1', the speech synthesis LSI (not shown) starts synthesis, sets the busy signal to %11, becomes the input signal Jl of the other output of the NOR circuit 5, and its output signal is NO. becomes. Therefore, regardless of one input signal of the NOR circuit 5, generation of the start signal is prohibited, and the output signal of the inverter 7 is set to "1" to generate the next start signal.Next, When the utterance is finished and the busy signal becomes OI, the initial state is returned and the word selection input signal can be read. Therefore, the word input signal is generated for a time longer than one generation time - 1. If so, it will occur along with it.

However, it is easy to control the speech synthesis device using a so-called microcomputer and to control whether it is uttered once or continuously on a word-by-phrase basis, but if a microcomputer is not used, There were problems such as the need for a complicated control circuit to change the voice mode on a unit-by-unit basis.

[Summary of the invention]

The present invention provides means for outputting a voice start signal by selecting an edge of a word selection input signal, a means for outputting a voice start signal again at the end signal of voice, and a voice mode selection circuit. The present invention provides a speech synthesis device that can select whether to make a single utterance or to make continuous utterances.

[Embodiments of the Invention] Now, embodiments of the invention will be described with reference to the drawings. Note that elements common to each drawing are given the same reference numerals.

FIG. 1 is a block diagram showing one embodiment of the present invention. A voice mode selection circuit 12, an AND circuit 13, and a NAND circuit 14 are added to the block diagram of the conventional example shown in FIG. That is, the utterance mode selection circuit 12 selects whether to utter one utterance or to utter continuously in units of uttered words.
, 2.3 are input as one input signal of the AND circuit 13, so eight types of words can be selected.

However, since the presence or absence of the word selection input signal is detected by the NOR circuit 4, seven types of words are selected. Note that this selection circuit 12 selects 11 in the case of consecutive occurrences.
', and in the case of only one utterance, outputs '0', which can be easily realized with a decoder circuit. The other input signal of the NAND circuit 13 is input terminal 1
1, and its output signal is the other input signal of the NOR circuit 5. The NOR circuit 14 has one input signal as the output signal of the NAND circuit 8, and the other input signal as the busy signal applied to the input terminal 11.
The output signal is supplied to the output terminal 10 as a start signal. Figures 2 and 3 are time charts showing signal waveforms at each part of the block diagram shown in Figure 1. In each figure, (
a) is a word selection input signal from input terminal 1, 2.
1'3, (b) shows the busy signal of the input terminal 11, and (C) shows the start signal of the output terminal 10. Next, the operation will be explained.

First, the case of continuous vocalization, that is, the case where the output signal of the vocalization mode selection circuit 12 is 11 will be described. When the voice synthesis LSI (not shown) is on standby, the busy signal is 10.
Therefore, the output signal of the AND circuit 13 becomes OI, and the word selection input signal is in a state where it can be put to sleep. Therefore, when the input signal becomes 11 at any one of the input terminals 1, 2.3, the output signal of the NOR circuit 4 Fit
Therefore, the output signal -1 of the NOR circuit 5 becomes one input signal "1" of the NAND circuit 8. The other input signal of the NAND circuit 8 remains %1 at this time. Therefore, the output signal XXO// becomes one input signal '0'' of the NOR circuit 14. Input terminal 11 busy signal turtle 0
is the other input signal 10'' of the NOR circuit 14, so its output signal %II is supplied to the output terminal 10 as the start signal 11.Then, the output signal %II of the NOR circuit 5 is the other input signal 10'' of the NOR circuit 14. After being delayed for a predetermined time in step 6, it is supplied to the NAND circuit 8 as the other input signal 'a □ // through the inverter 7. Therefore, the output signal IA 1 // of the NAND circuit 8 becomes On the other hand, the input signal 11N and the start signal 10' of the output terminal 10 are supplied, and a pulse-like start signal is generated.

Due to this start signal, the speech synthesis LSI (not shown) enters the voice generation state, the busy signal becomes "1", the output signal of the AND circuit 14 becomes 11N, and the output signal of the NOR circuit 5 becomes "0". 〃and the output signal of the inverter 7 becomes 11
Say N and prepare for the next utterance. Therefore, if the word selection input signal remains at 111 for longer than the utterance time, the words will be uttered continuously. This operation is illustrated in FIG.

Next, the case where the voice is uttered only once, that is, the case where the output signal of the utterance mode selection circuit 12 is -0'' will be explained.

In this case, one input signal of the AND circuit 13 is '0〃
Therefore, immediately after the other input signal, the busy signal of the input terminal 11, the output signal 10 becomes the Noah's 1 path 5.
becomes the other input signal '&0〃. Therefore, when the input signal becomes 1 at any one of the input terminals 1, 2 and 3, the start signal of the output terminal 1o becomes a pulse of 11 only once, in the same manner as described above. As long as one input signal of the NOR circuit 5 is "Ig", the output signal of the inverter 7 is "O". Therefore, in order to make the voice sound again, set all the word selection input signals of input terminals 1, 2, and 3 to -[1'0' and set the output signal of inverter I to V″1″.
Then, the input signal of any one of the input terminals 1°2.3 may be set to 11/'. This operation is illustrated in FIG.

〔Effect of the invention〕

According to this invention, by simply adding a few simple circuits in addition to the voice mode selection circuit, it is possible to easily select between one utterance and continuous utterance for each uttered phrase, so that the speech synthesis device The configuration can be simplified, and therefore, a speech synthesis system using the speech synthesis device can be constructed at low cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG.
FIG. 3 is a time chart showing signal waveforms at each part of this block diagram, FIG. 4 is a block diagram showing a conventional example, and FIG. 5 is a time chart showing signal waveforms at each part of this block diagram. 1.2,3,11...input terminal, 4,5°14...
・・NOR circuit, 6・・Delay delay circuit, T, 9・・・Inverter, 8・・・NAND circuit, 10・・Output terminal, 12・・Voice mode selection circuit, 13・・・◆AND circuit. Agent: Masuo Oiwa (11) Procedural amendment (spontaneous) October 1980, A3[1 Director of the Japan Patent Office 3, Relationship with the case of the person making the amendment Patent applicant address: Tokyo, f. f11 Ward Marunouchi-chome 2-3 Name (601) Mitsubishi Electric Co., Ltd. Representative piece 111 Jin 8 Part 4 Column 6 for detailed explanation of the invention in the agent's specification, Contents of amendment (1) Specification No. On page 3, line 18, change terminal 121 to “terminal 1”
0”. '°'], Book 5, Epistle 5, page 4, is added. 1 Noah circuit 1 for "Nand circuit 14" on page 6, line 19
4”. that's all

Claims (4)

[Claims] (1) In a speech synthesis device that changes the voicing mode in units of ffg phrases, means for outputting a voicing start signal by capturing the edge of the word selection input signal in response to a word selection input that lasts longer than the utterance time; A speech synthesis device comprising means for outputting a voice start signal again in response to an end signal, and selection means for selecting both of these means. (2) The speech synthesis device according to claim 1, which uses a monostable circuit as means for capturing the edges of the word selection input signal. (3) As a means for outputting the utterance start signal again, an AND circuit is used which inputs the utterance end signal to the monostable circuit if the word selection input signal continues, and the speech synthesis according to claim 1 of the fC patent is used. Device. (4) The speech synthesis device according to claim 1, wherein the selection means inputs the word selection input signal to the utterance mode selection circuit.