JPS59208626A - Interface circuit of sound generator - Google Patents

Abstract

PURPOSE:To obtain a sound generator interface circuit preventing a CPU from beig waited for a long period by holding external data during the writing of data. CONSTITUTION:A terminal CE of a sound generator detects the output of an AND circuit 5 and a terminal READY detects a negative edge of the signal CE and is turned to the low level for an optional period. When data input to a terminal Dt has been completed, the terminal Dt is turned to the high level. When a write-enabled signal WE is the low level, a data group DBy inputted to the terminal Dt is made effective. A latch circuit 7 inputs the chip enabled signal sion CE to a terminal ENABLE as a control signal and sends the data group DBy of the CPU1 to the terminal Dt of the sound generator 8. When the terminal ENABLE is in the high level, the input and output of the latch circuit 7 are the same level, and when in the low level, an input level kept before turning to the low level is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sound generator interface circuit for coupling a central processing unit and a sound generator.

Conventionally, this type of interface circuit cannot hold all external data while data is being written in an interface with a central processing unit (hereinafter referred to as CPU) that is synchronized with a CPU, and the CPU characteristic is that it is in a wait state for a long time. There was a drawback that

SUMMARY OF THE INVENTION An object of the present invention is to provide a sound generator interface circuit which eliminates the above-mentioned drawbacks, can hold external data while data is being written, and does not leave the CPU in a wait state for a long time.

The sound generator/interface circuit of the present invention outputs the sound from the central processing unit.

a first OR circuit that receives a request signal and a write strobe signal; a low-level pulse width reduction circuit that receives the output of the first OR circuit and outputs a write signal; and an address output from the central processing unit. An address decoder that decodes the group signal all-input binding address; a second OR circuit that ORs the output of the address decoder and the output of the low level pulse width reduction circuit; An AND circuit inputs the output of the second OR circuit as an input and inputs the logical product of both to the chip enable terminal of the sound generator, and a data group signal output from the central processing unit is manually input. A latch circuit that inputs the output of the AND circuit as a control signal and outputs a data group signal to the sound generator, and wiring that connects the central processing unit C1 to a clock input terminal of the sound generator. be done.

Next, embodiments of the present invention will be described using the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

This embodiment includes a first OR circuit 2 which receives all inputs of the ■10 request signal outputted from the CPU (central processing unit 1) and a write strobe signal WR, and a field of this first OR circuit 2. A low level signal that inputs power and outputs a 10W write signal.
A pulse width m, J1 times u3, an address decoder 6 that manually decodes addresses using the address group signal ABx output from the CPUI, an output (negative select signal) AB of this address decoder 6, and a low level pulse width reduction circuit. The second OR circuit 4 takes the logical interest with the output of 3 (write signal l0W), and the ready signal of the sound generator 8 is manually combined with the output of the second OR circuit 4 IOW+AB
The logic &' of both is inputted to the chip enable terminal CE of the sound generator 8 as an input of 't-other'. AND circuit 5 and data group signal D output from CPUI
A latch circuit 7 inputs the output of the AND circuit 5 as a control signal to an enable terminal and outputs a data group signal to the sound generator 8, and a latch circuit 7 that inputs the output of the AND circuit 5 as a control signal and outputs a data group signal to the sound generator 8;
and wiring to connect to.

Next, the operation of this embodiment will be explained.

FIG. 2 is a timing diagram of the operation of the embodiment shown in FIG.

A clock φ is sent from the CPUI to a terminal φSG of the sound generator 8. ■/ from CPUI.

When the awn is filled, the first OR circuit 2 calculates the logical sum of the two.

The pulse width of this OR is reduced by the low level pulse width reduction circuit 3 and outputted as a write signal IOW.

The address group signal ABx from the CPUI is decoded by the address decoder 6 and output as a negative select signal AB. The second OR circuit 4 is a low level pulse width reduction circuit 3
The logical sum IOW+ABt of the output IOW of the address decoder 6 and the output AB of the address decoder 6 is inputted to one input terminal of the AND circuit 5. The AND circuit 5 outputs the output READY/WE' from the ready terminal of the sound generator 8 as the other input as their AND chip enable signal CE, and inputs this output to the terminal CE of all the sound generators 8 and the latch circuit. It is also input to the terminal ENABLE of 7. The terminal CE of the sound generator detects the signal CE, the terminal READY detects all the negative edges of the signal CE, becomes low level for an arbitrary time, and becomes high level when data input to the terminal Dt is completed. When the write enable signal WE is at a low level, the data group DBy input to the terminal Dt becomes valid. The latch circuit 7 inputs the chip enable terminal CE from the AND circuit 5 as a control signal to the terminal ENABLE, and inputs the data group DBy of the CPUI.
'i Send to the terminal Dt of the sound generator 8. In the launch circuit 7, when the terminal ENABLE is at a high level, the human power and the output are at the same level, and when the terminal is low t/bell, the human power level before changing to the low level is outputted.

As described above, external data can be held while data is being written by the CPU synchronized with the clock φ. As a result, all normal data can be supplied to the sound generator, and since a fresh signal cannot be output when the CPU is in a wait state, it is possible to prevent the CPU from being in a wait state for a long time.

As explained in detail above, according to the present invention, all external data can be held while data is being written in the CE'U, which is synchronized with the clock, so normal data can be supplied to the sound generator. This is highly effective because it provides a sound generator interface circuit in which the CPU does not stay in a wait state for a long time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a timing diagram of the operation of the embodiment shown in the figure. 1...
...CPU (Central Processing Unit), 2...First OR circuit, 3...Low level pulse width reduction circuit, 4
...Second OR circuit, 5...AND circuit,
6...address decoder, 7...latch circuit, 8...sound generator. ＃IQJ

Claims (1)

[Claims] A first OR circuit that inputs an I/Q request signal output from the central processing unit and a write signal, and a low level circuit that inputs the output of the first OR circuit and outputs a write signal. a pulse width reduction circuit, an address decoder that receives an address group signal input from the central processing unit and decodes the address, and a logical sum of the output of the address decoder and the output of the low-level pulse width reduction circuit; and an AND circuit which takes the ready signal of the sound generator as one input, takes the output of the second OR circuit as the other input, and inputs the logical product of both to the chip enable terminal of the sound generator. , a latch circuit that manually inputs the data group signal output from the central processing unit, inputs the AND circuit as a control signal, and outputs all the data group signals to the sound generator; A sound generator interface circuit comprising: wiring connected to a clock input terminal of a sound generator.