JPS57191749A - Data transfer controller - Google Patents

Data transfer controller

Info

Publication number
JPS57191749A
JPS57191749A JP7496881A JP7496881A JPS57191749A JP S57191749 A JPS57191749 A JP S57191749A JP 7496881 A JP7496881 A JP 7496881A JP 7496881 A JP7496881 A JP 7496881A JP S57191749 A JPS57191749 A JP S57191749A
Authority
JP
Japan
Prior art keywords
register
signal
output
data
data transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7496881A
Other languages
Japanese (ja)
Inventor
Toshiyuki Okamori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7496881A priority Critical patent/JPS57191749A/en
Publication of JPS57191749A publication Critical patent/JPS57191749A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/4226—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To make the data transfer sure, by providing a register, which accepts input data independently of presence or absence of untransferred data, in the precedong stage. CONSTITUTION:The first register 4 which accepts input data and the second register 11 to which the output of the first register 4 is inputted are provided. When a request signal TRGIN2 becomes ''1'', data on a BUSIN3 is set to the register 4. Next, when an FF5 is ''0'', an AND gate 7 is opened, and an FF9 is set to ''1''. The output is returned as a signal TAGOUT10 corresponding to a signal TAGIN. Simultaneously, the signal 10 energizes the register 11, and the output of the register 4 is set to the register 11.
JP7496881A 1981-05-20 1981-05-20 Data transfer controller Pending JPS57191749A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7496881A JPS57191749A (en) 1981-05-20 1981-05-20 Data transfer controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7496881A JPS57191749A (en) 1981-05-20 1981-05-20 Data transfer controller

Publications (1)

Publication Number Publication Date
JPS57191749A true JPS57191749A (en) 1982-11-25

Family

ID=13562596

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7496881A Pending JPS57191749A (en) 1981-05-20 1981-05-20 Data transfer controller

Country Status (1)

Country Link
JP (1) JPS57191749A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59208626A (en) * 1983-05-12 1984-11-27 Nec Corp Interface circuit of sound generator
JPS63204355A (en) * 1987-02-18 1988-08-24 Mitsubishi Electric Corp Data transfer control circuit
US6978391B2 (en) 2000-11-01 2005-12-20 Nec Electronics Corporation Asynchronous bus interface circuit, method of controlling the circuit, microcomputer, and device controlling method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59208626A (en) * 1983-05-12 1984-11-27 Nec Corp Interface circuit of sound generator
JPS63204355A (en) * 1987-02-18 1988-08-24 Mitsubishi Electric Corp Data transfer control circuit
US6978391B2 (en) 2000-11-01 2005-12-20 Nec Electronics Corporation Asynchronous bus interface circuit, method of controlling the circuit, microcomputer, and device controlling method

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