JPS60254249A - False fault generating system - Google Patents

Abstract

PURPOSE:To suppress the increase of hardware and also to generate an error with the designated timing by providing a false fault register, an execution instruction counting part, a cycle counting part and then an error status register respectively. CONSTITUTION:The output of a false fault contents register 1 is supplied to an error status register 5 via AND gates 511-51n. The outputs of an execution instruction counting part 3 and a cycle counting part 4 are supplied to the register 5 via an AND gate 43 and gates 511-51n. Then the output of the register 5 is supplied to an error processing part 6 via an OR gate 61.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a pseudo-failure generating force formula, and more particularly to means for checking an error processing mechanism when an error is detected in a data processing device.

DESCRIPTION OF THE PRIOR ART Conventionally, as this type of pseudo-fault generation force formula, there is a "data processing device" as described in, for example, Japanese Patent Publication No. 12776/1983. The invention disclosed in the publication is a means for specifying an arbitrary FliIFF of an error indicator flip-flop (hereinafter referred to as 13IFF) provided in each unit in a data processing device and turning this n on to 1. This method generates a pseudo-failure by setting the specified EIPF' to 1 and turning it on at a time specified by the program.

However, this method has the disadvantage that the hardware increases because of the means to directly turn on the EIFF, and because the timing of pseudo-failure occurrence is unrelated to program control, it is difficult to execute the targeted instruction. The drawback was that pseudo-failures were less likely to occur during cycles.

OBJECTS OF THE INVENTION The present invention has been made in order to eliminate the above-mentioned drawbacks inherent in the conventional technology, and therefore, an object of the present invention is to provide an error registration mechanism in a data processing device and to process inputs from a plurality of EIFFs. Perform a logical OR with 1 bit of the error registration mechanism,
Set the bit that displays the error content in the error registration mechanism to 1.
The present invention aims to provide a new pseudo-fault generation force formula that can suppress an increase in the amount of hardware by providing a pseudo-fault content registration means that turns on the pseudo-fault content.

Further, the present invention has been made by focusing on the point that the data processing device is controlled by a plurality of instructions, and the execution of the instruction 1d is controlled by one or more machine cycles.Therefore, another object of the present invention is to: A new pseudo-fault generating ability that makes it easy to specify a machine cycle by generating a pseudo-fault when executing a specified number of machine cycles in the next instruction after executing a specified number of instructions. The goal is to provide a formula.

Structure of the Invention In order to achieve the above object, a data processing device according to the present invention includes an error registration mechanism that centralizes and registers detected errors, and an error processing system that executes error processing in response to a signal from the error registration mechanism. and a pseudo-fault content registration means that turns on a specified bit in the error registration mechanism at the time of execution of a specified n-th cycle in the next instruction after execution of a specified number of instructions. Consisting of:
The feature is to make it possible for specified pseudo failure contents to occur in a pseudo manner at a specified timing.

3. Detailed Description of the Invention Below, a preferred embodiment of the present invention will be specifically described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, reference number 1 indicates a pseudo-fault content registration register, and the output of the pseudo-fault content registration register 1 is input to the error status register 5 via logical products 511 to 51n. Further, the outputs of the executed instruction count section 3 and the cycle count section 4 are inputted to the error status register 5 via the AND gate 43 and AND gates 511 to 51n. Further, the output of the error status register 5 is inputted to the error processing section 6 via a logical sum 61.

3- Next, the operation of the present invention will be explained with reference to the drawings. Now, a case will be described in which a pseudo fault is generated at the start point of cycle C14 in the instruction Is in the pseudo fault insertion instruction 0 shown in FIG.

When the pseudo-fault insertion instruction IO shown in FIG. 2 is executed, the number of instructions "'l" up to the content of the pseudo-fault is input to the instruction execution counter 3 via the signal line 311 of FIG. 1, and the number of execution cycles is "4". is input to the cycle counting unit 4 via the signal line 423, and the simulated fault content is registered in the simulated fault content registration register 1. Furthermore, ENABLI shown in FIG.
! 3 signals to 1 on” (J), the ENA
Since the signal w (not shown) for transmitting the BLE signal is connected to the decoder 11, the instruction execution counting section 8, and the cycle counting section 4 in FIG. 1, the decoder 11. The instruction execution counting section 3 and cycle counting section 4 become operational.

Next, the instruction execution unit 2 of FIG. 1 executes the normal instruction I shown in FIG.
When I is executed, at the end of cycle CI+1, the output of the signal line 322 in FIG. It is subtracted to ``@0'' by the subtracter 31, and the value 10'' is input to the instruction execution counter 3 via the signal line 321 and the AND gate 32.After this, the instruction When the execution starts and the execution of cycle C starts, the output of the cycle start signal line 422 in FIG. Since the logic 11" is output to 421, the output of the cycle count section 4 is connected to the signal line 425 and @l.
``13'' is input to the cycle count section 4 through the subtractor 41 and the AND gate 42. After the execution of cycle C111 in FIG. The value of the cycle count section 4 in FIG. 1 is 12". Furthermore, the cycle Cms in FIG.
At the start of execution, the price of cycle count section 4 in Figure 1 is
At the start of cycle 014 in FIG. 2, the value of the cycle count section in FIG. 1 becomes 11O''.

Execution instruction count unit 3 and cycle count unit 4 in FIG.
The value of signal lines 312 and 424 becomes "+".
The output is a logic 1 bit, AND gate 43 and signal line 4
Logic "l" is inputted to logical products 511 to 51n through 31. - F. The output of the pseudo-fault content registration register l is decoded by the decoder 11, and the signal line 11 is decoded by the decoder 11.
1-11n (logical product)) 511-51n are manually operated. The outputs of the logical product darts 511 to 51n are input to the error status register 5 via the logical product darts 531 to 53n.

FliIFF, which is the output of the OR gates 521 to 52n, is input here, and the output of the OR gates 521 to 52n is input to the OR gate 5.
31 to 53n, the contents of the simulated fault content registration register 1 can simulate a fault at the east end.

The output of the error status register 5 is the OR gate 61
If at least one of the bits Fix to En is set to 1", that is, a pseudo-fault setting is made, the output of the bit 61 becomes "1", and the error processing unit 6 The error processing unit 6 is activated. The error processing section 6 reads bits El-En, which are the contents of the error status register 5, via the signal line 611, analyzes which bit among the bits El-En is 1 on, and performs error processing.

Also, when the output of the AND gate 43 becomes logic "'l", by turning off the ENABLE signal line (not shown) to the execution instruction count section 3 and cycle count section 4, the next Until the pseudo-fault insertion instruction is executed,
By suppressing the occurrence of pseudo-faults, it is possible to prevent disturbance to instruction execution after the occurrence of pseudo-faults.

Effects of the Invention As explained above, the present invention provides a pseudo-fault registration register, an executed instruction count section, a cycle count section, and an error status register, thereby suppressing the increase in -m-ware and making it possible to specify The effect is that a specified error can be generated at the timing of.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
The figure shows the operation sequence of instructions. , 5...Error status register, 6.
Φ・Error processing unit, ll...decoder, 31, 41・
・9 subtractor, 32.42.43.511~51n @
@11 AND gate, 521~52n, 531~5
3n%61 @ @ @OR gate, 111~lln
, all, 312.313.321, 322.42
1, 422.423.424.425.431...
Signal line patent applicant NEC Corporation Representative Patent attorney Yutabe Kumagai 8 -

Claims (1)

[Claims] A data processing device equipped with an error registration mechanism that centralizes and registers errors detected within the data processing device, and an error processing mechanism that performs predetermined error processing in response to a signal from the error registration mechanism. A pseudo-fault content registration means is provided that turns on a specified bit in the error registration mechanism upon execution of a specified number of cycles in the next instruction after the execution of the specified number of instructions. A pseudo-fault generation force formula 0 characterized by making the fault content pseudo-possible.