JPS60253256A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60253256A JPS60253256A JP10850784A JP10850784A JPS60253256A JP S60253256 A JPS60253256 A JP S60253256A JP 10850784 A JP10850784 A JP 10850784A JP 10850784 A JP10850784 A JP 10850784A JP S60253256 A JPS60253256 A JP S60253256A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor region
- semiconductor
- type
- epitaxial layer
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000009792 diffusion process Methods 0.000 abstract description 12
- 238000000034 method Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 4
- 230000008961 swelling Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000002730 additional effect Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
- H01L27/075—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. lateral bipolar transistor, and vertical bipolar transistor and resistor
- H01L27/0755—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
- H01L27/0777—Vertical bipolar transistor in combination with capacitors only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
- Electronic Switches (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体チップ上に集積回路を形成した半導体装
置に係り、特に外部から印加される静電電荷の放電回路
を備えた半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device in which an integrated circuit is formed on a semiconductor chip, and more particularly to a semiconductor device provided with a discharge circuit for electrostatic charge applied from the outside.
集積回路を有する半導体装置では外部から印加される静
電電荷により内部回路が静電破壊される恐れがある。こ
れを防止するために半導体チップの外部と接続される電
極に放電回路を接続することが行われる。例えば、第１
２図に示す如くダイオード１０のカソードを入力電極１
２に接続し、その７ノードを接地することによって静電
電荷の（２）
放電回路を形成するかあるいは第１３図に示す如＜ＮＰ
Ｎ ）ランジスタ１４のコレクタを入力電極１６に接続
し、そのエミッタを接地することによって放電回路を形
成していた。In a semiconductor device having an integrated circuit, internal circuitry may be damaged by electrostatic charge due to electrostatic charges applied from the outside. In order to prevent this, a discharge circuit is connected to an electrode connected to the outside of the semiconductor chip. For example, the first
As shown in Figure 2, the cathode of the diode 10 is connected to the input electrode 1.
2 and ground its 7 nodes to form a (2) discharge circuit for electrostatic charge, or as shown in FIG.
N) A discharge circuit was formed by connecting the collector of the transistor 14 to the input electrode 16 and grounding its emitter.
しかしながら、第１２図の如くダイオードを逆方向接続
した放電回路によると、負の電荷に対しては有効である
が正の電荷に対しては放電を行うことができず全く無防
備となる。第１３図のようにトランジスタを接続すると
正の電荷も負の電荷も放電可能となるが、このような放
電を行うためのトランジスタは、多大の面積を必要とし
、レイアウトを行う上で有効な領域を広く使用しなけれ
ばならないという不都合がある。However, a discharge circuit in which diodes are connected in the reverse direction as shown in FIG. 12 is effective against negative charges, but cannot discharge against positive charges and is completely defenseless. When transistors are connected as shown in Figure 13, it is possible to discharge both positive and negative charges, but the transistors for this kind of discharge require a large area, and the effective area for layout is limited. The disadvantage is that it has to be widely used.
従って本発明の特徴とするところは、外部と接続される
電極と、該電極に接続される第１半導体領域と、前記電
極の周辺に形成され前記第１半導体領域とＰＮ接合する
第２半導体領域と、該第２半導体領域の電位を最高電位
に持ち上げる正電位（３）
供給手段と、半導体基板とを備え、前記第２半導体領域
と半導体基板との間に容量を生じせしめることにある。Therefore, the present invention is characterized by an electrode connected to the outside, a first semiconductor region connected to the electrode, and a second semiconductor region formed around the electrode and making a PN junction with the first semiconductor region. , a positive potential (3) supply means for raising the potential of the second semiconductor region to the highest potential, and a semiconductor substrate, and a capacitance is generated between the second semiconductor region and the semiconductor substrate.
第１半導体領域と第２半導体領域とがＰＮ接合され、第
２半導体領域と半導体基板との間に容量が持たせられて
いるから、電極から印加される静電電荷はＰＮ接合ダイ
オードを介して容量放電される。また、第２半導体領域
は電極周辺に形成されており、一般にこの領域は空き領
域が設けられているのでその空き領域を利用することが
できる。Since the first semiconductor region and the second semiconductor region are in a PN junction and a capacitance is provided between the second semiconductor region and the semiconductor substrate, the electrostatic charge applied from the electrode is transferred via the PN junction diode. Capacity is discharged. Further, the second semiconductor region is formed around the electrode, and since this region generally has an empty area, the empty area can be utilized.
さらに、第２半導体領域が最高電位に持ち上げられてい
るため、入力側からは上述の容量が見えないこととなる
。Furthermore, since the second semiconductor region is raised to the highest potential, the above-mentioned capacitance is not visible from the input side.
第１図は本発明の一実施例として半導体装置の一部の構
造を表わす断面図である。同図において、１８はグラン
ド２０上に載置されているＰ形基板、２２はＰ形基板２
０上に拡散せしめられたＮ１の埋込層、２４はその上に
形成されたＮ形エピタキ（４）
シャル層である。このＮ形エピタキシャル層２４は、第
２図の平面図に示すように外部と接続される入力電極の
パッド２６の周辺に必然的（即ちボンディング線との余
裕を設けるため）に設けられる空き領域を利用して形成
される。FIG. 1 is a sectional view showing the structure of a part of a semiconductor device as an embodiment of the present invention. In the figure, 18 is a P-type substrate placed on the ground 20, and 22 is a P-type substrate 2.
24 is an N-type epitaxial layer formed thereon. As shown in the plan view of FIG. 2, this N-type epitaxial layer 24 has an empty area that is inevitably provided around the pad 26 of the input electrode connected to the outside (that is, to provide a margin with the bonding line). formed by using
Ｎｌエピタキシャル層２４の一部にはＰ膨拡散層２８が
設けられ、このＮ形エピタキシャル層２４とＰ膨拡散層
２８とはＰＮ接合している。Ｐ膨拡散層２８は電極３０
を介してパッド２６に接続されている。また、Ｎ形エピ
タキシャル層２４の一部にはこれとオーム性接触するＮ
形層３２が設けられ、このＮ形層３２は電極３４を介し
て正の電圧源ＶＣＣに接続されている。従ってＮ形エピ
タキシャル層２４がこの半導体装置で用いられる最高電
位に持ち上げられることとなる。A P swelling diffusion layer 28 is provided in a part of the Nl epitaxial layer 24, and the N type epitaxial layer 24 and the P swelling diffusion layer 28 are in a PN junction. The P swelling diffusion layer 28 is the electrode 30
It is connected to pad 26 via. Further, a portion of the N-type epitaxial layer 24 has an N
A type layer 32 is provided which is connected via an electrode 34 to a positive voltage source VCC. Therefore, the N-type epitaxial layer 24 is raised to the highest potential used in this semiconductor device.
第１図（第２図）の実施例を回路図で表わしたものが第
３図である。同図において、３６はＮ形エピタキシャル
層２４とＰ膨拡散層２８とによって形成されるＰＮ接合
ダイオード、３８はＮ形エピタキシャル層２４とＰ形基
板１８との間で形成（５）
される容量（より詳しくはＮ＋埋込層２２とＰ形基板１
８との接合容量）、４０は半導体装置の内部回路であり
、例えばアドレス入力等のゲートである。この容量３８
は、前述したようにＮ形エピタキシャル層２４が空き領
域を利用して大きな面積を確保できるため、非常に大き
な容量値とすることができる。一方、Ｎ形エピタキシャ
ル層２４が最高電位に持ち上げられるため、入力電極パ
ッド２６側からはダイオード３６でしゃ断されて大容量
が全く見えず、このダイオード３６の小容量Ｃｔのみが
見えるだけとなる。FIG. 3 is a circuit diagram showing the embodiment of FIG. 1 (FIG. 2). In the figure, 36 is a PN junction diode formed by the N-type epitaxial layer 24 and the P-type diffusion layer 28, and 38 is a capacitance (5) formed between the N-type epitaxial layer 24 and the P-type substrate 18. More specifically, the N+ buried layer 22 and the P type substrate 1
8), 40 is an internal circuit of the semiconductor device, and is, for example, a gate for address input. This capacity is 38
As described above, since the N-type epitaxial layer 24 can secure a large area by utilizing the empty area, a very large capacitance value can be achieved. On the other hand, since the N-type epitaxial layer 24 is raised to the highest potential, the large capacitance is not seen at all from the input electrode pad 26 side as it is cut off by the diode 36, and only the small capacitance Ct of this diode 36 is visible.
入力電極から正の静電電荷が印加されると、これはダイ
オード３６を介して容量３８に印加されて容量放電され
る。容量が非常に大きいので大きな電流を流すことがで
きる。When a positive electrostatic charge is applied from the input electrode, it is applied to the capacitor 38 via the diode 36 and is capacitively discharged. Since the capacitance is very large, a large amount of current can flow through it.
上述のように本実施例では、入力電極のパッドの周辺に
設けられている空き領域を利用してＰＮ接合ダイオード
の広大なカソード領域を形成し、そのカソード領域と基
板との間に生じる大容量によって放電を行わせているた
め、放電回路のため（６）
の特別な領域を占有することがなく、レイアウトが簡単
となって高密度化が可能となる。また、このカソード領
域を最高電位に持ち上げているため、入力電極側からの
容量特性が著しく悪化する恐れもない。しかも、Ｐ膨拡
散層２８及びＮ形層３２部分を設けるだけでよいので非
常に簡単に作成することができる。As described above, in this embodiment, the large cathode area of the PN junction diode is formed using the empty area provided around the pad of the input electrode, and the large capacitance generated between the cathode area and the substrate is Since the discharge is caused by the discharge circuit, the special area (6) is not occupied by the discharge circuit, and the layout becomes simple and high density is possible. Furthermore, since this cathode region is raised to the highest potential, there is no fear that the capacitance characteristics from the input electrode side will deteriorate significantly. Furthermore, since it is only necessary to provide the P-swelled diffusion layer 28 and the N-type layer 32, it can be produced very easily.
第４図は第１図の実施例の変更例である。この例では、
第１図のＮ形層３２の代りにＰ膨拡散層４２を設けてこ
こにＰＮ接合を形成し、第５図に示す如＜ＰＮ接合ダイ
オード４４を設けたものである。即ち、ダイオード３６
のカソード領域（Ｎ形エピタキシャル層２２）が正の電
圧源ＶＣＣに対してダイオード４４を介して接続されて
いる。これは、電圧源ＶＣＣより高い電圧の入力信号を
受ける場合に、これが電圧・源側に回り込んでしまうの
を防止するためである。本実施例のその他の構成及び作
用効果は第１図の場合と全く同じである。FIG. 4 is a modification of the embodiment shown in FIG. In this example,
A P expansion diffusion layer 42 is provided in place of the N type layer 32 in FIG. 1 to form a PN junction there, and a PN junction diode 44 is provided as shown in FIG. That is, the diode 36
The cathode region (N-type epitaxial layer 22) of is connected to the positive voltage source VCC via a diode 44. This is to prevent input signals of a voltage higher than the voltage source VCC from going around to the voltage/source side. The other configurations and effects of this embodiment are exactly the same as those in FIG. 1.
第６図は本発明のさらに他の実施例の断面図を示してい
る。この例では、Ｐ膨拡散層２８直下に（７）
Ｎ＋埋込層２２が形成されておらず、従ってＮ形エピタ
キシャル層２４とＰ形基板１８とがＰＮ接合しており、
Ｐ膨拡散層２８がエミッタ領域、Ｎ形エピタキシャル層
２４がベース領域、Ｐ形基板１８がコレクタ領域という
ＰＮＰトランジスタ４６ （第７図参照）が形成されて
いる。その他の構成は第１図の実施例と全く同じである
。FIG. 6 shows a cross-sectional view of yet another embodiment of the invention. In this example, the (7) N+ buried layer 22 is not formed directly under the P expansion diffusion layer 28, so the N type epitaxial layer 24 and the P type substrate 18 are in a PN junction.
A PNP transistor 46 (see FIG. 7) is formed in which the P-swelled diffusion layer 28 is an emitter region, the N-type epitaxial layer 24 is a base region, and the P-type substrate 18 is a collector region. The rest of the structure is exactly the same as the embodiment shown in FIG.
ベース領域は、前述の場合と同様にバンド２６周辺の空
き領域を利用して広い領域とし、Ｐ形基板１８との間に
意図的に大きな容量３８を持たせる。静電電荷が印加さ
れてこの容１３Ｂに電流が流れるとこれがトランジスタ
４６のベース電流となり、その電流増幅率β（ＰＮＰ）
倍の電流をこのトランジスタ４６を介してＰ形基板１８
に流すことができる。従って本実施例によれば、小さい
領域の容量でより大きい電流を放電させることができる
。本実施例のその他の作用効果は第１図の場合と同様で
ある。As in the case described above, the base region is made wide by utilizing the free space around the band 26, and a large capacitance 38 is intentionally provided between the base region and the P-type substrate 18. When an electrostatic charge is applied and a current flows through this capacitor 13B, this becomes the base current of the transistor 46, and its current amplification factor β (PNP)
A double current is passed through this transistor 46 to the P-type substrate 18.
can be passed to. Therefore, according to this embodiment, a larger current can be discharged with a smaller area of capacitance. The other effects of this embodiment are the same as those of FIG. 1.
第８図及び第９図に示す実施例は、第６図の実施例を第
４図の実施例の如く変更したもの即ち、（８）
ダイオード４４を電源に接続するようにしたものであり
、その付加的な作用効果は第４図の実施例の場合と全く
同様である。The embodiment shown in FIGS. 8 and 9 is a modification of the embodiment shown in FIG. 6 as in the embodiment shown in FIG. 4, that is, (8) the diode 44 is connected to the power supply, The additional effects are exactly the same as in the embodiment shown in FIG.
第１０図は本発明のまたさらに他の実施例を示している
。この例は、第８図及び第９図の実施例におけるダイオ
ード４４の代りにツェナーダイオード４８を設けたもの
である。これにより、入力電極パッド２６に一定電圧以
上の電圧が印加された場合、このツェナーダイオード４
８を介して正の電圧源Ｖ（（側にも放電が行われること
となり、より効果的な放電が行える。FIG. 10 shows yet another embodiment of the present invention. In this example, a Zener diode 48 is provided in place of the diode 44 in the embodiments of FIGS. 8 and 9. As a result, when a voltage higher than a certain voltage is applied to the input electrode pad 26, the Zener diode 4
Discharge is also performed on the positive voltage source V ((
第１１図は第８図及び第９図の実施例において、ベース
領域（Ｎ形エピタキシャル層２４）とアース間にツェナ
ーダイオード５０を接続したものであり、一定電圧以上
でこのツェナーダイオード５０をも介して放電を行うよ
うにして放電効果を向上させたものである。FIG. 11 shows the embodiment shown in FIGS. 8 and 9 in which a Zener diode 50 is connected between the base region (N-type epitaxial layer 24) and the ground. The discharge effect is improved by performing the discharge.
なお以上述べた実施例において、第１２図に示す如きダ
イオードによる従来の放電回路を併設しても良い。また
、以上の実施例はＮ形エピタキシ（９）
ャル層、Ｐ形基板を用いた例であるが、Ｎ形基板、Ｐ形
エピタキシャル層を用いても同様に構成することが可能
である。In the embodiment described above, a conventional discharge circuit using a diode as shown in FIG. 12 may also be provided. Further, although the above embodiment is an example using an N-type epitaxial layer and a P-type substrate, it is also possible to construct the same structure using an N-type substrate and a P-type epitaxial layer.
以上詳細に説明したように本発明によれば、第１半導体
領域と第２半導体領域とがＰＮ接合されると共に第２半
導体領域が入力電極周辺に形成されて基板との間に容量
が持たされているため、空き領域を利用し特別な領域を
占有することなく非常に大きな容量を得て静電電荷を容
量放電することができる。特別な領域を持たせる必要が
ないのでレイアウトが簡単となり高密度化を図れる。ま
た、第２半導体領域が最高電位に持ち上げられているた
め、入力側からは上述の容量が見えず、特性の悪化がな
い。As described above in detail, according to the present invention, the first semiconductor region and the second semiconductor region are PN-junctioned, and the second semiconductor region is formed around the input electrode, so that a capacitance is provided between the second semiconductor region and the substrate. Therefore, it is possible to obtain a very large capacity and discharge electrostatic charges by using empty space without occupying any special area. Since there is no need to provide a special area, the layout becomes simple and high density can be achieved. Further, since the second semiconductor region is raised to the highest potential, the above-mentioned capacitance is not visible from the input side, and there is no deterioration of characteristics.
第１図は本発明の一実施例の断面図、第２図はその平面
図、第３図はその回路図、第４図は本発明の他の実施例
の断面図、第５図はその回路図、第６図は本発明のさら
に他の実施例の断面図、第（１０）
７図はその回路図、第８図は本発明のまたさらに他の実
施例の断面図、第９図はその回路図、第１０図、第１１
図はそれぞれ本発明さらに他の実施例の回路図、第１２
図、第１３図は従来技術の回路図である。
１８・・−Ｐ形基板、 ２０山グランド・２２−・Ｎ＋
埋込層、２４−Ｎ形エピタキシャル層、２６−パッド、
２８．４２−、Ｐ膨拡散層、３０．３４−電極、 ３２
−Ｎ形層、
３６．４４−Ｐ Ｎ接合ダイオード、３日−・容量、４
６−Ｐ Ｎ Ｐ トランジスタ、
４８．５（１−−−ツェナーダイオード。
特許出願人
富士通株式会社
特許出願代理人
弁理士 青 木 朗
弁理士西舘和之
弁理士内田幸男
弁理士 山 口 昭 之
（１１）
第４図
第５図
工’−３８
第６図
９日
第７図
第８図
第９図FIG. 1 is a sectional view of one embodiment of the present invention, FIG. 2 is a plan view thereof, FIG. 3 is a circuit diagram thereof, FIG. 4 is a sectional view of another embodiment of the present invention, and FIG. Circuit diagram, FIG. 6 is a sectional view of still another embodiment of the present invention, FIG. 7 is a circuit diagram thereof, FIG. 8 is a sectional view of still another embodiment of the present invention, and FIG. are its circuit diagrams, Figures 10 and 11.
The figures are circuit diagrams of still other embodiments of the present invention, No. 12.
13 are circuit diagrams of the prior art. 18...-P type board, 20-mount ground, 22-, N+
buried layer, 24-N type epitaxial layer, 26-pad,
28.42-, P swelling diffusion layer, 30.34-electrode, 32
-N-type layer, 36.44-P N junction diode, 3 days--Capacity, 4
6-PNP transistor, 48.5 (1---Zener diode. Patent applicant: Fujitsu Limited Patent agent, patent attorney: Akira Aoki, patent attorney: Kazuyuki Nishidate, patent attorney: Yukio Uchida, patent attorney: Akira Yamaguchi (11) ) Fig. 4 Fig. 5 Fig. 38 Fig. 6 Fig. 9th Fig. 7 Fig. 8 Fig. 9
Claims (1)
半導体領域と、前記電極の周辺に形成され前記第１半導
体領域とＰＮ接合する第２半導体領域と、該第２半導体
領域の電位を最高電位に持ち上げる正電位供給手段と、
半導体基板とを備え、前記第２半導体領域と半導体基板
との間に容量を生じせしめることを特徴とする半導体装
置。 ２、前記第２半導体領域と半導体基板とがＰＮ接合され
ており、該第２半導体領域と半導体基板と前記第１半導
体領域とがトランジスタを構成している特許請求の範囲
第１項記載の半導体装置。 ３、前記正電位供給手段が正の電位源に接続されるオー
ム性接触手段である特許請求の範囲第１項もしくは第２
項記載の半導体装置。 ４、前記正電位供給手段が正の電圧源に接続されるＰＮ
接合ダイオードである特許請求の範囲第（１） １項もしくは第２項記載の半導体装置。 ５、前記正電位供給手段が正の電圧源に接続されるツェ
ナーダイオードである特許請求の範囲第１項もしくは第
２項記載の半導体装置。 ６、前記第２半導体領域とグランドとの間にツェナーダ
イオードが接続される特許請求の範囲第１、第２もしく
は第４項記載の半導体装置。[Claims] 1. An electrode connected to the outside, and a first electrode connected to the electrode.
a semiconductor region, a second semiconductor region formed around the electrode and making a PN junction with the first semiconductor region, and a positive potential supply means for raising the potential of the second semiconductor region to the highest potential;
1. A semiconductor device comprising: a semiconductor substrate, wherein a capacitance is generated between the second semiconductor region and the semiconductor substrate. 2. The semiconductor according to claim 1, wherein the second semiconductor region and the semiconductor substrate are in a PN junction, and the second semiconductor region, the semiconductor substrate, and the first semiconductor region constitute a transistor. Device. 3. Claim 1 or 2, wherein the positive potential supply means is an ohmic contact means connected to a positive potential source.
1. Semiconductor device described in Section 1. 4. PN in which the positive potential supply means is connected to a positive voltage source
The semiconductor device according to claim 1 or 2, which is a junction diode. 5. The semiconductor device according to claim 1 or 2, wherein the positive potential supply means is a Zener diode connected to a positive voltage source. 6. The semiconductor device according to claim 1, wherein a Zener diode is connected between the second semiconductor region and the ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10850784A JPS60253256A (en) | 1984-05-30 | 1984-05-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10850784A JPS60253256A (en) | 1984-05-30 | 1984-05-30 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60253256A true JPS60253256A (en) | 1985-12-13 |
| JPH0512861B2 JPH0512861B2 (en) | 1993-02-19 |
Family
ID=14486530
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10850784A Granted JPS60253256A (en) | 1984-05-30 | 1984-05-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60253256A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5685848A (en) * | 1979-12-15 | 1981-07-13 | Toshiba Corp | Manufacture of bipolar integrated circuit |
| JPS56132759U (en) * | 1980-03-10 | 1981-10-08 | ||
| JPS5817680A (en) * | 1981-07-23 | 1983-02-01 | Toshiba Corp | Semiconductor device |
| JPS592358A (en) * | 1982-06-28 | 1984-01-07 | Mitsubishi Electric Corp | Protective circuit for semiconductor circuit |
-
1984
- 1984-05-30 JP JP10850784A patent/JPS60253256A/en active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5685848A (en) * | 1979-12-15 | 1981-07-13 | Toshiba Corp | Manufacture of bipolar integrated circuit |
| JPS56132759U (en) * | 1980-03-10 | 1981-10-08 | ||
| JPS5817680A (en) * | 1981-07-23 | 1983-02-01 | Toshiba Corp | Semiconductor device |
| JPS592358A (en) * | 1982-06-28 | 1984-01-07 | Mitsubishi Electric Corp | Protective circuit for semiconductor circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0512861B2 (en) | 1993-02-19 |
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