JPS6025291A - Method of producing hybrid integrated circuit board - Google Patents

Method of producing hybrid integrated circuit board

Info

Publication number
JPS6025291A
JPS6025291A JP13383383A JP13383383A JPS6025291A JP S6025291 A JPS6025291 A JP S6025291A JP 13383383 A JP13383383 A JP 13383383A JP 13383383 A JP13383383 A JP 13383383A JP S6025291 A JPS6025291 A JP S6025291A
Authority
JP
Japan
Prior art keywords
plating
circuit board
integrated circuit
hybrid integrated
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13383383A
Other languages
Japanese (ja)
Inventor
茂 安田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP13383383A priority Critical patent/JPS6025291A/en
Publication of JPS6025291A publication Critical patent/JPS6025291A/en
Pending legal-status Critical Current

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  • Parts Printed On Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は高密度実装、高信頼性を要求される電子回路に
利用でき、受動チップ部品、半導体チップ部品の実装の
容易なセラミック多層の混成集積回路基板の製造方法に
関するものである。
[Detailed Description of the Invention] Industrial Application Field The present invention can be used for electronic circuits that require high-density packaging and high reliability, and is suitable for use in ceramic multilayer hybrid integrated circuits that are easy to mount passive chip components and semiconductor chip components. The present invention relates to a method of manufacturing a substrate.

従来例の構成とその問題点 従来、この種のセラミック多層の混成集積回路基板の製
造方法の1つとして、次のような方法がある。すなわち
、アルミナ粉末を主成分としだ生セラミツクシート上に
、タングステンモリブデン、マンガン等の耐熱性金属粉
末の単独もしくは混合物からなる導体ペーストを配線と
して印刷し、次いでアルミナ粉末の絶縁ペーストを絶縁
層として印刷する工程を交互に繰返して多層化した後、
還元雰囲気中で一括焼成する。次いで、最上層の表面に
露出した配線導体にニッケルメッキおよび金メッキを行
ない、セラミック多層配線基板とする。
Conventional Structures and Problems There are conventional methods for manufacturing this type of ceramic multilayer hybrid integrated circuit board as follows. That is, a conductive paste made of a heat-resistant metal powder such as tungsten molybdenum, manganese, etc., alone or in a mixture, is printed as a wiring on a raw ceramic sheet containing alumina powder as the main component, and then an insulating paste of alumina powder is printed as an insulating layer. After repeating the process alternately to create multiple layers,
Batch firing in a reducing atmosphere. Next, the wiring conductors exposed on the surface of the uppermost layer are plated with nickel and gold to obtain a ceramic multilayer wiring board.

これに、回路機能を持たすため、受動素子として、カー
ボン粉末と樹脂の混合物からなる抵抗ペーストを印刷、
焼付して抵抗体を形成する。次いで、受動チップ部品(
例えば、チノプコンデンザ)、ミニモールドトランジス
タなどを半田デイツプ法、半田リフロー法などで搭載し
、また半導体チップ部品(C,LSI)は、ワイヤボン
ド法などで接続する方法である。
In order to have a circuit function, we printed a resistive paste made of a mixture of carbon powder and resin as a passive element.
Baking to form a resistor. Next, passive chip components (
For example, chips (tinop capacitors), mini-mold transistors, etc. are mounted using the solder dip method, solder reflow method, etc., and semiconductor chip components (C, LSI) are connected using the wire bond method, etc.

しかしながら、この製造方法によれば、上記の耐熱金属
ペーストがいずれも400℃以上の高温、酸素雰囲気中
で酸化するためやむをえずカーボン系抵抗体を用いてい
る。このため、チップ部品等を搭載するための半田付工
程で熱的ストl/スを受けて抵抗値が変動するため、最
終検査で規格からしばしばはずれる欠点を有していた。
However, according to this manufacturing method, the above-mentioned heat-resistant metal pastes are all oxidized in an oxygen atmosphere at a high temperature of 400° C. or higher, so a carbon-based resistor is unavoidably used. For this reason, the resistance value fluctuates due to thermal stress during the soldering process for mounting chip components and the like, resulting in a drawback that the resistance value often deviates from the standard in the final inspection.

また、抵抗体の環境特性(耐熱特性、耐湿特性、温度特
性)も充分でなく、例えば耐熱特性(120℃、100
0Hr放置後の抵抗値変化率)は、−3,8%〜−6.
0%剛湿特性(60℃、96%RH1oooHr放置後
の抵抗値変化率)は+4.8%〜8.2係 温度特性(
−25℃〜+100℃間の抵抗値変化率)は±460p
pm/℃である。
In addition, the environmental characteristics (heat resistance, humidity resistance, temperature characteristics) of the resistor are not sufficient.
The resistance value change rate after standing for 0 hours is -3.8% to -6.
0% high humidity characteristics (60℃, 96% RH1oooHr resistance value change rate after leaving) is +4.8% to 8.2% Temperature characteristics (
Resistance value change rate between -25℃ and +100℃) is ±460p
pm/°C.

これらの値は、いずれも、面積抵抗値が75Ω/ロ〜1
0にΩ/口の抵抗体におけるものであり、抵抗値範囲が
大きくなれば上記の特性は、史に悪くなる傾向を示す。
All of these values have a sheet resistance value of 75Ω/Ω to 1
This is for a resistor with a resistance value of 0 to Ω/Ω, and as the resistance value range increases, the above characteristics tend to deteriorate over time.

どれらの欠点は、カーボン粉末と樹脂からなる抵抗体に
おいては常につきまとう問題であり、その原因は、耐熱
特性の場合は、樹脂の硬化収縮によるもので、耐湿特性
の場合は吸湿。
Which of these drawbacks is a constant problem with resistors made of carbon powder and resin? In the case of heat resistance, this is due to curing shrinkage of the resin, and in the case of moisture resistance, it is due to moisture absorption.

膨潤によるものである。This is due to swelling.

捷だ、従来の製造方法の大きな欠点として、半導体チッ
プ部品のワイヤボンド接続(金線による接続)のため、
基板の最上層配線に高価な金メッキを施す必要があり、
ボンディングの接続信頼性を確保するには、通常、電解
メッキ方式で1.6μm以上の厚みが必要であり、かつ
電解メッキを行なうだめのメッキ引出し配線が必要で、
基板の不要面積が増え、結果的に取り数が少なく基板コ
スト 。
However, one of the major drawbacks of the conventional manufacturing method is that the wire bonding (connection using gold wire) of semiconductor chip components requires
It is necessary to apply expensive gold plating to the top layer wiring of the board,
In order to ensure bonding connection reliability, a thickness of 1.6 μm or more is usually required using the electrolytic plating method, and a plating lead-out wiring is required for electrolytic plating.
The unnecessary area of the board increases, resulting in fewer chips and lower board costs.

が高くなる欠点を有していた。It had the disadvantage that it became high.

一方、無電解メッキ方式においては、3.o/Jm以上
の厚みが必要で°、この場合も、基板コストが高くなる
欠点を有していた0 発明の目的 本発明の目的は、高信頼性の印刷抵抗体が形成された混
成集積回路基板のコストの低減および半導体チップ部品
等の実装の容易な毛ラミック多層による混成集積回路基
板の製造方法を提供することにある。
On the other hand, in the electroless plating method, 3. A thickness of 0/Jm or more is required, which also has the disadvantage of increasing the substrate cost.Objective of the Invention The object of the present invention is to provide a hybrid integrated circuit in which a highly reliable printed resistor is formed. It is an object of the present invention to provide a method for manufacturing a hybrid integrated circuit board using lamic multilayers, which reduces the cost of the board and facilitates the mounting of semiconductor chip parts and the like.

発明の構成 この目的を達成するために本発明は、還元性雰囲気中で
一体化焼結されたセラミック多層配線基板上に印刷抵抗
体が形成された回路基板に、所望の回路パターンでメッ
キ用の金属核を有する活性ペーストを印刷した後、焼成
してメッキ核を形成す°るし、その後前記メッキ核上部
に無電解メッキを行ない、メッキ導体を形成するもので
ある。
Structure of the Invention To achieve this object, the present invention provides a circuit board in which a printed resistor is formed on a ceramic multilayer wiring board that is integrally sintered in a reducing atmosphere, and a circuit board for plating with a desired circuit pattern. After printing an active paste having a metal core, it is fired to form a plating core, and then electroless plating is performed on the top of the plating core to form a plated conductor.

なお、上記セラミック多層配線基板の表面配線引出孔に
は耐酸化性導体、例えば、白金、パラジウム、ロジウム
、イリジウムの単体もしくは合金などを充填したものが
必要である。これらにより、従来の還元性雰囲気焼結型
のセラミック多層配線基板に高信頼性の印刷抵抗体が形
成できる0まだ、印刷抵抗体は現在、常用されている酸
化ルテニウム系抵抗体が有効であり、この抵抗体の下部
電極には、銀、パラジウム、全白金の単体もしくは合金
からなる単体が有効である。
Note that the surface wiring lead-out hole of the ceramic multilayer wiring board needs to be filled with an oxidation-resistant conductor, such as platinum, palladium, rhodium, or iridium alone or in an alloy. As a result, a highly reliable printed resistor can be formed on a conventional reducing atmosphere sintered ceramic multilayer wiring board. However, as a printed resistor, the commonly used ruthenium oxide resistor is effective. For the lower electrode of this resistor, a single substance or an alloy of silver, palladium, or all-platinum is effective.

寸だ、メッキ導体としては、コスト、半田付性の点から
、銅、錫、半田、ニッケルメッキ等の単層メッキもしく
は複層メッキが特に有効である。
As a plating conductor, single-layer plating or multi-layer plating of copper, tin, solder, nickel plating, etc. is particularly effective in terms of cost and solderability.

このメッキ導体は回路導体および、受動チップ部品、半
導体チップ部品等の接続電極である0実施例の説明 以下、本発明を製造工程に従い、実施例に基づいて説明
する。
This plated conductor is a circuit conductor and a connection electrode for passive chip components, semiconductor chip components, etc. 0 Description of Embodiments The present invention will be described below based on embodiments according to the manufacturing process.

(1) セラミック材料として、主成分のアルミナに、
シリカ、マグネ7ア等を加え、さらに結合樹脂としてポ
リビニルブチラール樹脂、可塑剤としてフタル酸ジプチ
ル、溶剤としてイソプロピルアルコールとを加え混練し
たアルミナスラリーをシート状に造膜し、アルミナ生シ
ートを作成した。
(1) As a ceramic material, the main component is alumina,
Silica, Magne 7A, etc. were added, and an alumina slurry was kneaded with polyvinyl butyral resin as a binder resin, diptyl phthalate as a plasticizer, and isopropyl alcohol as a solvent, and then kneaded into a film to form a raw alumina sheet.

(2)次いで、第1図のようにアルミナ生シート1上に
、タングステン、モリブデン、マンガン等の耐熱性金属
の単体もしくは混合物を含むペースト状の導体2をスク
リーン印刷法により所望の配線パターンで印刷し、乾燥
した。
(2) Next, as shown in Fig. 1, a paste-like conductor 2 containing a single or a mixture of heat-resistant metals such as tungsten, molybdenum, and manganese is printed in a desired wiring pattern on the raw alumina sheet 1 using a screen printing method. and dried.

(3)次いで、第2図のように上記アルミナ生シート1
と同じ材料からなる絶縁ペースト状の絶縁体3をスクリ
ーン印刷法により、所望のパターンで印刷し、乾燥した
(3) Next, as shown in Fig. 2, the above raw alumina sheet 1
An insulating paste-like insulator 3 made of the same material as above was printed in a desired pattern by screen printing and dried.

(4)次いで、第3図のように上記の(2) + (3
)の工程を交互に繰返し行ない、アルミナ生シート1上
に内部配線導体2および、スルホール導体を兼ねた内部
配線導体4、最上層の絶縁体5に表面配線引出孔6を形
成した。
(4) Next, as shown in Figure 3, the above (2) + (3
) were repeated alternately to form internal wiring conductors 2 and internal wiring conductors 4 which also served as through-hole conductors on the raw alumina sheet 1, and surface wiring extraction holes 6 in the uppermost layer insulator 5.

(6)次いで第4図のように表面配線孔6に、白金、パ
ラジウム、ロジウム、イリジウムの単体もしくは混合物
から耐酸化性金属のペースト状の導体7をスクリーン印
刷法により充填した後、還元雰囲気中で1520℃に加
熱して、上記導体、絶縁体および生シートを一体化焼結
した。
(6) Next, as shown in Fig. 4, the surface wiring hole 6 is filled with an oxidation-resistant metal paste conductor 7 made of platinum, palladium, rhodium, or a mixture of platinum, palladium, rhodium, and iridium by screen printing method, and then placed in a reducing atmosphere. The conductor, insulator, and raw sheet were sintered into one piece by heating to 1520°C.

これにより得たセラミック多層配線基板の表面配線孔に
はピンホールは皆無であった。
There were no pinholes in the surface wiring holes of the ceramic multilayer wiring board thus obtained.

(6)次いで、これにより得た、セラミック多層配線基
板上に、第5図に示すように、銀、パラジウム、金、白
金等の耐熱性金属の単体もしくは混合物を含むペースト
状の導体8を所望の電極パターンでスクリーン印刷法に
より印刷し、酸化雰囲気中で850℃に加熱して、電極
とした。
(6) Next, on the ceramic multilayer wiring board thus obtained, as shown in FIG. An electrode pattern was printed using a screen printing method and heated to 850° C. in an oxidizing atmosphere to obtain an electrode.

(7)次いで、第6図に示すように上記(6)で得た電
極の上部に酸化ルテニウム粉末、ホウケイ酸鉛系ガラス
、樹脂としてエチルセルローズ、溶剤として、プチルカ
ルビトールアセテートヲ加え、混合、分散して成る抵抗
ペーストを所望の抵抗パターンでスクリーン印刷し、酸
化雰囲気中で68o℃に加熱して抵抗体9を形成した。
(7) Next, as shown in FIG. 6, ruthenium oxide powder, lead borosilicate glass, ethyl cellulose as a resin, and butyl carbitol acetate as a solvent were added to the top of the electrode obtained in (6) above, and mixed. The dispersed resistor paste was screen printed in a desired resistance pattern and heated to 68° C. in an oxidizing atmosphere to form a resistor 9.

(8)次いで、第7図に示すように、メッキ用の金属核
を有する活性ペースト(大冊化学工業■製、商品名 1
980P40)を所望の配線パターン状にスクリーン印
刷し、酸化雰囲気中で480℃に加熱してメッキ核10
を形成した。
(8) Next, as shown in FIG.
980P40) into the desired wiring pattern and heated to 480°C in an oxidizing atmosphere to form plating nuclei 10
was formed.

(9)次いで、これを、硫酸銅メッキ液中に浸漬し無電
解方式により銅メツキ導体11を形成した。これを受動
チップ部品、半導体チップ部品の接続電極とし、これを
セラミック多層の混成集積回路用基板とした。
(9) Next, this was immersed in a copper sulfate plating solution to form a copper-plated conductor 11 by an electroless method. This was used as a connection electrode for passive chip components and semiconductor chip components, and this was used as a substrate for a ceramic multilayer hybrid integrated circuit.

参考までに、第8図に上記セラミック多層の混成集積回
路用基板上に積層チップコンデンサ12、半導体チップ
(IC)13を搭載したセラミックチップキャリアを半
田リフロ一方式により装着した状態を示した。
For reference, FIG. 8 shows a state in which a ceramic chip carrier on which a multilayer chip capacitor 12 and a semiconductor chip (IC) 13 are mounted is mounted on the ceramic multilayer hybrid integrated circuit substrate using a solder reflow method.

以上の(1)〜(9)の工程で得た混成集積回路基板に
形成した印刷抵抗体の環境特性を測定したところ、面積
抵抗値が15Ω/口〜850にΩ/(]の範囲内で、耐
熱特性(120℃、1000Hr放置後)は、0.12
%−0,38%、耐湿特性(60’C95%RH、10
00Hr放置後)は0.04−0.21%、温度特性(
−26℃〜+1oo℃)は、±280ppm/℃であり
、従来のカーボン系抵抗体を使用したものより著しく特
性が改善される。
When we measured the environmental characteristics of the printed resistor formed on the hybrid integrated circuit board obtained in steps (1) to (9) above, we found that the sheet resistance value was within the range of 15Ω/unit to 850Ω/(). , heat resistance property (after standing at 120℃, 1000Hr) is 0.12
%-0,38%, moisture resistance (60'C95%RH, 10
After 00Hr standing) is 0.04-0.21%, temperature characteristics (
-26°C to +100°C) is ±280 ppm/°C, and the characteristics are significantly improved compared to those using conventional carbon-based resistors.

発明の効果 以上のように本発明による製造方法は、信頼性の高い印
刷抵抗体を形成した回路基板に、低コストのメッキ導体
形成が可能で、しかも無電解メッキ方式で行なえるため
、製法が簡単であることや取り数が多いことなどにより
基板コストを大幅に低減できる効果がある。また、従来
の製造方法の場合は、多層配線基板の製造メーカーが、
金メツキ工程あるいは抵抗形成工程まで行なったものを
ユーザーで加工するシステムのため、配線パターンを変
更する場合、長期間(30〜45日)要するが、本発明
では、ユーザーの方で、セラミック基板(配線のない状
態)と同じイメージで、メッキ導体用のパターン変更の
みを行なえばよく、設計変更への対応が早くなる効果が
ある二さらには受動チップ部品、半導体部品等の実装が
一度に行なえ、組立工数の低減がはかれるなどの効果も
ある。
Effects of the Invention As described above, the manufacturing method according to the present invention enables low-cost plating conductor formation on a circuit board on which a highly reliable printed resistor is formed, and moreover, it can be performed using an electroless plating method. Due to its simplicity and large number of chips, it has the effect of significantly reducing board costs. In addition, in the case of conventional manufacturing methods, manufacturers of multilayer wiring boards
Since the system requires the user to process the product after the gold plating process or the resistor forming process, it takes a long time (30 to 45 days) to change the wiring pattern. With the same image as the state (without wiring), only the pattern for the plated conductor needs to be changed, which has the effect of speeding up response to design changes.Furthermore, passive chip components, semiconductor components, etc. can be mounted at the same time. This also has the effect of reducing assembly man-hours.

【図面の簡単な説明】[Brief explanation of drawings]

第1図〜第7図は本発明の一実施例における混成集積回
路基板の製造工程を示す断面図、第8図は本発明により
得た混成集積回路基板に受動チップ部品と半導体部品を
実装した状態を示す断面図である。 1・・・・・・アルミナ生シート、2,7.8・川・・
導体、3.5・・・・・・絶縁体、4・・・・・・内部
配線導体、6・・・・・表面配線孔、9・・・・・・抵
抗体、10・・・・・・メッキ核、11・・・・・・銅
メツキ導体、12・・・・・・積層チップコンデンサ、
13・・・・・・半導体チップ。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 第2図 第6図 第7図 第8関
Figures 1 to 7 are cross-sectional views showing the manufacturing process of a hybrid integrated circuit board according to an embodiment of the present invention, and Figure 8 is a cross-sectional view showing the manufacturing process of a hybrid integrated circuit board obtained according to the present invention, with passive chip components and semiconductor components mounted on the hybrid integrated circuit board obtained according to the present invention. It is a sectional view showing a state. 1... Alumina raw sheet, 2, 7.8... River...
Conductor, 3.5... Insulator, 4... Internal wiring conductor, 6... Surface wiring hole, 9... Resistor, 10... ... Plated core, 11 ... Copper plating conductor, 12 ... Multilayer chip capacitor,
13... Semiconductor chip. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 6 Figure 7 Figure 8

Claims (1)

【特許請求の範囲】[Claims] 還元性雰囲気中で一体化焼結されたセラミック多層配線
基板上に印刷抵抗体が形成された回路基板に、所望の回
路パターンでメッキ用の金属核を有する活性ペーストを
印刷した後、焼成してメッキ核を形成し、その後前記メ
ッキ核上部に無電解メッキを行ないメッキ導体を形成す
ることを特徴とする混成集積回路基板の製造方法。
After printing an active paste with a metal core for plating in a desired circuit pattern on a circuit board in which a printed resistor is formed on a ceramic multilayer wiring board that is integrally sintered in a reducing atmosphere, it is fired. 1. A method for manufacturing a hybrid integrated circuit board, comprising forming a plating core, and then performing electroless plating on the top of the plating core to form a plated conductor.
JP13383383A 1983-07-21 1983-07-21 Method of producing hybrid integrated circuit board Pending JPS6025291A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13383383A JPS6025291A (en) 1983-07-21 1983-07-21 Method of producing hybrid integrated circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13383383A JPS6025291A (en) 1983-07-21 1983-07-21 Method of producing hybrid integrated circuit board

Publications (1)

Publication Number Publication Date
JPS6025291A true JPS6025291A (en) 1985-02-08

Family

ID=15114101

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13383383A Pending JPS6025291A (en) 1983-07-21 1983-07-21 Method of producing hybrid integrated circuit board

Country Status (1)

Country Link
JP (1) JPS6025291A (en)

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