JPS60251693A - High density fanout metallurgy substrate and method of producing same - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is directed to a dielectric substrate for semiconductor packages.
It relates to forming (metallurgical) interconnect structures, and more specifically to forming dense fan-out patterns in multilayer ceramic substrates.

[Prior Art] Future semiconductor packages will require many highly integrated semiconductor devices, each containing hundreds of circuits, mounted on a single substrate and interconnected into functional systems. Ru. This includes significantly increasing the area of the package substrate compared to single and overlapping device package substrates commonly used today, increasing wiring density, and providing closely spaced bonding terminals for connection to semiconductor devices. It is necessary to provide a large number of A structure that may be able to meet future high-density packaging requirements is a multilayer ceramic substrate. This structure is described in U.S. Pat.
It is described in detail in No. 5273. This substrate is embedded with metallurgy lines, allowing for highly complex wiring interconnections.

The basic process is to create a ceramic slurry of granular ceramic material, resin adhesive, and adhesive solvent, doctor blade the slurry, and dry it to produce ceramic green sheets.

It consists of drilling holes in green sheets, screening conductors, pasting the sheets together, and sintering them.

[Problems to be Solved by the Invention] Integrated circuit devices are becoming increasingly dense and large, which requires more terminals, and the terminals are becoming more closely spaced. In a typical multilayer ceramic substrate using solder bonding, the top sheet has a perforated via structure that matches the terminal structure of the semiconductor device. Fan-out of metallurgy lines is performed in multiple base layers. However, when the via holes are closely spaced, cracks may form between the vias during sintering due to the different coefficients of thermal expansion of the conductive material in the vias and the ceramic material of the substrate. This results in a loss of yield and can cause future problems if the initial short circuit does not occur.

Moreover, the close spacing of a large number of terminals requires more and more base layers to achieve metallurgy wire fan-out, significantly increasing the cost of the board.

It is known to implement surface metallurgy fan-out patterns with terminals on the top surface of the substrate, as suggested by US Pat. No. 3,968,19.3. This one
A surface metallurgical structure consisting of a layer or multiple layers can be achieved by screening the substrate through a mask or using photolithographic techniques after sintering the substrate.

However, during sintering the substrate shrinks by about 17%. This shrinkage can be accommodated by designing the unsintered substrate to be larger by the shrinkage. Shrinkage is not necessarily uniform over the entire area of the substrate. Areas of larger or smaller shrinkage may appear, distorting the pattern of vias on the surface. It may not be possible to align the screening mask or resistor exposure mask to the pattern vias. The pattern vias must be connected so that contact is established with the internal metallurgy of the board. As the vias get smaller and the sheets get bigger, this problem becomes more critical.

Accordingly, it is an object of the present invention to provide a method of forming a semiconductor package substrate having a conductive surface fan-out pattern interconnected to an internal metallurgy pattern.

Another object is to provide a substrate with a traffic metallurgy pattern consisting of an interconnected conductive surface line pattern with an internal metallurgy structure.

Another object is to provide a practical and reliable method for contacting underlying internal metallurgy with surface metallurgy patterns without requiring increasingly closely spaced vias in the top sheet. It is an object of the present invention to provide a method for forming closely spaced terminal patterns and fan-out metallurgy patterns on a substrate for making connections.

Means for Solving the Problems Based on the above objects, the present invention provides a method for forming a high density interconnect pattern and metallurgy structure for electrically connecting an integrated circuit semiconductor device to a supporting substrate. , providing a green ceramic substrate with an internal metallurgy system including a barrier matrix filled with a conductive metal paste on the top surface of the green ceramic sheet; forming a recessed area interspersed therewith and a recessed line joined to the recessed area and generally extending outward to form a fan-out structure; filling the recessed area and the recessed line with a conductive metal paste; This is done by screening a dielectric layer of ceramic material that covers the recessed lines on the top surface of the substrate but leaving the vias and recessed areas exposed, and by sintering the substrate.

The high density multiple interconnect pad and fan-out metallurgy for the multilayer ceramic module of the present invention comprises a multilayer ceramic substrate with an internal metallurgy system, a plurality of an outer ring of vias surrounding the vias and a matrix on the top surface of the substrate, arranged as a matrix with vias within the via matrix arranged in alternating spaces between the via matrix, and a matrix of recessed areas with the via matrix; a plurality of small recessed regions of the substrate surface, each terminating at one end in a recessed region of the matrix and at the other end in one via of the via outer ring, collectively defining an interconnect terminal structure; a conductive metal material deposited in the recessed lines, recessed lines and recessed areas of the via matrix to form a surface metallurgy fan-out pattern; a dielectric layer with an opening over each recessed region, and a plurality of terminal pads overlying the vias with a matrix of via holes and the recessed region with a matrix of recessed regions, respectively. .

EXAMPLE Referring now to the drawings, FIG. 1 shows a flowchart illustrating a new combination of steps of the method according to the invention for producing a dense metallurgical structure in a multilayer ceramic substrate. be.

Block 10 instructs to provide a green ceramic substrate. The basic structure of this ceramic substrate, preferably a multilayer ceramic substrate, is conventional. Block 12 provides additional pads and conductors on the surface of the top layer in addition to the normally spaced vias. A top cross-sectional view of the preferred embodiment is shown in substrate 2 in FIG.

The terminal pad connection footprint for connecting to a semiconductor device is comprised of circular vias 22 arranged in a matrix of rows and columns and a second matrix of recessed areas 24 interspersed between the via matrix. . As clearly shown in Figure 3, the fan-out structure of via 22 is
It ends with a series of vias 26 arranged in one or more rows around the edges of the matrix structure. As can be seen in FIG. 3, the vias 22 extend downwardly into the ceramic layer 28.
and 30, where it is joined to a metallurgical strip 32, which is connected to a via 26, which terminates in a pad 38 on the surface of the substrate. Board 2
A fan-out arrangement of 0 internal layers can extend through more or fewer layers, and typically can extend in both the X and 'Y directions in different layers. As is well known, the combination of vias 26, cuttable stripes 36, and pads 38 generally requires engineering changes.
It's called a pad. In use, wire portions 36 can be cut and appropriately connected from pads 38 to other suitable terminals to correct defects in internal metallurgy or to modify wiring. An important aspect of the green substrate 20 is that the density of the vias 22 is less than the butts of the input/output connections to the device since intermediate connections to pads are made. The surface metallurgy structure of the present invention includes a pad 24, a surface line 40 bonded to the pad 24 and the pad 42;
It consists of a surface fan-out metallurgy containing . As shown in FIG. 3, vias 44 extend downwardly into substrate 20. As shown in FIG.

Interconnected with the internal metallurgy of the board. Technique changes can also be made to the surface metallurgy pattern by cutting stripes 40 and bonding pads 42 with wires to which pads 42 are bonded.

To form a surface metallurgy on the substrate 20, a pattern of recessed surface areas 24 and recessed lines 40 is created in the substrate. The substrate is a green sheet and is deformable so that it can be recessed. Also, since the substrate is a green sheet and has not yet been deformed by normal sintering operations, aligning this depression with other surface features on the substrate such as vias 42 and proper spacing maintained between vias 22 be able to.

Recessed surface features can be formed by creating a die that includes raised areas and lines in a pattern that is inverse to the shape of the intended recessed features. The die can be produced by forming a pattern on the area to be raised using a conventional metal forming method such as photolithography, and then performing a metal removal operation such as metal etching, sputter etching, or electrolytic metal removal. A die on which a raised line in the opposite shape to the pattern is formed is placed on a substrate, and the die is pressed inward using an appropriate pressure/temperature application technique such as a lamination press.
A recessed area 24.42 and a recessed line 40 are formed. Further, even if the surface of the substrate is corroded by an electron beam, a laser, etc., depressions can be formed.

The shape, width, and depth of the lines may be any dimension consistent with the relevant dimensions of the substrate and sheet. Preferably, the depth of the lines and regions should be between 0.0076 and 0.05 mm. The width of the recessed line is O,,013~0.05mm, preferably O',0
25-0.05mm. The line width to depth ratio is preferably on the order of 2:] to 1:1.

Block 14 indicates that the next step in the method of the present invention is to fill the recessed pattern or regions 24 and recessed lines 40 with conductive material.

If the substrate is made of a material that requires high sintering temperatures, such as alumina, the conductive paste must be made of a refractory metal. Pastes consisting essentially of particulate refractory metal, MOlW, or Ta, with the addition of a resin, a solvent for the resin and, if desired, a plasticizer, are well known. but,
If the substrate material is a glass-ceramic material that does not have a high sintering temperature, such as alumina, other suitable metals with higher conductivity, such as copper, may be used. In any case, the conductive paste applied to the recessed pattern must be able to withstand the subsequent sintering operation. The paste is
The paste may be applied by any suitable method, such as by wiping the substrate surface with a suitable device that selectively applies the paste to the recesses. A better method for applying paste to the recesses is to first apply a thin plastic film to the substrate surface and then form the recesses. If there is a plastic membrane,
It becomes easier to attach the conductive material to the recess. The method of applying conductive paste to the recesses of the board is based on IBM's T.D.B.
, April,' 1974 P.

3561 in detail. In this method, a Mylar sheet, which is used as a coating base for doctor blading a ceramic slurry, is first coated with polyvinyl alcohol. Peel off the cast green sheet from the casting base sheet.
The polyvinyl alcohol coating adheres strongly to the green ceramic sheet, forming a thin, smooth, uniform surface film. The coated green ceramic sheet is then indented in the desired pattern.

A depression can be formed due to the membrane. Push the conductive paste into the recess and allow the solvent to evaporate. During sintering, the film burns away. Alternatively, the green sheet can be coated or cast as a precast sheet and then the surface film applied. Also, polyamide may be used instead of polyvinyl alcohol.

Block 16 indicates that the next step in the method of the present invention is to selectively apply a dielectric layer 5° in the area of the terminal pad structure.

Dielectric layer 50 includes engineering pads 42.36.
It must not extend above the 38th column. When soldering devices to pad structures, to prevent solder bridging from occurring on very closely spaced input/output pads and lines.
A dielectric layer is applied over the foot traffic terminal area. Preferably, U.S. Patent Nos. 3,495,113 and 3,429,040
The device may be joined to the pad structure using solder joints, as detailed in this issue. Best is to form dielectric layer 50 of a material that withstands sintering operations. The preferred material is a ceramic slurry similar to that used to manufacture the green ceramic sheets of the substrate. Of course, various combinations of solvents and organic thickeners (thixotropic agents) can be used during screening. To avoid weakening of the green metal wire at the edges of the screened ceramic area, the slurry should be of a composition that does not wash off the solvent after screening. A ceramic slurry can be applied to the pad area through a suitable screening mask. The mask must provide blockout areas so that no ceramic material is applied over the vias 22 and recessed area pads 24. The thickness of the dielectric layer is best between 0.0025 and 0.025 mm. After applying the dielectric layer on the butt area, block 1
The substrate is sintered in the usual manner as indicated at 8. During the sintering operation, the substrate typically shrinks by about 17%, depending on the ceramic type and sintering conditions. Additionally, during the sintering operation, the substrate may be slightly distorted, but not so much that the individual pad areas used to bond the substrate to the semiconductor device become misaligned.

All microalignment steps have been completed prior to sintering. Following the sintering operation, the metallurgy areas including vias 22, pads 24, engineering pads and vias 42, and the recessed patterns not covered by the dielectric layer are coated with a suitable metal to make the pads solder wettable. , Related Technology Changes Pads can be coated with metals to which wires can be bonded by heat compression bonding or other methods. This metallurgy is formed on the surface of the substrate using conventional methods.

[Effects of the Invention] According to the present invention, a large number of terminals can be arranged on a ceramic substrate at close intervals, so that the cost of a multilayer substrate can be significantly reduced.

[Brief explanation of drawings]

FIG. 1 is a flow chart showing each step of the method of the present invention, FIG. 2 is a greatly enlarged plan view of a portion of the solder pad structure and surface fine-out metallurgy structure of the present invention, and FIG. FIG. 2 is a sectional view taken along line 3-3 in FIG. 2; 20... Board, 22:... Via, 24...
・Pad, 26... Via, 28.3o... Ceramic layer, 32... Metal stripe, 36...
・Cuttable stripe, 38...pad, 4o...
...Surface line, 42...Pad, 44...Via, 5o...Dielectric layer. Applicant International Business Machines
Corporation Sub-Agent Patent Attorney Shino 1) Text Yu FIG, 1 20--Board

Claims (2)

[Claims] (1) a multilayer ceramic substrate with an internal metallurgical structure; a plurality of vias arranged in a closely spaced matrix on the top surface of the substrate and an outer ring of vias surrounding the matrix; Bahia alternates between Bahia and Bahia.
a plurality of small recessed regions arranged in a matrix such that the via matrix and the matrix of recessed regions collectively define an interconnect pad structure within the spaces between the matrices; terminating in a recessed area of the matrix;
the other end terminates in a via in said via outer ring;
a plurality of recessed lines on the surface of the substrate; a conductive metallic material deposited in the recessed lines and the recessed areas to form a surface metallurgy fan-out pattern; a dielectric layer with an opening over each of said recessed regions filled with metal in a matrix of recessed regions; and over each of said recessed regions with said matrix of vias and recessed regions, respectively. A high-density fan-out metallurgy board for multilayer ceramic modules, including multiple solder pads in the. (2) providing an unsintered green ceramic substrate with an internal metallurgy structure including a via matrix filled with a conductive metal paste on the top surface of the green ceramic substrate between the vias; forming a recessed area interspersed with the recessed area and a recessed line bonded to this recessed area and generally expanding outward to form a fan-shaped structure; filling the recessed area and the recessed line with a conductive metal paste; screening a dielectric layer of ceramic material on top of the recessed line but leaving the barrier and the recessed area exposed and sintering the substrate; A method of forming a high-density fan-out metallurgy board for electrically connecting a support substrate to a support substrate.