JPS60250436A - Microprogram controller - Google Patents

Abstract

PURPOSE:To decrease the number of states by decoding the outputs of an instruction register and a microinstruction pointer which stores temporarily the address of the state under execution through the 1st decoder and providing a specific branch control circuit to said pointer. CONSTITUTION:The outputs of a microinstruction pointer 34 which stores temporarily the address of the state under execution and an instruction register 1 are supplied to a PLA type decoder 32. Then the address of the state to be executed and a flag showing the presence or absence of branch are supplied to a branch control circuit 33 to decide a branch address. The output of the pointer 34 is decoded by a ROM type decoder 5, and a decoder 5 or 32 is selected through a selection signal line 6 and encoded by an encoder 7. Thus it is possible to use the output of the decoder 32 for the 2nd and its subsequent states.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a microprogram control system with a large degree of freedom in which states can be branched or shared.

Conventional configurations and their problems Microprogram-based control systems can reduce the overall number of states by sharing instruction states, but as the number of state branch conditions increases, the branch control circuit becomes more complex. I'm going to switch.

A conventional example of a conventional microprogram control system will be explained with reference to FIGS. 1 and 2.

In the figure, 1 is an instruction register (I, R) that temporarily stores the instruction code, 2 is a PLA format decoder (PLA dec, ) that decodes its output, and 3 is the address of the next state to be executed (NXTADR). , a branch condition (BRCOND), and a flag (FL) indicating the presence or absence of a branch.
A branch control circuit (BRC) which inputs a part of the output of the instruction register 1 (AG) and a part of the output of the instruction register 1 and sets a branch destination address to a microinstruction pointer (described later); 4 is a microinstruction which temporarily stores the address of the state currently being executed; Pointer (MIP
), 6 is a ROM-format decoder (ROMdec, ) that decodes its output, 6 selects the output of the PLA-format decoder 2 in the first state of the instruction, and selects the output of the ROM-format decoder 5 in subsequent states. 7 is the PLA format decoder 2 or ROM
This is an encoder that encodes the output of the format decoder 6. A part of the output of this encoder 7 is applied to the branch control circuit 3 as an NXTADR signal.

As shown in Figure 2, there are three types of instructions a, b, and C.
In the state, the operation mode is different for each instruction,
And if there are four addressing modes, it is necessary to branch in 12 directions when transitioning from control by the first PLA format decoder 2 to control by the 1 (OM format decoders).In that case, generally the output of instruction register 1 The branch control circuit 3 is required to have a function of incorporating a part of the address into the branch destination address and setting it in the microinstruction pointer 4.

In FIG. 2, black circles indicate PLA dec, used, and white circles indicate ROMdec, used.

In the conventional method, states can be easily merged, but branching requires a large amount of hardware in the branch control circuit, and as shown in Section 2A, the number of decodes of the second state increases. 0 Also, if only a PLA format decoder is used, multiple decode lines can be enabled simultaneously in the second state as shown in Figure 2B, so the number of decodes in the second state will be reduced. Since it is difficult to share states, there is a problem in that even states that perform the same processing, such as the fourth state, must be decoded for each instruction.

OBJECTS OF THE INVENTION The present invention solves the above problems, and aims to provide a microprogram control device that reduces the number of overall instruction states by sharing states and simplifies the state branch control circuit. .

Structure of the Invention The present invention provides an instruction register table for temporarily storing an instruction code;
A PLA format decoder inputs and decodes the output of the instruction register and the microinstruction pointer, and inputs the address of the next state to be executed, a signal indicating a state branch condition, and a flag indicating the presence or absence of a branch. , a branch control circuit that changes the branch destination address, the microinstruction pointer that temporarily stores the address of the branch destination state, and an RO that decodes the output of the microinstruction pointer.
A microprogram control device having an M-format decoder and a selection means for selecting either the output of the PLA-format decoder or the output of the ROM-format decoder, which reduces the number of states of the entire instruction. This makes it possible to branch or share states with a large degree of freedom with a simple branch control circuit.

DESCRIPTION OF THE EMBODIMENT FIG. 3 shows the configuration of a microprogram control device in an embodiment of the present invention, where 1, 5, 6, and 7 are the same as the conventional example, and 32 is a part of the microinstruction pointer input. 33 is a branch control circuit that receives as input the address of the next state to be executed, a branch condition, and a flag indicating the presence or absence of a branch, and determines the branch address. , unlike the conventional example, the output of the instruction register 1 is not input. 34 is a microinstruction pointer that temporarily stores the address of the branch destination state;
It is reset by the gate 38 described later in the final execution cycle of the instruction. Gate 38 is connected to the microinstruction pointer 34.
This is a gate that resets the 39 is a LAST signal indicating the final execution cycle of the instruction, and 310 is a USEROM signal indicating that the output of the ROM format decoder 5 is used.

The operation of the microprogram control device of this embodiment configured as described above will be explained below.

As shown in Fig. 4, there are instruction 1 that is executed in 2 cycles and instruction 2 that is executed in 3 cycles, and both instruction 1 and instruction 2 are instructions that select and use the output of the ROM-format decoder 6 in the last cycle. . USEROM 3101rJ: In the next state, the output of ROM-format decoding 5 is programmed.
'It is enabled in the cycle in which the output of the OM format decoder 5 is selected. Therefore, in that cycle, the output of the decoder 5 is encoded to generate the control signal Sig1.

The first state of instruction 1 and the first state and second state of instruction 2
The state encodes the output of the decoder 32 in reverse, and the control signal Sig 1 is generated.

By making the output of the PLA format decoder 32 selectable in the second state 1 as in instruction 2, the decode line that determines the operation mode and the decode line that determines the addressing mode for each instruction as shown in FIG. can be separated. In addition, in Figure 5, the black circle is PLAdec, used, and the white circle is ROMdec.

Shows use. Therefore, for example, in the case of instruction a using addressing mode 2, a decode line that outputs adrm 2 and a decode line that outputs the operation mode of instruction a are simultaneously output in state 2.

In the conventional example, since state 2 outputs from the ROM-type decoder I/6, it is not possible to output two decode lines at the same time.

As described above, by using the PLA type decoder output, the number of states of the entire instruction can be switched and the number of decode lines can be significantly reduced.

Effects of the Invention The present invention makes it possible to use the output of the PLA format decoder even after the second state, thereby simplifying the state branch control circuit and greatly reducing the number of states in the entire instruction. Therefore, its practical effects are great.

[Brief explanation of the drawing]

FIG. 3 is a block diagram of a microprogram control device according to an embodiment of the present invention, FIG. 4 is a timing diagram for explaining the operation of the embodiment, and FIG. 6 is a state branch diagram for explanation. FIG. 2 is a state branch diagram for explaining state branches in the same embodiment. 1... Instruction register, 32... PLA format decoder (first decoder), 33... Branch control circuit, 34...
...Microinstruction pointer, 6...ROM format decoder (second decoder), 6...Selection signal, 7...
...Encoder. Name of agent: Patent attorney Toshio Nakao and 1 other person Hana 1
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Claims (1)

[Claims] an instruction register that temporarily stores an instruction code; a microinstruction pointer that temporarily stores the address of the currently executing state; and a first decoder that receives and decodes the output of the instruction register and the microinstruction pointer. , a second decoder for decoding the output of the microinstruction pointer, a selection means for selecting and outputting the first decoder output and the second decoder output, and encoding the output selected by the selection means. an encoder that generates a control signal, and a branch control circuit that receives as input the address of the next state to be executed, a signal indicating a state branch condition, and a flag indicating the presence or absence of a branch, and sets the branch address in the microinstruction pointer. A microprogram control device comprising: