JP2001229075A - Bi-endian multi-instruction length executing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute two endian modes with multi-instruction length by the same encode circuit. SOLUTION: In multi-instruction length executing method for supporting multi-instruction length in two modes, that is, a big endian mode and a little endian mode, continuous short instructions are always stored in an instruction storage area as a pair of former and later instructions according to the log instructions in the area regardless of the two endian modes, and the order of reading is executed as the order of former and later instructions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an apparatus for handling different endians, and more particularly to an information processing apparatus for storing and executing a program on a memory having an address in a byte unit.

[0002]

2. Description of the Related Art Information processing that has both a mode that operates in a big endian addressing mode and a mode that operates in a little endian addressing mode and that can switch the operation mode by an external setting or an internal setting. As the device, for example, there is a VR4100 microprocessor of NEC Corporation. VR41
00 ^TM 64-bit microprocessor
Manual (Document number U10050JJ1VOUM00
According to (first version)), all the command words defined in this information processing device have a fixed length of 32 bits (1 word). In this type of information processing apparatus, when an instruction stored in a memory is read out and the instruction is decoded, 32.
A bit-length instruction word will be supplied. The instruction read address specification specifies a word address.

FIG. 6 shows the memory address assignment in the big endian operation mode, and FIG. 7 shows the memory address assignment in the little endian operation mode. Respectively,
The word address is shown on the left side of the figure, and the byte address is written in each cell in the figure. In the figure, N represents a positive integer. Therefore, for example, 4 of instructions 1 to 4 having a 32-bit length
FIG. 8 shows an instruction sequence stored in the memory in the big-endian operation mode, and FIG. 9 shows an instruction sequence stored in the memory in the little-endian operation mode when trying to execute one. . It can be seen from FIGS. 8 and 9 that the word-addressed instruction in the big endian operation mode is the same as the word-addressed instruction in the little endian operation mode. Thus, in an information processing apparatus in which only 32-bit fixed-length instructions are defined, the instruction word reading and instruction decoding circuits can be completely shared between the big endian operation mode and the little endian operation mode. it can.

On the other hand, as an information processing apparatus in which a plurality of types of instruction word lengths are defined, for example, there is an M32R family microprocessor of Mitsubishi Electric Corporation. M32
According to the R-family software manual, in this information processing apparatus, two types of instruction word lengths of 16 bits and 32 bits are defined, and the word length of the instruction is identified by the value of the most significant bit of the instruction word. You. In this information processing apparatus, only the big endian operation mode is supported, and there is no operation mode in little endian.

Conventionally, there is no information processing apparatus in which both 32-bit instructions and 16-bit instructions are defined, and which support both big-endian and little-endian operation modes. In order to solve this problem, the user has to prepare a 32-bit instruction
When defining an information processing device that defines both bit-length instructions and supports both big-endian and little-endian operation modes, the address display method differs between big-endian mode and little-endian mode. Therefore, the following configuration is adopted. However, according to this configuration, the decoding processing speed of the instruction is reduced.

Hereinafter, this configuration and operation will be described in detail. FIGS. 4 and 5 are diagrams illustrating the format of an instruction defined by the information processing apparatus. FIG. 4 shows a format of an instruction executed by the information processing apparatus.
It consists of a bit length instruction. The 32-bit or 16-bit length is identified by the most significant bit in each instruction format. For example, when the most significant bit of the instruction word is a binary value “1”, a 32-bit instruction, “0” ", The instruction is a 16-bit length instruction. 7 below the most significant bit
Operation code (O) indicating the type of instruction with bits
P) is formed, and an operand or the like is designated by other bits. FIG. 5 shows two consecutive 16-bit instructions arranged in a 4-byte area on a word boundary. A 16-bit instruction always handles two instructions as one set. The most significant bit of the 16-bit instruction arranged in the lower 2 bytes can be used for software control or other hardware control. FIG. 5A shows that the most significant bit of a 16-bit instruction arranged in the lower 2 bytes has a binary value “0”.
FIG. 5B shows a case where 16 is arranged in the lower 2 bytes.
The case where the most significant bit of the bit length instruction is a binary value “1” is shown.

In this information processing apparatus, since instructions described in a program are allocated on a memory in the order of appearance, for example, a sequence of instructions in a program includes a 32-bit instruction, a 16-bit instruction, and a 16-bit instruction. When the instruction 3 is described in the order of 32-bit instruction 4 32-bit instruction 5, the instruction sequence stored in the memory in the big endian operation mode is as shown in FIG. Are as shown in FIG. In each operation mode, the arrangement on the memory to which the 32-bit instruction is allocated is the same, but the arrangement on the memory to which the 16-bit instruction is allocated is different. In the big endian operation mode, the 16-bit instruction 2 is arranged in the upper halfword of the word position, and the 16-bit instruction 3 is arranged in the lower halfword of the word position. In the little endian operation mode, the 16-bit instruction is arranged. 2 is the lower halfword of the word position, 16
Bit length instruction 3 is located in the upper halfword of the word position.

In general, the address of an instruction is represented by the first byte address of the instruction word, in other words, the byte address of the byte position of the smallest address in the instruction word, so that in the big endian operation mode and the little endian operation mode, The addresses of the individual instructions are exactly the same in FIG. 10 and FIG. The instruction address of 16-bit long instruction 2 is big endian operation mode,
4N in any of the little endian operation modes
The instruction address of the 16-bit long instruction 3 is 4N + 6 in any operation mode. That is, in the case of a 16-bit length instruction, the instruction words specified by the same address in the big endian operation mode and the little endian operation mode are arranged differently on the memory.

FIG. 12 shows an example of an instruction decoder circuit of an information processing apparatus for arranging such instructions. The endian indicating means 12 specifies the big endian operation mode when the logical value is 0, and specifies the little endian operation mode when the logical value is 1. The selection signal generation circuit 13 outputs an endian instruction signal 14 by the endian instruction means 12,
A selection signal 16 of the multiplexer 8 based on the most significant bit signal 15 indicating the instruction length identifier of the instruction word read from the memory and the control signal 7 indicating the halfword position of the instruction word output from the instruction decoder 5 Generate The control signal 7 is cleared to "0" when a new instruction word is loaded into the instruction register 1, and is set to "1" when decoding of the first 16-bit instruction is completed.
The multiplexer 8 selects an upper halfword or a lower halfword in the instruction register 1 based on the instruction of the selection signal generation circuit 13 and supplies the same to the instruction decoder.

FIG. 13 shows an input signal to the selection signal generation circuit 13 and an instruction decoder 5 selected by the multiplexer 8.
4 shows the relationship between the instruction word positions supplied to. In the case of a 32-bit instruction, bits 0 to 15 of the instruction register are supplied to the instruction decoder regardless of the instruction of the endian instruction means 12. That is, in this case, there is no need to switch the control signal of the multiplexer 8 when supplying the signal to the instruction decoder. On the other hand, in the case of a 16-bit length instruction, it is necessary to switch the control signal of the multiplexer 8 based on the endian instruction. First, in the case of the big endian operation mode, when an instruction word is loaded into the instruction register 1 and the control signal 7 becomes a value of “0”, a 16-bit instruction of an upper half word specified by a word boundary address, ie, Supply bits 0-15 of the instruction register to the instruction decoder. Also, in the little endian operation mode, when the instruction word is loaded into the instruction register 1 and the control signal 7 has a value of “0”, the lower half word 16-bit instruction specified by the address of the word boundary, ie, , Bits 16-31 of the instruction register to the instruction decoder. In this way, when selecting an instruction to be supplied to the instruction decoder, the multiplexer circuit is controlled using the instruction length identifier included in the instruction word itself, so that the delay time until the instruction is supplied to the instruction decoder increases. Processing speed decreases.

[0011]

A conventional apparatus for supporting two instruction lengths and supporting two endian operation modes is configured as described above. That is,
In an information processing apparatus having an instruction format of a plurality of different lengths, an instruction decoding process is performed based on an instruction length identifier placed in an instruction word and an address where the instruction word is placed, but it operates in big endian. The information processing device that processes both the mode and the mode operating in little endian uses different address allocation methods depending on the mode, so that the instruction decoding circuit becomes complicated, and as a result, the processing speed is reduced. There is.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. The present invention deals with both instructions having a length of one and two times and simplifies the configuration when processing both endian operation modes, and achieves high-speed processing. Plan.

[0013]

A bi-endian multiple instruction length execution method according to the present invention is an instruction execution method that supports multiple instruction lengths in two modes, big-endian and little-endian. Regardless of the endian mode, consecutive short instructions are always stored as a set of first and second instructions that match the long instruction of the area, and the reading order is executed in the order of the first and second instructions.

Still further, when an instruction is executed in one endian mode, an instruction address is obtained by changing a part of a program counter in the other endian mode.

Still further, for a set of short instructions,
Instruction decoding is performed immediately after the short instruction.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 4 shows an instruction format supported by the instruction execution method according to the present invention;
In this example, it consists of a 32-bit instruction and a 16-bit instruction. The 32-bit or 16-bit length is identified by the most significant bit in each instruction format. For example, when the most significant bit of the instruction word is a binary value “1”, a 32-bit instruction, “ In the case of "0", it is a 16-bit length instruction. An operation code (OP) representing the type of instruction is formed by the seven bits below the most significant bit, and the other bits specify an operand or the like. FIG. 5 shows two consecutive 16-bit instructions arranged in a 4-byte area on a word boundary. In the present invention, a continuous 16-bit instruction always includes two instructions as one set. deal with. In addition, these two 16-bit instructions have the upper 2 bits regardless of the big endian and little endian operation modes.
The instruction arranged in the byte is executed first, and the instruction arranged in the lower two bytes is executed later. The most significant bit of the 16-bit instruction arranged in the lower 2 bytes can be used for software control or other hardware control. FIG. 5 (a) shows the lower 2
The most significant bit of the 16-bit instruction placed in the byte is 2
FIG. 5B shows the case where the binary value is “0”, and the most significant bit of the 16-bit instruction arranged in the lower 2 bytes is the binary value “1”.
Shows the case of

FIGS. 1 and 2 show the relationship between an instruction sequence arranged on a memory and a program counter value when each instruction is executed. In these examples, only the lower 4 bits are described for the program counter to simplify the description. The program counter indicates the position of the instruction being executed, and a general information processing device holds the address of the instruction being executed. The program counter in the present invention is expressed not as the instruction address itself but as a combination of a word address portion of the instruction and half word position information in the same word as the instruction position information. That is, the lower 2 of the program counter
When the bit is “00”, it indicates the execution of a 32-bit instruction or a 16-bit instruction stored in the upper halfword of a word. When the lower two bits of the program counter are “10”, the lower halfword of the word is executed. Indicates the execution of a stored 16-bit instruction. Therefore, in the big endian operation mode, the address of the instruction being executed and the program counter value completely match, and in the little endian operation mode, the value of the lower two bits is inverted between the program counter value and the instruction address when the 16-bit instruction is executed. . Although this method is a simple method of always executing the upper half first in a word in the two modes, the upper half may be always executed by another logic.

More specifically, in the big endian operation mode of FIG.
When the bit-length instruction A is executed, the program counter value is "0
000 ", the program counter value at the time of execution of the 16-bit instruction B located at address 4-5 is" 0100 ",
The program counter value at the time of execution of the 16-bit length instruction C located at the address 6-7 is “0110”. Next, in the little endian operation mode of FIG.
The program counter value at the time of executing the 32-bit instruction A located at addresses 0 to 3 is “0000”,
The program counter value at the time of execution of the 16-bit instruction C located at −5 is “0110”, and the program counter value at the time of execution of the 16-bit instruction B located at address 6-7 is “0100”. The upper two bits of the program counter indicate the word address where the instruction is located, and the lower two bits indicate the halfword position in the same word. Regardless of whether the operation mode is the big endian operation mode or the little endian operation mode, when the lower 2 bits are “00”, the lower 2 bits represent the upper half word in the word, and the lower 2 bits are “10”.
Represents the lower halfword in a word. The instruction execution order in program execution is defined by the operation of the program counter. Normally, unless an instruction for changing the program execution sequence such as a branch instruction is executed, the program counter is sequentially incremented to sequentially execute an instruction sequence continuously arranged on the memory. Generally, the program counter value specifies the memory address of the instruction to be executed.
By using the bit as the identifier indicating the halfword position in the word of the instruction instead of the address of the instruction, the increment control of the program counter can be common in the big endian operation mode and the little endian operation mode. 1 and 2, the transitions of the addresses of the instructions executed in both operation modes are different, but the transitions of the program counter value are the same, and therefore the instruction execution order in both modes is the same. Thus, in both the big-endian operation mode and the little-endian operation mode, the instruction execution order is A,
The order can be B, C, D, E, F.

FIG. 3 is a diagram showing an example of an instruction decoding circuit configuration used in the present invention. Conventionally, such a circuit could process only one instruction length even if both modes were supported, but this embodiment can support two instructions. In the figure, an instruction register 1 stores a 32-bit instruction word read from a word position in a memory 3 specified by an instruction address register 2 via a 32-bit data bus 4. When the read instruction word is 32 bits long, one instruction is stored in the instruction register, and when the read instruction word is 16 bits long, two instructions are stored. When an instruction word is set in the instruction register 1, the instruction decoder 5 first takes in the most significant bit, and if the value is "1", the instruction is a 32-bit instruction, and the value is "0".
Then, it is determined that two 16-bit instructions are set. Next, the instruction decoder 5 outputs an OP composed of the following 7 bits.
The code section is taken in, the type of the instruction is determined, and a control signal defined for each instruction is generated. The determination of the instruction length and the determination of the instruction type may be performed simultaneously.

Hereinafter, a specific operation will be described with reference to the instruction sequence shown in FIG. 1 and FIG. 2, and the operation of the circuit will be the same in the big endian operation mode and the little endian operation mode. However, in FIGS. 1 and 2, only the lower 4 bits are described for the program counter and the instruction address. Therefore, only the 4 bits are described for the address and the program counter value in the following description.

The operation in the big endian operation mode will be described with reference to FIG. First, the address “0000” is set in the instruction address register 2 and 3
Load the 2-bit instruction (A) into the instruction register 1.
At this time, the program counter is also set to "0000". Bits 0 to 15 of the instruction register 1 are supplied to the instruction decoder 5 via the multiplexer 8, and the instruction is decoded. In this case, since the instruction is a 32-bit instruction, the instruction decoder 5 increments the word address stored in the instruction address register 2 by the instruction of the control signal 6 and reads the instruction from the next word position “0100” on the memory. Give instructions to The instruction decoder 5
Is the control signal 9 when the 32-bit instruction (A) is executed.
Is generated, and the word address portion of the program counter 11 (in this description, the upper 2 bits of the 4-bit configuration)
Is incremented to “0100”.

Next, from instruction address "0100" to 16
The instruction word in which the bit length instruction (B) and the 16 bit length instruction (C) are packed is read and loaded into the instruction register 1. The lower two bits of the program counter indicate the halfword position of the instruction word. In this case, since it is "00", the upper halfword is specified. Therefore, bits 0 to 15 of the instruction register 1 are supplied to the instruction decoder 5 via the multiplexer 8, and the 16-bit instruction (B) is decoded. In this case, since the first instruction to be executed is a 16-bit instruction, the instruction decoder 5 does not issue an instruction to increment the instruction address register 2, sends a control signal 7 to the instruction register 1, and It instructs the instruction decoder 5 to input the 16-bit instruction (C) stored in bits 16-31 of the register 1. The instruction decoder 5 is 1
At the time of execution of the 6-bit instruction (B), a control signal 10 is generated, and a halfword position portion of the program counter 11 (the lower 2 bits of a 4-bit configuration in this description)
Is incremented to “0110”.

Next, bits 16-31 of the instruction register 1
Is supplied to the instruction decoder 5 via the multiplexer 8, and the 16-bit instruction (C) is decoded. In this case, because of the 16-bit instruction executed second,
The instruction decoder 5 increments the word address stored in the instruction address register 2 according to the instruction of the control signal 6, and instructs to read the instruction from the next word position "1000" on the memory. The instruction decoder 5 generates the control signal 9 at the time of executing the 16-bit length instruction (C), increments the word address portion of the program counter 11 (the upper 2 bits of the 4-bit configuration in this description), and , The control signal 10 causes a half word address portion (in this description, the lower two
(Bit) is cleared to "1000". Thereafter, the subsequent 16-bit instruction (D), 16-bit instruction (E), and 32-bit instruction (F) are similarly executed.

Next, the operation in the little endian operation mode will be described with reference to FIG. First, the address “0000” is set in the instruction address register 2 and the memory 3
Then, the 32-bit instruction (A) is loaded into the instruction register 1. At this time, the program counter is also set to "0000". In this case, since the instruction is a 32-bit length instruction,
The instruction address matches the program counter value. Bits 0 to 15 of the instruction register 1 are supplied to the instruction decoder 5 via the multiplexer 8, and the instruction is decoded. In this case, since the instruction is a 32-bit instruction, the instruction decoder 5 increments the word address stored in the instruction address register 2 by the instruction of the control signal 6 and reads the instruction from the next word position “0100” on the memory. Give instructions to The instruction decoder 5 generates the control signal 9 at the time of executing the 32-bit instruction (A),
The word address portion of the program counter 11 (the upper two bits of the 4-bit configuration in this description) is incremented to “0100”.

Next, from instruction address "0100" to 16
The instruction word in which the bit length instruction (B) and the 16 bit length instruction (C) are packed is read and loaded into the instruction register 1. The instruction address “0100” indicates a 16-bit instruction (C), but the lower two bits of the program counter indicate a halfword position of the instruction word. A 16-bit instruction (B) is specified as an execution target. Therefore, bits 0 to 15 of the instruction register 1 are supplied to the instruction decoder 5 via the multiplexer 8, and the 16-bit instruction (B) is decoded. In this case, since the first instruction to be executed is a 16-bit instruction, the instruction decoder 5
Sends a control signal 7 to the instruction register 1 without issuing an instruction for incrementing the instruction address register 2, and instructs the 16-bit instruction (C) stored in bits 16-31 of the instruction register 1 via the multiplexer 8 to the next instruction. The decoder 5 is instructed to input. The instruction decoder 5 is 1
At the time of execution of the 6-bit instruction (B), a control signal 10 is generated, and a halfword position portion of the program counter 11 (the lower 2 bits of a 4-bit configuration in this description)
Is incremented to “0110”.

Next, since the lower two bits of the program counter are "10", a 16-bit instruction (C) of a lower half word corresponding to the instruction address "0100" is designated as an execution target. Therefore, the bits 16-31 of the instruction register 1 are supplied to the instruction decoder 5 via the multiplexer 8, and the 16-bit instruction (C) is decoded. In this case, since the instruction is the second 16-bit instruction to be executed, the instruction decoder 5 increments the word address stored in the instruction address register 2 according to the instruction of the control signal 6, and sets the next word position "1000" in the memory. ”To read the instruction. The instruction decoder 5 generates the control signal 9 at the time of executing the 16-bit length instruction (C), and outputs the control signal 9 to the program counter 11.
By incrementing the word address portion (the upper 2 bits of the 4-bit configuration in this description) and clearing the half word address portion (the lower 2 bits in this description) by the control signal 10.
000 ". Thereafter, the subsequent 16-bit instruction (D), 16-bit instruction (E), and 32-bit instruction (F) are similarly executed.

As described above, the operation of the instruction decode circuit is exactly the same in both the big endian operation mode and the little endian operation mode, and a common instruction decode circuit can be used in both modes.

In the instruction execution method according to the present invention, when storing the instruction in the instruction storage area, the instruction is stored as a set in the upper half of one word regardless of both modes, and the instruction word is read from the memory to decode the instruction. When starting, the upper half (16 bits) of the instruction register is transmitted to the instruction decoder regardless of the big endian operation mode and the little endian operation mode, and irrespective of the value of the instruction length identifier placed in the instruction word. Therefore, the overhead of determining the bit position to be supplied to the instruction decoder can be eliminated, and the speed of instruction decoding can be increased. In the case where two 16-bit instructions are stored in the instruction register, an instruction to supply a subsequent 16-bit instruction to the instruction decoder is performed in advance at the time of decoding the first 16-bit instruction. There is no delay in the decoding processing time of the subsequent 16-bit instruction. It is clear that the same method can be used even when the instruction length is two bits of 64 bits and 32 bits.

The set of individual 32-bit instructions and two sets of 16-bit instructions packed into 32 bits are located at the same word boundary address in the big endian operation mode and the little endian operation mode. The circuit configuration is shared, and does not require a circuit overhead for absorbing a difference between modes. Therefore, the circuit structure is simplified and the decoding processing performance is improved.

[0030]

As described above, according to the present invention, the storage order of short instructions in the instruction storage area is made the same in the two modes by using the conventional decoding circuit supporting one mode, and the read order is also reduced. Since the order is the order, there is an effect that the decoding circuit is simple and there is no delay in the execution of the instruction.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of an instruction sequence, a counter, an address, and an execution order in a big endian arranged on a memory according to Embodiment 1 of the present invention;

FIG. 2 is a diagram showing an example of an instruction sequence, a counter, an address, and an execution order in little endian arranged on a memory according to the first embodiment;

FIG. 3 is a diagram illustrating an example of an instruction decode circuit according to the first embodiment;

FIG. 4 is a diagram illustrating a configuration of two instructions supported by the present invention.

FIG. 5 is a diagram illustrating a configuration of two short instructions supported by the present invention.

FIG. 6 is an instruction arrangement diagram on a memory in a general big endian.

FIG. 7 is an instruction arrangement diagram on a memory in general little endian.

FIG. 8 is a diagram showing an instruction arrangement on a memory in a conventional big-endian fixed-length instruction.

FIG. 9 is a diagram showing an instruction arrangement on a memory in a little-endian manner of a conventional fixed-length instruction.

FIG. 10 is an instruction arrangement diagram on a memory in a conventional big-endian mode supporting both modes.

FIG. 11 is a diagram illustrating an instruction arrangement on a memory in a conventional little-endian mode supporting both modes.

FIG. 12 is a diagram of a conventional instruction decoding circuit supporting both modes.

FIG. 13 is a diagram illustrating an instruction word selection method of a conventional instruction decode circuit.

[Description of Signs] 1 instruction register, 2 instruction address registers, 3 memories, 4 instruction decoders, 8 multiplexers, 11
Program counter.

Claims (3)

[Claims] 1. An instruction execution method for supporting a plurality of instruction lengths in two modes, big endian and little endian, wherein a continuous short instruction is always stored in an instruction storage area regardless of the two endian modes. A bi-endian multiple-instruction-length execution method, characterized in that the instruction is stored as a first / last pair according to an instruction, and the read order is executed in the first / last order. 2. The method according to claim 1, wherein the instruction execution in one endian mode is performed by changing a part of a program counter in the other endian mode to obtain an instruction address. Endian multiple instruction length execution method. 3. The method according to claim 1, wherein the instruction decoding is executed immediately after the short instruction in the set.