JPH03252845A - Address control system - Google Patents

Abstract

PURPOSE:To secure the connection of plural same units and the simultaneous connection of the units having the addresses overlapping with each other by designating the units based on the addresses produced from a host processor and performing the address conversion for each unit. CONSTITUTION:A host processor 1 outputs an address to an address signal line 2, and a unit designating circuit 3 selects a unit based on the address inputted through the line 2 to designate the selected unit via a unit designating signal line 11. An address conversion circuit 7 converts the address inputted from the line 2 into an internal address of a unit 4. An address decoding circuit 8 decodes the internal address of the unit 4, and a selected register 9 is designated by a register designating signal 10. The units 5 and 6 have the same internal constitutions as that of the unit 4. Thus it is possible to secure the connection of plural same units and the simultaneous connection of the units having the addresses overlapping with each other.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an address control method, and more particularly to a method for decoding and converting address codes generated by a host processor.

[Conventional technology]

Conventionally, in the address control method, an address code generated by a host processor is output directly to a bus, and each unit specifies a register, etc. by directly decoding the address code on the bus.

[Problem to be solved by the invention]

In the conventional address control method described above, each unit directly decodes the address code generated by the host processor, so all address mappings for each package must be individual addresses, making it difficult to implement two or more identical units. However, it is not possible to simultaneously implement units that have the same address mapped to them, resulting in a lack of system flexibility.

[Means to solve the problem]

The address control method of the present invention includes means for specifying a unit from an address code generated by a host processor, means for converting the address code generated by the host processor into a unit internal address code for each unit,
It is characterized by comprising means for decoding the converted address code and specifying a predetermined register or the like.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. In the figure, the host processor 1 outputs an address to address signals 1!2, and the unit designation circuit 3 outputs an address to the address signal line 2.
Select one unit from the input address,
The unit designation signal line 11 is used to designate the selected unit.

The address conversion circuit 7 converts the address input from the address signal line 2 into an internal address of the unit 4, and the address decode circuit 8 decodes the internal address of the unit 4 and designates the register 9 selected by the register designation signal 10. Unit 5. Unit 6 also has the same internal configuration as unit 4.

〔Effect of the invention〕

As described above, the present invention specifies a unit from an address generated by a host processor and performs address conversion for each unit, thereby making it possible to connect a plurality of the same units or to connect units with overlapping addresses simultaneously.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention. 1... host processor, 2... address signal line,
3...Unit designation circuit, 4,5.6...Unit, 7...Address conversion circuit, 8...Address decoding circuit, 9...Register.

Claims (1)

[Claims] means for specifying a unit from an address code generated by the host processor; means for converting the address code generated by the host processor into a unit internal address code for each unit; and means for decoding the converted address code and storing it in a predetermined register, etc. An address control method comprising means for specifying.