JPS60249451A - クロツク位相誤差検出器 - Google Patents

クロツク位相誤差検出器

Info

Publication number
JPS60249451A
JPS60249451A JP59105749A JP10574984A JPS60249451A JP S60249451 A JPS60249451 A JP S60249451A JP 59105749 A JP59105749 A JP 59105749A JP 10574984 A JP10574984 A JP 10574984A JP S60249451 A JPS60249451 A JP S60249451A
Authority
JP
Japan
Prior art keywords
signal
clock
sampler
value
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59105749A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0535617B2 (enExample
Inventor
Junji Namiki
並木　淳治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59105749A priority Critical patent/JPS60249451A/ja
Publication of JPS60249451A publication Critical patent/JPS60249451A/ja
Publication of JPH0535617B2 publication Critical patent/JPH0535617B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0334—Processing of samples having at least three levels, e.g. soft decisions

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP59105749A 1984-05-25 1984-05-25 クロツク位相誤差検出器 Granted JPS60249451A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59105749A JPS60249451A (ja) 1984-05-25 1984-05-25 クロツク位相誤差検出器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59105749A JPS60249451A (ja) 1984-05-25 1984-05-25 クロツク位相誤差検出器

Publications (2)

Publication Number Publication Date
JPS60249451A true JPS60249451A (ja) 1985-12-10
JPH0535617B2 JPH0535617B2 (enExample) 1993-05-27

Family

ID=14415894

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59105749A Granted JPS60249451A (ja) 1984-05-25 1984-05-25 クロツク位相誤差検出器

Country Status (1)

Country Link
JP (1) JPS60249451A (enExample)

Also Published As

Publication number Publication date
JPH0535617B2 (enExample) 1993-05-27

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