JPS60249431A - Ad converter device of bit extension system - Google Patents

Abstract

PURPOSE:To extend easily the number of bits by constituting two stages of flush circuits and holding down the joint bit error of a connection part between two stages of these circuits to a small value. CONSTITUTION:An analog input signal Vin is inputted to a proportional adding circuit 5 of a flush circuit C1 for conversion of upper bits through a buffer amplifier 9. The difference between the output signal of the proportional adding circuit 5 and the input signal Vin which passes a delay element 4 is detected and amplified by a differential amplifier 6. The output of the differential amplifier 6 is impressed to a lower bit flush circuit C2 through an AD converter 7, and upper bits and lower bits are latched in latch circuits 3 and 8 respectively, and timings of upper bits and lower bits are matched to each other and they are synthesized by a clock circuit 18 and a delay element 19. Thus, the number of upper bits and the number of lower bits are selected optionally, and a high- precision A/D converter is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an AD (analog-digital) converter device capable of expanding the number of bits.

[Conventional technology 1] In a conventional high-speed AD converter, a number (2"-1) of humpparators are arranged in parallel to satisfy the desired resolution, and the level of the applied analog signal and (2"-1) are arranged in parallel. 1)
A parallel comparison type AD converter is mainly used, which performs AD conversion by simultaneously comparing and parallel polycycles with a predetermined divided reference voltage.

In addition, half of the desired number of bits is first AD converted by parallel comparison, and at the same time the upper bits are obtained, crystal (digital/analog) conversion is again performed, and by taking the difference with the input analog signal, an error signal is obtained. A cascade comparison type AD converter is also used in which this error signal is then AD converted into the remaining half bits to obtain the lower bits.

[Problem to be solved by the invention 1 However, in the above-mentioned parallel comparison type AD converter, the number of humpparators and the elements required in conjunction therewith is (2).
``-1)'' The problem is that the size is almost the same as that of the ``-1'' group, and it is difficult to increase the bit rate.

In addition, in the above cascade comparison type AD converter, the AD conversion output from the upper bit does not match the input analog signal in timing due to the time delay caused by the time it takes to pass through the comparison circuit and the AI conversion circuit. This causes an error when taking the difference. Therefore, hold the analog signal temporarily (
The problem is that a high-speed sample-and-hold circuit that requires advanced technology to maintain (hold) is required, and it is difficult to increase the speed.

The present invention aims to solve these problems by using a two-stage flash type circuit configuration, and by making it possible to suppress the joint bit error between the two stages of this circuit to a small amount. It is an object of the present invention to provide a bit number expansion type AD converter device that allows the bit number to be expanded.

[Means for solving the problem 1 For this reason, the bit number expansion 2 of the present invention)\D converter device receives the input analog signal and expands the number of bits according to the number n (n is an integer of 2 or more). 11 to output digital signals
An upper bit circuit consisting of a bit comparison circuit, an encoder that receives digital signals from the 11-pin comparison circuit, and a second-order bit launch that holds the output from the encoder is provided, and a a DA converter that adds appropriate weights to the digital signals and outputs the corresponding analog signals;
''; a delay element that delays the input analog signal by a predetermined time; a differential amplifier that receives the outputs from the DA converter and the delay element; and a differential amplifier that receives the intermediate analog signal from the differential amplifier and calculates the number of bits m ( The present invention is characterized in that it is provided with a lower bit circuit consisting of an AD converter that outputs a digital signal (m is an integer of 2 or more) and a latch for lower bits that holds the output from the AD converter.

1 Effect 1 With the above configuration, the 11-bit comparison circuit, encoder, and upper focus latch output the upper 11 bits, and the delay element causes the input analog signal to be output from the 11-bit comparison circuit and the 11-bit comparison circuit and the upper focus latch. ) The timing input to the differential amplifier via the A converter and the timing input to the differential amplifier via the delay element are matched, and at the same time, the timing input from the DA converter to the differential amplifier is matched. The error is reduced by the output, and then the AD converter and lower bit latch which receive the signal from the differential amplifier output the lower 10 bits.

[Embodiment] Hereinafter, a bit number expansion type AD converter device as an embodiment of the present invention will be explained with reference to the drawings. Fig. 1 is a block diagram showing its overall configuration, and Fig. 2 shows its 11-bit comparison circuit. FIG. 3 is an internal configuration diagram showing the DA converter, FIG. 4 (a) to (e), and FIG. 5 (a).
, (+1), and FIG.

As shown in FIG. 1, an upper 11-bit circuit C1 for the number of bits to be expanded to 11 is provided, and a lower m-bit circuit C2 is provided, and these circuits CI
, C2 form a two-stage flash circuit.

Here, Ill and 11 are integers greater than or equal to 2.

By the way, the upper 11 pinto circuits C1 are 11-bit comparison circuits 1. The lower m-bit circuit C2 includes an enhancer (encoder) 2 and a latch 3 for upper bits, and a delay element 4. , Proportional addition circuit as a DA converter5.
Differential amplifier6. It is equipped with an AD converter 7 and a latch 8 for lower focusing.

11-bit comparison circuit] receives the input analog signal Vin via the buffer amplifier 5j and expands the number of bits to 11.
The internal configuration is shown in FIG. 2. That is, this 11-bit comparator circuit 1 includes n'(=2''-1) hump parators 11-1, 11-2, 11-3, .
1-n' and n'(=2" 1) resistors R that supply appropriate reference voltages to the input terminals of each comparator.
11R21R31...ffRI+'.

In addition, each resistor Rl lR21R: l + "' IR
I+' are connected in series, and one end of the resistor group connected in series in this way is connected to the reference voltage source 13 (see FIG. 1) via the terminal 12, and 11I! The ends are 7-stamped.

Further, the encoder 2 is a circuit that encodes the binary code from the 11-bit comparator circuit 1 into an n-bit binary signal, and the latch 3 for upper bits is a circuit that encodes the binary code from the 11-bit comparator circuit 1 into an n-bit binary signal.
This is a circuit that temporarily stores (retains) the advance signal.

Furthermore, the proportional addition circuit 5 adds appropriate weights to the binarized signals from the 11-bit comparison circuit 1 and outputs an analog signal corresponding to this, and its internal configuration is as follows.
It is as shown in Figure 3. In other words, this proportional addition circuit 5 includes a transistor current switching circuit 15 comprising a current switching transistor TrllTr2 and a constant current source 14.
-1.15-2. ..., is -n' and these transistor current switching circuits 15-1.15-2+.
. . A current-voltage conversion circuit 17 is provided which outputs from a terminal 16 a voltage signal in the form of a staircase waveform which receives current outputs from +15-n' and adds them proportionally.

The delay element 4 has an input analog signal of n bits in the comparison circuit 1.
and the timing input to the differential amplifier 6 via the proportional addition circuit 5 and the timing input to the differential amplifier 6 via the same delay element l[. This is for extracting the error signal between the staircase waveform and the input analog waveform.

Furthermore, the AD converter 7 is a ready-made m-via high-speed AD converter, and the lower bit latch 8 is a circuit that temporarily stores (holds) the m-bit binary signal from the AD converter 7. be.

Note that the clock signal is compared with the comparison circuit 1. A clock circuit 18 for supplying the signals to the latches 3 and 8 is also provided to keep these timings. For reference, timing charts of each part are shown in FIGS. 6(a) to (1n).

Here, FIG. 6(a) shows the clock pulse for the 11-bit comparison circuit, FIG. 6()]) shows the I]bit comparison circuit input analog signal, and FIG. Figure 6(d) is the encoder output signal, Figure 6(e) is the latch clock pulse for the upper bit, Figure 6(f) is the latch output signal for the upper bit, and Figure 6(g) is the proportional addition circuit output analog. 6(I) is the delay element output analog signal, FIG. 6(1) is the differential amplifier output intermediate analog signal, FIG. 6(j) is the A I) converter clock pulse, FIG. k) is the AD converter output signal, Fig. 6 (σ)
is the latch clock pulse for the lower bit, Fig. 6(,n)
indicate the launch output signals for lower bits, respectively.

Further, reference numeral 20 in the second M is a comparator which receives a clock signal from the clock circuit 18] I-1, ll-
2°J'l-3, . . . , terminals for supplying this clock signal to the clock circuits 11n' are shown.

With the above configuration, the analog signal Vin is sent from the analog input terminal through the buffer amplifier 9 to the 11-pin comparison circuit 1.
added to. In this 11-bit comparator circuit 1, each of the hump parators 11-1.31-2.11-
The input analog signal and each reference voltage are compared by 3゜...+11-n', and the 2 corresponding to the input analog signal is
A value code is output.

Here, the 11-bit comparator circuit 1 functions to divide the entire operating range of the input voltage into 2 to the power of the number of points to be expanded.

Then, the binary code from the comparison circuit 1 is encoded into a binary code by the encoder 2, and temporarily stored in the latch 3 as 11 bits of the 1st-order.

In addition, the binary values of the output of the 11-focus comparison circuit 1 are multiplied by a weight corresponding to each reference voltage by the proportional addition circuit 5, and then added together, iz, and transformed into a staircase waveform corresponding to the input analog signal I'! /! and sent to the differential amplifier 6.

Here, as shown in FIG. 3, the proportional addition circuit 5 uses the outputs of the comparators 11-1, 1]-2, 11-3°, . Switching circuit 15-1.15-2.15-3
.

On the other hand, in order to obtain an error signal between the staircase waveform and the input analog waveform at the same point in time, the analog signal output from the buffer amplifier is passed through the delay element 4, delayed by the time required to pass through the comparison circuit 1 and the proportional addition circuit 5, and the difference is Add to the dynamic amplifier 6.

That is, the delay element 4 matches the timing of the signal input to the differential amplifier 6 via the comparison circuit 1 and the proportional addition circuit 5 with the timing of the signal input to the differential amplifier 6 via the delay element 4. act.

The error signal obtained in this way is AD converted by a ready-made high-speed AD converter 7 and sent to the lower bit lunch (3).
AD converted by outputting 11 bits at the same time,
An all-bit signal expanded by 11 pins can be obtained.

In addition, as a commercially available 1-chip AD converter, 2; Bin Y
Since it is easy to obtain, we prototyped an 8-pin AD converter with only 2 pins extended, and the bit output and human output characteristics of this are as follows:
It became like the figure.

Figures 4(a) to (e) show input voltages ranging from 0 to 0 in ascending order.
MS B when changed up to 3 (V), No. 9.8, 6
．． Part of the 4-focus output is shown.

In addition, Fig. 5(a), <11) shows the input/output characteristics when a linearly increasing voltage is AD converted by this device and its output is decoded by a 1 () bin) DA converter. (,) shows an input sweep waveform diagram, and FIG. 5(1)) shows a decoded waveform diagram.

In this way, in order to expand the number of bits by 11 for a 1n-bin AD converter and make the number of pinpoints Ill + n, it is necessary to All you have to do is add a circuit, and it can be configured without using a sample-and-hold circuit, so even if you cannot obtain a high-bit 1-chip AD converter, you can easily expand the focus and achieve the desired high-speed AD conversion. You can get a vessel.

[Effect of the Invention 1] As detailed above, the bit number expansion type AD converter device of the present invention receives an input analog signal and converts it into a digital signal corresponding to the number of bits II (I+ is an integer of 2 or more) to be expanded. The 3rd bit circuit consists of a +1 bit comparison circuit that outputs a signal, an encoder that receives the digital signal from the +1 bit comparison circuit, and a latch for the 1st bit that holds the output from the encoder and -der. Along with being established,
a DA converter that adds the digital signals from the r1 bit comparison circuit with appropriate weights and outputs a corresponding analog signal; a delay element that delays the input analog signal by a predetermined time; A differential amplifier receives the output from the converter and the delay element, and receives the intermediate analog signal from the differential amplifier and calculates the number of focuses (m).
is an integer greater than or equal to 2).\I
) converter and a lower bit circuit consisting of a latch for the F-order bit that holds the output from the AI) converter.The simple two-stage flash circuit configuration has a simple two-stage flash circuit configuration that includes a low-order bit circuit consisting of a latch for the F-order bit that holds the output from the AI) converter. It has the advantage that the number of bits can be expanded easily and with low power consumption while suppressing errors.

[Brief explanation of the drawing]

The figures show a bit number expansion type A/D converter device as an embodiment of the present invention, FIG. 1 is a block diagram showing its overall configuration, and FIG. 2 is an internal configuration showing its r-bit comparison circuit. Figure 3 is an internal configuration diagram showing the DA converter, Figure 4 (a) - (eL Figure 5 (a), (b) and Figure 6 (a) - (珀) are all the internal configuration diagrams of the DA converter. This is a graph for explaining the action. 1. I+ bit comparison circuit, 2. Encoder, 3.
Upper bit latch, 4...Delay element, 5...Proportional addition circuit as D'A converter, 6...Differential amplifier, 7...
AD converter, 8... Latch for lower bits, 9... Banff 7 amplifier, 1()... Input terminal, ] 1-1.1 ]-
2,1]-3,11-n'... Comparator, 12.
・Terminal, 1″A...Reference voltage source, 1.1...Constant current source,
15-ko,] 5-2.15-11'...Current switching circuit, 16...Terminal, 17...Current voltage conversion circuit, 18
...Clock circuit, 1...Delay element, 2()...Terminal, C1...-L focus circuit, C2...Lower bit circuit, RIIR21R,, Rn'...Resistance. Agent Patent Attorney Yoshihiko Iinuma Figure 1 Old 19 Figure 2 Figure 3 Figure 7 Figure 4 Figure 6 (m) 2 ■ D

Claims (1)

[Claims] An n-bit comparison circuit that receives an input analog signal and outputs a digital signal according to the number of bits to be expanded, n (n is an integer of 2 or more), an encoder that receives a digital signal from the +1-bit comparison circuit, and the encoder. A DA converter is provided with an upper bit circuit consisting of a latch for upper bits that holds the output from the n-bit comparison circuit, and adds the digital signals from the n-bit comparison circuit with appropriate weights, and outputs an analog signal corresponding to the digital signals. and a delay element that delays the input analog signal by a predetermined time;
A differential amplifier that receives the output from the above-mentioned DA converter and delay element, and an AD converter that receives the intermediate analog signal from the differential amplifier and outputs a digital signal with the number of bits m (II+ is an integer of 2 or more). and a lower bit circuit consisting of a lower bit latch that holds the output from the AD converter.
Transducer device.