JPS60247896A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent destruction or mis-reading of storage information and to attain high speed operation even if a delay time of a common source line of a differential amplifier circuit is large by operating a data line high potential compensating circuit or connecting the circuit to input/output lines after the amplified state of a data line is detected. CONSTITUTION:Two circuits DA1 whose output goes to a low level when a potential of a data line is lower than a reference level Vref1, a NAND circuit NAND1 inputting the output of the two circuits, and an AND circuit AND1 obtaining a NAND output, a pulse PHIs and an AND output are provided to a detection circuit 1. No AR is operated and input/output lines are not connected before the signal amplification by an SA is not executed sufficiently and the storage information is not destructed and no mis-read is caused. Since the AR operation and the connection with the input/output line are not delayed unnecessary, high speed memory operation is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device, and more particularly to a semiconductor device equipped with a circuit that stabilizes the operation when the charging/discharging time of a pair of data lines is long.

[Background of the invention]

In semiconductor devices, as the capacity increases, the wiring width becomes finer, so signal delay due to wiring resistance becomes a problem. That is, this delay appears as a malfunction of the memory array due to mismatch in operating speed of peripheral circuits. This will be explained using FIG.

FIG. 1 is a circuit diagram of a main part of a conventional dynamic memory configured with an 11-channel MO8. In the memory shown in FIG. 1, a read operation is performed as follows. First, the precharge signal ΦP is set to high level, and the precharge circuit PRC precharges the data line, D or the common lease line C'S of the differential amplifier circuit SA to high level, and the dummy cell 0M that generates the reference signal.
Set the node inside to ground potential. After that, after setting Φp to low level, the X decoder signal XD+.

Word line 1, for example W2, is selected by X D 2 etc.
A signal is output onto the data line from each memory cell MC connected thereto. At the same time, the X decoder signal XD+'
dummy word line DW2 selected by -XD2' etc.
A reference signal is output from each dummy cell DM connected to the data line n. Thereafter, the pulse Φ8 is set to a high level and the common lease line C8 of the SA is discharged to the ground potential, thereby operating the SA and amplifying the signal outputted to the data pair line. Then, a pulse Φ which is obtained by delaying the pulse Φ8 by a certain time by a delay circuit DLYC.
1, the data line high potential compensation circuit AR is operated and the data line on the high potential side (which is either D depending on the information of the memory cell) is boosted to the rewrite level. Further, the amplified signal is sent to the Y decoder Y D t −Y D
By applying the pulse Φa to the switch SW selected by ++a, etc., the human output line I10. The signal is output to I10 and taken out to the outside as a data output through various circuits. A write operation is also performed on the input/output lines I10. according to data input information applied from the outside. I10 is applied to a predetermined memory cell M through a selected switch SW.
written to C. Here, the pulse Φy is generated by the pulse ΦSa output from the delay circuit DLYC2 so as to rise a certain time after the pulse ΦS. In FIG. 1, Φ0 is a pulse that changes from a low level to a high level after the memory operation is completed.

The word line clear circuit WC discharges the selected word line and dummy word line to the ground potential.

Now, the following problem occurs in the memory shown in FIG. That is, in SA near the MOS transistor Q0 that discharges the common lease line C8 to the ground potential, the source side of SA immediately becomes a low potential, so that the data pair line D
1. Amplification of the signal on D+, ie, discharge of the data line, is performed quickly. On the other hand, Q. or in SA far from C.
The wiring resistance of 8 causes a delay in the time when the source side of SA becomes a low potential, and the amplification of the signal, that is, the discharge of the data line is delayed. Therefore, if the timing settings of Φ1 and ΦA are not appropriate, the operation of the high potential compensation circuit AR or the connection with the input/output line may occur before the signal is sufficiently amplified, causing destruction of stored information or erroneous reading. becomes. On the other hand, in the conventional technology, A
The design is such that the start of operation of R and the connection with the input/output line are sufficiently delayed by a delay circuit. However, this reduces the operating speed and makes it impossible to increase the operating speed.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device which can improve such conventional problems, prevent destruction and erroneous reading of stored information caused by delays due to resistance of a common source line, and which is capable of high-speed operation. be.

[Summary of the invention]

The present invention for achieving the above object is characterized in that the following operation is performed by detecting the actual pulse response of the data line or wiring equivalent thereto. More specifically, the discharge of the data line is detected, and the detected output is used to operate the data line high potential compensation circuit and connect it to the input/output line.

[Embodiments of the invention]

The present invention will be specifically explained below using examples.

FIG. 2 is a circuit diagram of a main part of a semiconductor device showing an embodiment of the present invention. Note that the memory array part CA indicated by the dotted line is the same as in FIG.

As shown in FIG. 2, in this embodiment, a new data pair line Dd y Dd is provided on the far side when viewed from the MoS transistor Qo, and one of the data lines is almost ov in this data pair line. A circuit 1 for detecting Φ is provided, and its output pulse is input to an AND circuit (ANDo) for generating drive pulses Φ1 and Φ of the data line high potential compensation circuit AR. The newly provided data pair lines Dd and Dd are the same as the data pair lines in the memory array CA, and the data line capacitance discharged by SA is made equal to that of the other data pair lines. Note that this data pair line is the input/output line I10. Since there is no need to make a connection to I10, the gate of switch SWa is connected to ground potential. Also, this data pair line Dd
, D-cho. The reason why it is placed on the far side is because the discharge of the data line at this position is delayed the most. Furthermore, as shown in FIG. 2, the detection circuit 1 includes a circuit DA, which outputs a low level (for example, A NAND circuit (which can be configured with a differential amplifier circuit) with the outputs of these two circuits as input.
Ds)- and an AND circuit (AND+) that obtains an AND output of the NAND output and pulse Φ8. Alternatively, depending on the design, circuit DA may be omitted and D
d y Dd can also be directly input to the NAND circuit. That is, the threshold voltage CII O of the circuit itself
pg Or II 1 @7 discrimination level) to Vref
It is used as This also applies to each of the following embodiments. According to this embodiment, the operation of the AR and the connection of the input/output lines are not performed before the signal is sufficiently amplified by the SA, and the stored information is not destroyed or read incorrectly. Also, unnecessary AR
Since there is no delay in the operation or connection with input/output lines,
High-speed memory operation becomes possible.

FIG. 3 is a circuit diagram of a main part of a semiconductor device showing another embodiment of the present invention. This example is based on the example shown in FIG.
It is detected by AR that either Dcl y D<1- has reached almost the rewriting level, and the detection output and pulse Φ. A circuit 2 is added which generates a signal for operating the word clear circuit WC by AND logic with the word clear circuit WC. As a result, in this embodiment, in addition to the effect shown in FIG. 2, word line discharge does not start before the rewrite level is sufficiently transmitted to the memory cells, and sufficient accumulated charge is always transferred to the memory cells. can be stored in

For example, as shown in the figure, the detection circuit 2 is a circuit DA2 (DA.

Similarly, for example, it can be configured with a differential amplifier circuit), and an OR operation m (OR2
), and A with this OR output and pulse ΦC as inputs.
It is difficult to configure it with an ND circuit (AND2).

In the embodiments shown in FIGS. 2 and 3, additional data pair lines DdlD are provided to prevent unnecessary loads from being connected to the data pair lines in CA, and also to prevent the connection of extra load to the data pair lines in CA. Although the layout of the connection part with the CA is made easy, the data pair line in the CA (however, the Q.

The data pair line on the farthest side from Dn, Dn in Figure 1
), or the detection circuit 1 may be connected to the other data pair line, for example, the data pair line furthest from the side to which the AR drive pulse Φ is applied (in Figure 1, D〒). 2 may be connected. This makes it possible to minimize the increase in area compared to the prior art (FIG. 1) and to obtain the effects described in FIGS. 2 and 3.

FIG. 4 is a circuit diagram of a main part of a semiconductor device showing another embodiment of the present invention. In FIG. 4, CA
The switch 5W (
The data line Dd is set to a high level through I, and the six terminals are connected to the ground potential, and these potentials are respectively written into the memory cells connected to the data line Dcl*Dd. Then, a circuit 3 is provided only on the data line Da side to detect that the level of the data line has become approximately Ov, and its output pulse is used to generate drive pulses Φ1 and ΦA for AR.
It is used as an input to an ND circuit (ANDO). In this embodiment, since the data line Dd always has a low potential, the circuit for detecting the potential of the data line is simpler than in the embodiment shown in FIG.

For example, as shown in FIG. 4, the detection circuit 3 has one circuit DA inputting the data line I)a, one complementary pulse of the pulse ΦS, and the output of the circuit DAI. NOP circuit (NOR3
). Further, depending on the design, D A t may be omitted and D d may be used as an input to the NOR circuit. The NOR circuit may also be constructed of the circuit shown in FIG. 9 or FIG. 11 of Japanese Patent Application No. 58-55012.

FIG. 5 is a circuit diagram of a main part of a semiconductor device showing still another embodiment of the present invention. In the embodiments shown in FIGS. 2 and 4, a new data pair line is provided and the potential of the data pair line is detected, but in FIG. A detection circuit 3 is provided at the far end of the common source line C8 (as viewed from the MoS transistor Q0) which is at the same potential, and detects that the potential has become approximately Ov.
The purpose is to operate the AR and connect it to input/output lines. According to this embodiment, the same effect as the embodiment shown in FIG. 2 or 4 can be obtained without providing a new pair of data lines.

FIG. 6 is a circuit diagram of a main part of a semiconductor device showing still another embodiment of the present invention. The embodiments shown in FIGS. 2 to 5 show examples of dynamic memories configured only with n-channel MO8, but FIG. 6 shows an example in which the present invention is applied to a dynamic memory using CMO8. . The figure shows a differential amplifier circuit S that amplifies the signal read out to the data line.
The circuit SC for shorting the AC and data lines is a different part from the CA shown up to FIG. 5. Note that in the same figure, the MOS transistor with an arrow is a p-channel MO8.
It is. Moreover, as shown in FIG. 4, the data pair line D d
+D d is newly added to CA, Dd is connected to high level and D is connected to ground potential through switch SWd. Further, D d + D cl is provided with a circuit 4 that detects that D has almost reached the rewrite level and that n7 has become almost ○■, and the output pulse is sent to an AND circuit for ΦA generation ( ANDO) input.

In the figure, the read operation is performed as follows. First, the precharge signal ΦP is set to high level, the short circuit SC connects the data line, and D is set to the intermediate level 1/2.
Initialize the VC. Thereafter, after setting Φp to a low level, a pulse is applied to the selected word line by the X driver XDR, and a signal is output from each memory cell connected to the selected word line to the data line. A dummy word line is selected when
A reference signal is output from each dummy cell connected to the other data line. Thereafter, the pulse Φ8 is set to a high level and the pulse i is set to a low level, the differential amplifier circuit SAC is operated, and the high potential side of the data line is charged and discharged to the high level Vc and the low potential side to the ground potential, respectively. Also, in the newly added data pair line Dd t Dd-, D
a is charged and discharged to the high level Vc, and Dd- is charged and discharged to the ground potential, and when the detection circuit 4 detects that they have been sufficiently charged and discharged, an output path is generated from the detection circuit 4, and the data line and I10 line are connected. connection is made.

In this way, in this embodiment, as in the embodiments described so far, it is possible to prevent erroneous reading when connected to the input/output line caused by a delay due to the resistance of the common source line C8 or the common drain line CD. Can be done. Furthermore, as shown in the figure, the data pair line D d r D d is SA
MOS transistor Q that drives C. It is necessary to arrange it on the far side when viewed from Qs.

For example, as shown in the figure, the detection circuit 4 has a data line 107.
and reference level Vref, as input circuit D A +
, data line DJ and reference level Vrefz are input,
A circuit DA2 whose output becomes a low level when the potential of Da becomes higher than Vrefz (the circuit DA shown in Fig. 3)
(However, if configured with a differential amplifier circuit, Da2 and τ7 can have the same circuit configuration, just having different output terminals), and a NOR with these outputs and pulse Φ8 as inputs. It can be configured with a circuit (NOR4). Also, depending on the design, D A I may be omitted and D
, i can be used as inputs of the NOR circuit as they are.

FIG. 7 is a circuit diagram of a main part of a semiconductor device showing still another embodiment of the present invention. In the embodiment shown in FIG.
Although transistors Qo and Q were operated almost simultaneously,
In the embodiment shown in FIG. 7, Qo is first operated, the detection circuit 5 detects that the low potential side of the meter wire is sufficiently discharged, and Q is operated using the output pulse Φss.
Charge the high potential side of the data line to the rewrite level.

Then, the detection circuit 6 confirms that the data line has been sufficiently charged to the rewrite level (that is, the data line Dd+
107 potential difference has been sufficiently amplified), and its output is used as an input to an AND circuit (AND, ) for generating Φy. According to this embodiment, since the n-channel and p-channel MoS transistors in the SAC, which have a common gate, are not turned on at the same time during signal amplification, the voltage between the power supply potential Vc and the ground potential flowing through one transistor is Through current can be prevented. Furthermore, since the signal is connected to the input/output line after it has been sufficiently amplified, erroneous reading can be prevented. For example, as shown in the figure, the detection circuit 5 receives the data line Dd and the reference level Vreft, which are always on the low potential side, as inputs, and the circuit DAI, and the output of the pulse below and DAI as inputs. It can be configured with an OR circuit (OR6) that outputs a low level when In addition, the detection circuit 6 receives the outputs of the complementary pulses 77 and DAz of the output pulse Φss of the circuit DA 2 and the detection circuit 5, which input the five data lines that are always on the high potential side and the reference level Vrefz. A as input
It can be configured with an ND circuit (ANDe). Also in the figure, DA may be omitted and Dd may be used as an input to the OR circuit, depending on the case.

Although several embodiments of the present invention have been described above, the scope of application of the present invention is not limited to the embodiments described here, and it goes without saying that various changes can be made without departing from the spirit of the invention. For example, here, the data pairs are arranged in memory cells (folded bits) where D is laid out close to each other.
Although we have shown examples of memories using ine arrangement or folded memory cells,
Data pair line, D is spatially separated cells (o
The present invention can be similarly applied to a memory using a pen bitline arrangement or an open type memory cell. Furthermore, in the embodiments shown in FIGS. 6 and 7, a memory array configuration in which the dummy cell DM is omitted is also possible.

〔Effect of the invention〕

As explained above, according to the present invention, after detecting the amplification state of the data line, the data line high potential compensation circuit is operated or connected to the input/output line, so that the common source of the differential amplifier circuit Even if the line delay time is large, destruction of stored information and erroneous reading can be prevented, and high-speed operation is possible.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of the main part of a conventional dynamic memory;
The figure is a circuit diagram of a main part of a semiconductor device showing an embodiment of the present invention.
Figures 3, 4, 5, and 6. FIG. 7 is a circuit diagram of a main part of a semiconductor device showing other embodiments of the present invention. 1.2, 3, 4, 5, 6...detection circuit, SA. SAC...read signal amplification circuit, AR...data line high potential compensation circuit, PRC...precharge circuit, D
M...Dummy cell, MC...Memory cell, CA...
・Memory main part, MA...Memory cell array, WC・
...Word clear circuit, XDR...X driver circuit,
IOG...input/output selection circuit, SC...short circuit, DA...differential amplifier circuit, CS...common source line,
CD... common drain line. %r Figure S3 Figure 14 Figure f Js Figure Waka 6 Figure

Claims (1)

[Scope of Claims] 1. A data line group, a word line group, and a memory cell group arranged at the defect of the data line and word line, and the voltage of the data line to which the signal of the memory cell is transmitted is In a semiconductor device having a detection amplification circuit for detecting and amplifying, and a high potential compensation means for charging the data line at a high potential after amplification to a predetermined voltage, the voltage amplification of the data line is detected and the high potential is increased by a detection output. A semiconductor device comprising a circuit for operating a compensation means. 2. Detection amplification, which has a data line group, a word line group, and a memory cell group arranged at the intersection of the data line and word line, and detects and amplifies the voltage of the data line to which the signal of the memory cell is transmitted. A semiconductor device having a circuit and a connection control means between an input/output line common to the data line group and the data line, further comprising a circuit that detects voltage amplification of the data line and operates the connection control means based on the detected output. A semiconductor device characterized by: