JP4179402B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a hierarchical bit line type semiconductor memory device.
In recent years, with the advancement of semiconductor technology, semiconductor memory devices have also been highly integrated and increased in capacity, and at the same time, there has been a demand for higher speed and lower power consumption. Therefore, it is desired to provide a semiconductor memory device capable of shortening the amplification time and power consumption by the sense amplifier in the memory cell array portion.
[0002]
[Prior art]
In recent years, semiconductor memory devices (for example, DRAM: Dynamic Random Access Memory) are being increased in capacity to 64 Mbits or 256 Mbits. As processing data becomes larger and peripheral devices become faster, there is an increasing demand for higher operating speeds for semiconductor memory devices. Further, not only when the semiconductor memory device is used in a battery-driven notebook personal computer or portable device, it is also important to reduce the power consumption of the semiconductor memory device.
[0003]
In order to satisfy such requirements, a hierarchical bit line type DRAM (semiconductor memory device) has been proposed. This hierarchical bit line method uses a multilayer metal wiring to divide the bit line into a global bit line and a local bit line made of polysilicon or polycide, and a transfer gate between the global bit line and the local bit line. Is to be provided. In the hierarchical bit line system, only the transfer gate in the memory cell array in which the accessed word line exists is opened (switched on) so that the bit line can be reduced in capacity and time constant. It has become.
[0004]
FIG. 10 is a circuit diagram showing an example of a semiconductor memory device as a related technique corresponding to the present invention. In the figure, reference numerals GBLX and GBLZ are global bit lines, LBL0X and LBL0Z; LBL1X and LBL1Z are local bit lines, WL is a word line, DBX and DBZ are data signal lines, TG0 and TG1 are transfer gates, and SA is a sense amplifier. MC denotes a memory cell. Reference symbol φ_X0, φ_X1Is a local bit line selection signal, CL is a column selection signal, TGRX, TGRZ, TGR0, TGR1 are reset transfer gates, and V_RIndicates a reference voltage (fixed reference voltage). Here, a memory cell MC is provided between each word line WL and each local bit line LBL0X, LBL0Z, LBL1X, LBL1Z. For example, n + 1 word lines WL (0-o to 0-n) are provided for the local bit line pair LBL0X, LBL0Z, and for the local bit line pair LBL1X, LBL1Z, for example, , N + 1 word lines WL (1-o to 1-n) are provided.
[0005]
As shown in FIG. 10, in the related-art semiconductor memory device, transfer gates TG0 and TG1 serving as connection points between the local bit lines LBL0X, LBL0Z, LBL1X and LBL1Z and the global bit lines GBLX and GBLZ are respectively connected to the local bit lines. It is provided at one end of LBL0X, LBL0Z, LBL1X, LBL1Z. In the related-art semiconductor memory device shown in FIG. 10, the global bit lines are configured as two complementary signal lines GBLX and GBLZ.
[0006]
FIG. 11 shows an example of the memory cell MC in the semiconductor memory device. As shown in the figure, the memory cell MC includes a gate transistor Q and a capacitor C. The drain of the transistor Q is connected to a local bit line LBL (LBL0X, LBL0Z, LBL1X, LBL1Z), and the gate is a word line. The source is connected to the power source Vp through the capacitor C.
[0007]
As described above, in the related-art semiconductor memory device shown in FIG. 10, the transfer gates TG0 and TG1 for controlling the connection to the global bit lines GBLX and GBLZ are provided at one end of each of the local bit lines LBL0X, LBL0Z, LBL1X and LBL1Z. The global bit lines are configured as two complementary signal lines GBLX and GBLZ.
FIG. 12 is a diagram showing signal waveforms for explaining the operation of the semiconductor memory device of FIG.
[0008]
As shown in FIG. 12, first, when the / RAS (row address strobe) signal changes from the high level “H” to the low level “L”, the bit line reset signal φ_BFalls from the high level “H” (high potential power supply voltage Vcc or Vii) to the low level “L” (low potential power supply voltage Vss), and the local bit line selection signal φx (φ_X0, φ_X1) Changes, the corresponding local bit lines LBL0X, LBL0Z are selected and connected to the global bit lines GBLX, GBLZ. Here, the local bit line selection signal φ_X0Becomes Vcc + α (or Vii + α), and the local bit lines LBL0X, LBL0Z are selected (selected), and the local bit line selection signal φ_X1Assume that the low level becomes “L” and the local bit lines LBL1X and LBL1Z are not selected (unselected).
[0009]
Next, when a predetermined word line WL is selected, the contents of the memory cells MC connected to the word line WL appear on the global bit lines GBLX and GBLZ via the local bit lines LBL0X and LBL0Z. At this time, in the related-art semiconductor memory device, since the transfer gate TG0 is provided at one end of the local bit lines LBL0X and LBL0Z, the wiring resistance and the signal transmission time constant of the bit lines (LBL0X and LBL0Z) increase. The read time (t) will also increase. That is, in order to shorten the time (t) until a sufficient difference voltage is generated in the bit lines LBL0X, LBL0Z (GBLX, GBLZ), for example, the length of the local bit lines is reduced to reduce the number of local bit lines. And the number of transfer gates and a signal line for controlling the transfer gates (signal φ_X) Need to be increased.
[0010]
Further, in related-art semiconductor memory devices, it is usually necessary to provide two complementary global bit lines GBLX and GBLZ formed by metal wiring (for example, aluminum wiring). The pitch cannot be shortened, and the degree of integration is also reduced.
In FIG. 12, for example, when the data reading process is completed, the / RAS signal changes from the low level “L” to the high level “H”, the level of the word line WL becomes the low level “L”, Bit line reset signal φ_BReturn from the low level “L” to the high level “H” and change the level of the global bit lines GBLX and GBLZ to the reference voltage (reference potential) V_RAnd Then, the local bit line selection signal φx (φ_X0) Also changes from Vcc + α (or Vii + α) to Vcc (or Vii), and the connection between the local bit lines LBL0X and LBL0Z and the global bit lines GBLX and GBLZ returns to the initial state.
[0011]
In view of the problems of the semiconductor memory device (hierarchical bit line type semiconductor memory device) described above, the present inventor has further increased the speed and power consumption without increasing the number of local bit lines. A semiconductor memory device that can be used has been proposed as Japanese Patent Application No. 6-293050.
FIG. 13 is a circuit diagram showing another example of a semiconductor memory device as a related technique corresponding to the present invention proposed in Japanese Patent Application No. 6-293050.
[0012]
As shown in FIG. 13, the related-art semiconductor memory device proposed in Japanese Patent Application No. 6-293050 is a hierarchical bit line type semiconductor memory device having local bit lines LBLZ0 and LBLZ1 and global bit lines GBLZ and GBLX. The transfer gates TG0 and TG1 are provided near the center of the local bit lines LBLZ0 and LBLZ1. That is, the length of each transfer gate TG0, TG1 and the memory cell MC at the end of each local bit line LBLZ0, LBLZ1 is reduced, and the resistance of the bit line is reduced.
[0013]
Further, in the related-art semiconductor memory device shown in FIG. 13, the local bit lines LBLZ0 and LBLZ1 are connected to a single global bit line GBLZ, and the potential of the global bit line GBLZ is set to the reference potential V._RDifferential amplification between the two. That is, two pairs of local bit lines LBL0X, LBL0Z; LBL1X, LBL1Z (LBLZ0, LBLZ1) connected to the complementary (two) global bit lines GBLX, GBLZ in the semiconductor memory device shown in FIG. Only one (one) global bit line GBLZ is connected, and the other global bit line GBLX is removed. As a result, the number of global bit lines is reduced (halved), the charge / discharge current of the bit lines is reduced, and the amplification time of the sense amplifier is shortened.
[0014]
[Problems to be solved by the invention]
FIG. 14 is a diagram showing signal waveforms for explaining the read operation of data “1” in the semiconductor memory device of FIG.
As shown in FIG. 14, first, when the / RAS (row address strobe) signal changes from the high level “H” to the low level “L”, the bit line reset signal φ_B(Omitted in FIG. 14) falls from the high level “H” (high potential power supply voltage Vcc or Vii) to the low level “L” (low potential power supply voltage Vss), and the local bit line selection signal φx (φ_X0, φ_X1) Changes, the corresponding local bit lines LBLZ0 and LBLZ1 are selected and connected to the global bit line GBLZ.
[0015]
Next, when a predetermined word line WL is selected, the contents of the memory cell MC connected to the word line WL appear on the global bit line GBLZ via the local bit line LBLZ0. Here, in the related-art semiconductor memory device shown in FIG._RIs a fixed potential (for example, V that is an intermediate potential between the high-side amplitude and low-side amplitude of the bit line)._CC/ 2 or internal power supply potential V_IIIntermediate potential V_II/ 2).
[0016]
By the way, when reading, the external power supply V_CC(Or internal power supply potential V_II) Changes rapidly, the reference potential V set to this intermediate potential_RWill also fluctuate. This reference potential V_RCan also be caused by noise generated from the semiconductor memory device itself. For example, the bit line connected to the memory cell to be read is precharged (reference potential) V._RWhen this variation occurs immediately after being disconnected from the gate (see reference numeral TT1 in FIG. 14), the initial potential of the bit line to be read and the reference potential V_RAs a result, and in the worst case, the potential of the bit line generated by the information of the cell to be read and the reference potential V_RThe difference voltage that should occur between the two is reduced and correct information cannot be read out.
[0017]
Specifically, the reference potential V_RIs exactly V_CC/ 2 (V_II/ 2) The potential of the global bit line GBLZ and the reference potential V generated in the case of_R(See reference sign VV1 in FIG. 14) is a reference potential V_R(See symbol VV2 in FIG. 14), there is a risk that data “1” originally stored in the memory cell is read as reverse data “0”. This corresponds to rewriting the opposite data to the memory cell according to erroneous read data.
[0018]
The change in the potential of the global bit line GBLZ is caused by the reference voltage (reference potential) V supplied to the current mirror amplifier (readout differential amplifier) A._RAnd is differentially amplified between. Further, the output (GBLX) of the current mirror amplifier A is fed back to the input terminal of the current mirror amplifier A to which the global bit line GBLZ is connected via the inverter (rewriting amplifier) A ′, thereby the signal line ( The potential of the global bit line GBLX) becomes Vcc (or Vii: high level “H”), and the potential of the global bit line GBLZ changes to Vss (low level “L”). Further, when the column selection signal CL changes from the low level “L” (Vss) to the high level “H” (Vcc or Vii), the transfer gates TGDX and TGDZ are switched on to correspond to the signal lines (complementary global bit lines). ) The potentials of GBLX and GBLZ are transmitted to the data signal lines DBX and DBZ and output to the outside. When the data reading process is completed, the / RAS signal changes from the low level “L” to the high level “H”, the level of the word line WL becomes the low level “L”, and the bit line reset signal φ_BThe level of the signal lines (global bit lines) GBLX and GBLZ is returned to the reference voltage V from the low level “L” to the high level “H”._RAnd At this time, the local bit line selection signal φx (φ_X0, φ_X1) Also changes from Vcc + α (or Vii + α) to Vcc (or Vii), and the connection between the local bit lines LBLZ0 and LBLZ1 and the global bit line GBLZ returns to the initial state.
[0019]
As described above, the related-art semiconductor memory device shown in FIG. 13 can reduce the number of global bit lines and the charge / discharge current of the bit lines to shorten the amplification time of the sense amplifier. External power supply V_CCAnd internal power supply potential V_IIIn the worst case, the potential of the bit line and the reference potential V generated by the information of the memory cell to be read out due to fluctuations in the noise or noise generated from the semiconductor memory device itself._RThere is a risk that the difference voltage to be generated between the two and the like decreases, and correct information cannot be read out.
[0020]
In view of the problem of the above-described conventional semiconductor memory device, the present invention provides a power supply potential (V_CCOr V_IIIt is an object of the present invention to provide a semiconductor memory device that can always read out correct data even when there is a fluctuation in noise) or when noise occurs.
[0021]
[Means for Solving the Problems]
  FIG. 1 is a circuit diagram showing a principle configuration of a semiconductor memory device according to the present invention.
  According to the present invention,Both the real bit line part RR and the dummy bit line part D1 (D2)Local bit lines LBLZ0, LBLZ1 and global bit line GBLZConsist ofA hierarchical bit line type semiconductor memory device, wherein the local bit lines LBLZ0, LBLZ1 provided near the center of the local bit lines LBLZ0, LBLZ1 and transfer gates TG0, TG1 connecting the global bit line GBLZ, andOf the real bit line portion RRGlobal bit line GBLZPotentialAnd sense reference potential V_R 'And the output signal GBLX of the read amplifier circuit A is inverted and a predetermined activation signal φ is inverted.₂ Via a rewrite transfer gate controlled byOf the real bit line portion RRA rewrite amplifier circuit A ′ for supplying the global bit line GBLZ;Bit line precharge control signal φ B ByReference potential V for precharge during standby_R Charged up and floating while activeThe global of the dummy bit line portion D1A bit line DGBLZ, andMemory cell in the dummy bit line portion D1 MC Is configured so that no data is written to it,The dummy bit lineThe global bit line of part D1 DGBLZIs the reference potential for sensing V_R A semiconductor memory device characterized by being supplied as' is provided.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
  The semiconductor memory device of the present inventionBoth the real bit line part RR and the dummy bit line part D1 (D2)Local bit lines LBLZ0, LBLZ1 and global bit line GBLZConsist ofHierarchical bit line type semiconductor memory device, provided near the center of local bit lines LBLZ0, LBLZ1, transfer gates TG0, TG1, which connect local bit lines LBLZ0, LBLZ1 and global bit lines GBLZ,Real bit line part RRGlobal bit line GBLZPotentialAnd sense reference potential V_R 'And amplifying the output signal GBLX of the read amplifier circuit A for differential amplification with respect to the₂ Via a rewrite transfer gate controlled byReal bit line part RRAmplifying circuit A ′ for rewriting supplied to global bit line GBLZ, andBit line precharge control signal φ B Therefore, during standby, the precharge reference potential V _R The dummy bit line portion D1 is charged globally and is floating when active.A bit line DGBLZ is provided. here,Memory cell in dummy bit line portion D1 MC Is configured so that data is not written to the global bit line of the dummy bit line D1. DGBLZ The reference potential for sensing V _R ' To supply as.As a result, the semiconductor memory device of the present invention can always read correct data even when the power supply potential fluctuates or noise occurs.
[0023]
In FIG. 1, reference numeral RR indicates a real bit line portion that is actually used, and D1 and D2 indicate dummy bit line portions. The real bit line portion RR includes a global bit line GBLZ, local bit lines LBLZ0, LBLZ1, memory cells MC, and a sense amplifier portion. The dummy bit line portion D1 (D2) includes dummy global bit lines DGBLZ, It includes dummy local bit lines DLBLZ0, DLBLZ1, and memory cells MC. Here, the real bit line portion RR is actually configured to include, for example, 128 global bit lines GBLZ.
[0024]
Further, in FIG. 1, reference symbols DBX and DBZ are data signal lines, TG0 and TG1 are transfer gates, φ_X0, φ_X1Is the local bit line selection signal, CL is the column selection signal, V_RIs the precharge reference voltage (precharge reference potential) and V_R'Indicates a sense reference voltage (sense reference potential). Here, a memory cell MC is provided between each word line WL and each local bit line LBLZ0, LBLZ1. A pair of local bit lines LBLZ0 and LBLZ1 are provided. Further, for example, n + 1 word lines WL (0-o to 0-n) are provided for the local bit line LBLZ0, and for example, n + 1 word lines are provided for the local bit line LBLZ1. WL (1-o to 1-n) is provided. The configuration of the memory cell MC is the same as that shown in FIG.
[0025]
As shown in FIG. 1, in the semiconductor memory device of the present invention, the sense reference potential V is used together with the real bit line portion RR used for actually storing data._RDummy bit line portions D1 and D2 are provided for supplying 'to a sense amplifier portion (reading amplifier circuit: differential amplifier circuit, current mirror amplifier A) of the real bit line portion RR. One end of the global bit line DGBLZ in the dummy bit line portions D1 and D2 is connected to the bit line reset signal φ at the gate._BIs supplied, and one input (reference potential input) of the read amplifier circuit A is connected to the other end of the global bit line DGBLZ. That is, the sense reference potential V applied to the reference potential input of the read amplifier circuit A_R'Is the bit line precharge control signal (bit line reset signal) φ_BBit line precharge reference potential V corresponding to transistor TGRD controlled by_RIs supplied via the global bit line DGBLZ of the dummy bit line portions D1 and D2.
[0026]
Here, a bit line precharge control signal φ for controlling the transistor TGRD of the dummy bit line portions D1, D2_BIs a signal (φ for controlling the transistor TGRD of the real bit line portion RR._B), The sense reference potential V applied to the reference potential input of the read amplifier circuit A_R'Indicates the precharge reference potential V during standby_RThe battery is charged up and is floated while active. Therefore, even if the power supply voltage fluctuates at this time (active state), the sense reference potential V_R'Can be held and its reference potential V_RThe data is read by differentially amplifying 'and the potential of the global bit line GBLZ of the real bit line portion RR by the read amplifier circuit A.
[0027]
In addition, the sense reference potential V_R'Is supplied via the global bit line DGBLZ of the dummy bit line portions D1 and D2, so that, for example, even when the potential of the global bit line GBLZ of the real bit line portion RR fluctuates due to noise or the like in the active state. , The reference potential V for sensing according to the variation_R'Will also fluctuate, so the data can be read correctly.
[0028]
FIG. 2 is a diagram showing signal waveforms for explaining the operation of the semiconductor memory device of FIG.
As shown in FIG. 2, first, when the / RAS (row address strobe) signal changes from the high level “H” to the low level “L”, the bit line reset signal φ_BFalls from the high level “H” (high potential power supply voltage Vcc or Vii) to the low level “L” (low potential power supply voltage Vss), and the local bit line selection signal φx (φ_X0, φ_X1) Changes, the corresponding local bit lines LBLZ0 and LBLZ1 are selected and connected to the global bit line GBLZ in the real bit line portion RR used for actually reading and writing data. Here, in the dummy bit line portions D1 and D2, the bit line reset signal φ_BIs high, the transistor TGRD is switched on and the precharge reference potential V is set via the global bit line DGBLZ._R(V_CC/ 2 or V_II/ 2) is applied to the reference potential input of the read amplifier circuit A, but the bit line reset signal φ_BWhen the signal becomes low level "L", the transistor TGRD is switched off and the global bit line DGBLZ is in a floating state.
[0029]
In FIG. 2, the bit line reset signal φ_BFalls from the high level “H” to the low level “L” and the local bit line selection signal φx (φ_X0, φ_X1) Changes when the power supply voltage (external power supply voltage V_CCOr internal power supply voltage V_II) Rises rapidly (see reference numeral TT1 in FIG. 2). At this time, the precharge reference potential V_R(V_CC/ 2 or V_II/ 2) also varies as the power supply voltage increases. However, the sense reference potential V applied to the reference potential input of the read amplifier circuit A_R'Is the bit line reset signal φ_BAs a result, the transistor TGRD is switched off and the global bit line DGBLZ is in a floating state, so that the voltage up to that time can be held. That is, according to the semiconductor memory device of the present invention, the power supply voltage (V) is set immediately after the global bit line GBLZ of the real bit line portion RR becomes floating._CC, V_II) Rapidly changes, the sense reference potential V supplied via the global bit line DGBLZ in the dummy bit line portion._RSince 'is a floating node having the same coupling as the global bit line GBLZ in the real bit line portion, only the same fluctuation as the global bit line GBLZ in the albit line portion occurs. Therefore, in the read amplifier circuit A, the potential of the global bit line GBLZ in the real bit line portion RR and the reference potential for sensing V_R'Is sensed, the precharge reference potential V_RIt becomes possible to read data correctly regardless of fluctuations.
[0030]
Note that when the potential of the global bit line GBLZ of the real bit line part RR changes due to noise or the like in the active state, the reference reference potential V for sensing is so canceled that the change_RThe manner in which 'also changes will be described later with reference to FIG.
[0031]
【Example】
Embodiments of a semiconductor memory device according to the present invention will be described below with reference to the drawings.
FIG. 3 is a circuit diagram showing an embodiment of the semiconductor memory device of the present invention. In the figure, reference numeral RR indicates a real bit line portion that is actually used, and D1 and D2 indicate dummy bit line portions. In the real bit line section RR, the reference symbol GBLZ is a global bit line, LBLZ0 and LBLZ1 are local bit lines, WL is a word line, DBX and DBZ are data signal lines, TG0 and TG1 are transfer gates, and MC is a memory. Shows the cell. Furthermore, reference sign φ_X0, φ_X1Is the local bit line selection signal, CL is the column selection signal, and V_RIndicates a precharge reference voltage. In FIG. 3, reference numeral A is a current mirror amplifier (reading amplifier circuit), A 'is a tristate inverter (rewriting amplifier circuit), φ_BIs the bit line reset signal, φ₁Is the current mirror amplifier activation signal, / φ₂Indicates an activation signal for a rewrite inverter, CLR indicates a read column selection signal, and CLW indicates a write column selection signal.
[0032]
In the dummy bit line portion D1 (D2), reference symbol DGBLZ is a global bit line, DLBLZ0 and DLBLZ1 are local bit lines, WL is a word line, DBX and DBZ are data signal lines, TG0 and TG1 are transfer gates, and V_R'Indicates the reference voltage for sensing. Here, the current mirror amplifier A is a differential amplifier for reading, and the tristate inverter A 'is an amplifier for rewriting. As is apparent from FIG. 3, the dummy bit line portion D1 (D2) is not provided with a write / read circuit such as a current mirror amplifier A and an inverter A ′, but the other configuration is a real bit line. It is the same as the part RR. The real bit line portion RR includes, for example, 128 global bit lines GBLZ.
[0033]
In the embodiment shown in FIG. 3, the dummy bit line portions D1 and D2 are provided on both sides of the real bit line portion RR. However, as will be described later with reference to FIG. It may be provided only on one of the parts RR, or may be provided for a predetermined number of real bit line parts RR (a predetermined number of subarrays of the memory array). The configuration of the dummy bit line portion D1 (D2) is the same as that of the real bit line portion RR except for the write / read circuit (current mirror amplifier A, etc.). This is because the change in the potential of the global bit line GBLZ is reflected in the change in the potential of the global bit line DGBLZ in the dummy bit line portion D1 (D2).
[0034]
A memory cell MC is provided between each word line WL and each local bit line LBLZ0, LBLZ1, and a pair of local bit lines LBLZ0, LBLZ1 is provided. Further, for example, n + 1 word lines WL (0-o to 0-n) are provided for the local bit line LBLZ0, and for example, n + 1 word lines are provided for the local bit line LBLZ1. WL (1-o to 1-n) is provided.
[0035]
As shown in FIG. 3, in the semiconductor memory device of the present embodiment, transfer gates TG0 and TG1 serving as connection points between the local bit lines LBLZ0 and LBLZ1 and the global bit line GBLZ are provided as in the semiconductor memory device of FIG. The local bit lines LBLZ0 and LBLZ1 are provided at the center. That is, the length of each transfer gate TG0, TG1 and the memory cell MC at the end of each local bit line LBLZ0, LBLZ1 is about half that of the related-art semiconductor memory device shown in FIG. It is supposed to be.
[0036]
Further, as apparent from the comparison between FIG. 10 and FIG. 3, the semiconductor memory device of this embodiment is connected to the complementary (two) global bit lines GBLX and GBLZ in the related technique of FIG. Similarly to the semiconductor memory device of FIG. 13, two pairs of local bit lines LBL0X, LBL0Z; LBL1X, LBL1Z (LBLZ0, LBLZ1) are connected to only one (one) global bit line GBLZ. The global bit line GBLX is removed. In the semiconductor memory device of this embodiment, the potential of the global bit line GBLZ in the real bit line portion RR is changed by the current mirror amplifier A to the sense reference potential V._RAs a result of the differential amplification between the two, the number of global bit lines is reduced (halved) and the charge / discharge current of the bit lines is reduced to shorten the amplification time of the sense amplifier. Here, the bit line reset signal φ is connected to the gates at both ends of the global bit line GBLZ of the real bit line part RR._BIs provided with a resetting transistor TGR and a transistor 33, and the bit line reset signal φ_B(Φ_BIs set to the high level “H”), the level of the global bit line GBLZ is set to the reference voltage V for precharging._RIt is supposed to be. Note that an output signal line (GBLX) of a current mirror amplifier A to be described later also has a bit line reset signal φ at its gate._BIs supplied to the reference voltage (precharge reference voltage) V by the resetting transistor 31 supplied with_RTo be reset.
[0037]
As shown in FIG. 3, the current mirror amplifier (reading amplifier circuit) A is composed of P-channel MOS transistors 11 and 12 and N-channel MOS transistors 13, 14, 15, and 16, and a real bit line portion RR. The global bit line GBLZ is connected to the gate of the transistor 13. Further, the global bit line DGBLZ (reference potential V for sensing) of the dummy bit line portion D1 (D2)_R′) Is applied to the gate (reference potential input) of the transistor 14, so that in the current mirror amplifier A, the potential of the global bit line GBLZ of the real bit line portion RR is changed to the reference potential V for sensing._RCompared with ', data will be read out.
[0038]
The tri-state inverter (rewrite amplifier circuit) A ′ is composed of P-channel MOS transistors 21 and 22 and N-channel MOS transistors 23 and 24. The global bit line GBLZ is connected to the transistors 22 and 23. The output signal (GBLX) of the current mirror amplifier A is supplied to the gates of the transistors 22 and 23. Further, the P-channel drive signal PSA and the N-channel drive signal NSA are supplied to the sources of the transistors 21 and 24, respectively. Here, the output of the NOR gate 41 is supplied to the gate of the transistor 24, and the output of the NOR gate 41 is supplied to the gate of the transistor 21 via the inverter 42. The control circuit B composed of the NOR gate 41 and the inverter 42 may be provided, for example, in a column decoder unit, and can be shared by a plurality of sense amplifiers. Further, the NOR gate 41 has an input to the rewrite inverter activation signal / φ₂, And the write column selection signal CLW is supplied and the signal / φ₂, CLW controls the operation of the inverter A ′.
[0039]
That is, as described above, the potential of the global bit line GBLZ of the real bit line part RR is supplied by the current mirror amplifier A via the global bit line DGBLZ of the dummy bit line part D1 (D2). V_R'Is differentially amplified between. Further, the output (GBLX) of the current mirror amplifier A is supplied to the input terminal of the current mirror amplifier A together with the global bit line GBLZ of the real bit line section RR via the amplifier A ′, whereby the complementary global bit lines GBLX, A signal line corresponding to GBLZ is configured, and the potentials of the signal lines GBLX and GBLZ are transmitted to the data signal lines DBWX, DBRX (DBX) and DBWZ (DBZ) via the transfer gates 32 and 34 (TGDX and TGDZ). Output to the outside. Here, the transfer gate 32 includes a transistor 321 whose gate is supplied with a read column selection signal CLR and a transistor 322 whose gate is supplied with a write column selection signal CLW, and is selected at the time of reading and writing. The transfer gate 33 is composed of a transistor whose gate is supplied with a write column selection signal CLW, and is selected during writing. Reference symbols DBWX and DBWZ indicate data signal lines for writing, DBRX indicates a data signal line for reading, and the data signal line DBX is used as both data signal lines DBWX and DBRX for writing and reading.
FIG. 4 is a diagram showing signal waveforms for explaining an operation of reading data “1” in the semiconductor memory device of FIG.
[0040]
As shown in FIG. 4, when the read operation is started, the / RAS (row address strobe) signal changes from the high level “H” to the low level “L”, and the bit line reset signal φ_BFalls from the high level “H” (high potential power supply voltage Vcc or Vii) to the low level “L” (low potential power supply voltage Vss), and the global bit line GBLZ and the output signal line (GBLX) of the current mirror amplifier A Is the precharge reference voltage V_RReleased from.
[0041]
Here, in the dummy bit line portions D1 and D2, the bit line reset signal φ_BIs high, the transistor TGRD is switched on and the precharge reference potential V is set via the global bit line DGBLZ._R(V_CC/ 2 or V_II/ 2) is applied to the reference potential input of the read amplifier circuit A, but the bit line reset signal φ_BWhen the signal becomes low level "L", the transistor TGRD is switched off and the global bit line DGBLZ is in a floating state.
[0042]
Further, in the real bit line portion RR used for actually reading and writing data, the local bit line selection signal φx (φ_X0, φ_X1) Changes, the corresponding local bit lines LBLZ0 and LBLZ1 are selected and connected to the global bit line GBLZ. Specifically, one local bit line selection signal φ_X0Changes from Vcc (or Vii) to Vcc + α (or Vii + α) (selected state), the signal φ_X0The transfer gates TG0 (two) supplied to the gate are switched on to connect the local bit line LBLZ0 (two) and the global bit line GBLZ, and the other local bit line selection signal φ_X1Changes from Vcc (or Vii) to Vss (unselected state), the signal φ_X1The transfer gates TG1 (two) supplied to the gate are switched off, and the local bit line LBLZ0 (two) and the global bit line GBLZ are disconnected. That is, one (or one) local bit line pair LBLZ0 is connected to the global bit line GBLZ.
[0043]
At this time, in the dummy bit line portions D1 and D2, the bit line reset signal φ_BIs high, the transistor TGRD is switched on and the precharge reference potential V is set via the global bit line DGBLZ._R(V_CC/ 2 or V_II/ 2) is applied to the reference potential input of the read amplifier circuit A, but the bit line reset signal φ_BWhen the signal becomes low level "L", the transistor TGRD is switched off and the global bit line DGBLZ is in a floating state.
[0044]
Next, in the real bit line portion RR, a predetermined word line WL (any one word line selected corresponding to the address signal) is selected, and the activation signal φ of the current mirror amplifier₁Becomes high level “H”, the current mirror amplifier A is activated, and when the read column selection signal CLR becomes high level “H”, the transistor (transfer gate) 321 is switched on, and the current The output signal line GBLX of the mirror amplifier A is connected to the data signal line DBX (DBRX). As a result, the contents of the memory cell MC connected to the selected predetermined word line WL appear on the global bit line GBLZ via the local bit line LBLZ0. In this embodiment, the read column selection signal CLR is set to the high level “H” before amplification of the read signal, and the output line GBLX of the current mirror amplifier A is connected to the data signal line DBX (DBRX). Therefore, the reading operation can be further speeded up.
[0045]
At this time, in the dummy bit line portions D1 and D2, as in the real bit line portion RR, the local bit line selection signal φx (φ_X0, φ_X1) Change, the corresponding local bit lines DLBLZ0 and DLBLZ1 are selected and connected to the global bit line DGBLZ, and a predetermined potential (high level “H”) is applied to the selected predetermined word line WL. The Note that no data is written in the memory cells MC in the dummy bit line portions D1 and D2, and the potential of the global bit line DGBLZ (the reference potential for sensing V V) even when a predetermined word line WL is selected._R') Never changes.
[0046]
In FIG. 4, the bit line reset signal φ_BFalls from the high level “H” to the low level “L” and the local bit line selection signal φx (φ_X0, φ_X1) Changes when the potential of the global bit line GBLZ of the real bit line part RR varies due to noise or the like (see reference numeral TT2 in FIG. 4). As described above, when the potential of the global bit line GBLZ of the real bit line part RR changes, the current mirror amplifier is connected via the global bit line DGBLZ of the dummy bit line part D1 (D2) configured in the same manner as the real bit line part RR. Sense reference potential V applied to one input (reference potential input) of A_R'Also varies in the same manner (see symbol TT3 in FIG. 4). Therefore, the potential of the global bit line GBLZ in the real bit line portion RR and the reference potential V for sensing_RThe potential difference between and 'is substantially the same voltage as when the potential of the global bit line GBLZ does not change (see symbol VV3 in FIG. 4). That is, for example, the potential of the word line WL is V_SSTo V_CC+ Α (or V_II+ Α) or V of the local bit line select signal φx_CCTo V_CC+ Α (or V_IITo V_II+ Α), or V of the word line WL when not selected._SSThe sensing reference potential V supplied via the global bit line DGBLZ of the dummy bit line portion also against coupling noise due to changes to_R'Is affected in the same manner as the potential variation of the global bit line GBLZ in the real bit line portion RR, and therefore the variation widths of both are almost the same. Therefore, even when the potential of the global bit line GBLZ of the real bit line portion RR varies due to noise or the like in the active state, the sensing reference potential V is corresponding to the variation._R'Also changes, so that the current mirror amplifier A can correctly read data.
[0047]
At this time, in the semiconductor memory device of this embodiment, since the transfer gate TG0 (TG1) is provided near the center of the local bit line LBLZ0 (LBLZ1), the potential change caused by the selected memory cell MC is reduced for a short time. Can be transmitted to the bit line. That is, for example, even when the selected memory cell MC is farthest from the transfer gate TG0, the distance is less than half of the local bit line LBLZ0, so that the resistance by the bit line (local bit line LBLZ0) is reduced and selected. The change in the potential of the local bit line LBLZ0 caused by the memory cell MC is transmitted to the global bit line GBLZ in a short time (high speed). This is indicated by the fact that the change time T of the potential of the bit line shown in FIG. 4 is shorter (about half) than the change time t shown in FIG.
[0048]
Further, as shown in FIG. 4, the activation signal / φ of the inverter for rewriting₂Becomes the low level “L” and the write column selection signal CLW input to the NOR gate 41 is at the low level “L”, so that the output of the NOR gate 41 becomes the high level “H” and the tristate inverter (for rewriting) The amplifier A) is activated.
That is, the change in the potential of the global bit line GBLZ in the real bit line part RR (change to the high potential side in FIG. 4) is the sense reference voltage V supplied to the current mirror amplifier A._R, And the potential of the output signal (GBLX) of the current mirror amplifier A is applied to the gates of the transistors 22 and 23 in the inverter A ′, inverted and amplified, and output to the global bit line GBLZ. . The P-channel and N-channel drive signals PSA and NSA supplied to the sources of the transistors 21 and 24 are precharge reference voltages V during standby._RFrom the level of the activation signal φ₂Is changed (activated) before being charged up and discharged to the level of voltage Vcc (or Vii) and Vss. As a result, the potential difference between the global bit line GBLZ and the output signal (GBLX) of the current mirror amplifier A is widened. The output signal (GBLX) of the current mirror amplifier A is transmitted to the data signal line DBRX (DBX) via the transistor 321 and output to the outside. Note that the potential of the global bit line GBLZ is not transmitted to the data signal line DBZ because the transfer gate (transistor) 34 is off.
[0049]
When the data reading process is completed, the / RAS signal changes from the low level “L” to the high level “H”, the level of the word line WL becomes the low level “L”, and the current mirror amplifier is activated. Signal φ₁Changes from the high level “H” to the low level “L”, the current mirror amplifier A is deactivated, and the bit line reset signal φ_BThe level of the global bit line GBLZ and the signal line GBLX is returned to the reference voltage V from the low level “L” to the high level “H”._RAnd Further, the local bit line selection signal φx (φ_X0, φ_X1) Also changes from Vcc + α (or Vii + α: selected state) to Vcc (or Vii), or from Vss (unselected state) to Vcc (or Vii). Connection is returned to the initial state.
[0050]
Here, in this embodiment, for example, at the time of reading, the global bit line GBLZ is not directly connected to the read wiring (data signal line) DBRX (DBX), so the read column selection signal CLR is activated early. can do. Further, when the word line WL is activated, a potential is supplied to the global bit line GBLZ with a time constant about half that of the related-art semiconductor memory device shown in FIG._RThere is a voltage difference between The current mirror amplifier A then activates the current mirror amplifier activation signal φ almost simultaneously with the word line WL.₁Therefore, the differential amplification is immediately performed and the cell information is sent to the data signal line DBRX (DBX) via the output signal GBLX 32 (321), thereby enabling high-speed access. Here, the amplification of the output signal GBLX can be performed at high speed because of its small capacity, and the activation signal / φ of the rewriting inverter A ′₂Since the amplification has already been completed at the time when is output, rewriting to the global bit line GBLZ is also performed at high speed. In addition, since almost no through current is generated in the inverter A ′, current consumption can be sufficiently reduced. Specifically, the charge / discharge current of the bit line is normally about half that of the related-art semiconductor memory device shown in FIG. Furthermore, since the pitch of the global bit lines GBLZ can be relaxed to about twice that of the semiconductor memory device of FIG. 10, the line capacity and mutual interference of the global bit lines can be reduced. These effects are exhibited not only at the time of reading but also at the time of writing.
[0051]
FIG. 5 is a circuit diagram showing another embodiment of the semiconductor memory device of the present invention.
In the embodiment shown in FIG. 5, the dummy bit line portion D1 ′ is provided only on one side of the real bit line portion RR, and the memory cell MC is omitted in the dummy bit line portion D1 ′. It is configured. As described above, even when the dummy bit line portion D1 ′ in which the memory cell MC is omitted is provided only in one of the real bit line portions RR, the potential variation of the global bit line GBLZ in the real bit line portion RR is detected as the reference potential for sensing. V_RIt can be reflected in '(sense reference voltage applied to the reference potential input of the current mirror amplifier A via the global bit line DGBLZ of the dummy bit line portion D1'). However, the local bit line selection signal φx (φ_X0, φ_X1The transfer gates TG0 and TG1 controlled by (1) must be provided in the dummy bit line portion D1 ′. The operation of the semiconductor memory device shown in FIG. 5 is the same as that described with reference to FIG.
[0052]
As described above, according to the embodiments of the semiconductor memory device of the present invention, the global bit line DGBLZ of the dummy bit line portions D1, D2 (D1 ′) is connected to the global bit line GBLZ of the real bit line portion RR during standby. Same precharge reference potential V as_RCharged up. After that, the bit line reset signal φ_BAs a result, the global bit line GBLZ of the real bit line part RR is set to the precharge potential V._RAt the same time as the disconnection from the dummy bit line, the precharge potential V_RDetached from. As a result, the bit line becomes precharged potential V_RAfter being disconnected from the precharge potential V_REven if the fluctuation occurs due to coupling, the global bit line GBLZ in the real bit line portion and the global bit line DGBLZ in the dummy bit line portion are both floating. There is no potential difference between DGBLZ. For the same reason, when the bit line (global bit line GBLZ, DGBLZ) fluctuates due to coupling noise due to the rise or fall of the word line WL or the local bit line selection signal, the dummy bit line portion Since the global bit line DGBLZ is affected by the same effect as the global bit line GBLZ in the real bit line portion, no potential difference is generated between the global bit lines GBLZ and DGBLZ. As a result, correct data can always be read even when the power supply potential fluctuates or noise occurs.
[0053]
In each of the above-described embodiments, the sensing reference potential V_RThe wiring capacity when 'is wired in the memory block in the memory array or in the sub-array is not taken into consideration, and the potential of the global bit line GBLZ and the sense reference potential V in the real bit line portion are not considered._RIt is considered that there is a slight difference in the fluctuation of '. Therefore, in the embodiment shown in FIG. 3 (FIG. 1), dummy bit line portions D1 and D2 are provided at two positions on both ends of the real bit line portion RR so as to compensate for the wiring capacitance in the sub-array and the like. However, even if the dummy bit line portion D1 ′ is provided on one side of the real bit line portion RR and the memory cell MC is omitted as in the embodiment shown in FIG. 5, there is almost no problem in actual use. . Although the memory array area is increased, in order to maintain symmetry in the memory array, the sense reference voltage V described above is used._RA dummy wiring for generating 'may be installed in the sub-array of the memory array.
[0054]
  FIG. 6 is a circuit diagram showing still another embodiment of the semiconductor memory device of the present invention. FIG. 7 is a diagram showing signal waveforms for explaining the read operation of data “1” in the semiconductor memory device of FIG. It is.
  The semiconductor memory device shown in FIG. 6 differs from the semiconductor memory device shown in FIG. 3 (FIG. 5) in the configuration of the read amplifier circuit (A) and the rewrite amplifier circuit (A ′). Yes. In FIG. 6, reference numeral 17 denotes an activation signal φ at the gate.₁ N-channel MOS transistor, 20 is a latch circuit composed of inverters 201 and 202, and 25 is a transfer circuit.AgeShows
[0055]
As shown in FIG. 6, the read amplifier circuit (current mirror amplifier) A is composed of P-channel MOS transistors 11 and 12 and N-channel MOS transistors 13, 14, and 17, and the global of the real bit line portion RR. The bit line GBLZ is connected to the gate of the transistor 13. Further, the global bit line DGBLZ (reference potential V for sensing) of the dummy bit line portion D1 (D2)_R′) Is applied to the gate (reference potential input) of the transistor 14, so that in the current mirror amplifier A, the potential of the global bit line GBLZ of the real bit line portion RR is changed to the reference potential V for sensing._RCompared with ', data will be read out.
[0056]
Here, as shown in FIG. 7, the activation signal φ for the current mirror amplifier A₁Is the activation signal φ in FIG.₁High level “H” for a shorter period of time. In the current mirror amplifier A of this embodiment, this is the activation signal φ₁This is because a through current flows through the transistor 17 while the high level is “H”, so that power consumption due to the through current is minimized.
[0057]
  The rewrite amplifier circuit A 'includes a latch circuit 20 and a transfer circuit.AgeAnd 25. The latch circuit 20 is composed of two inverters 201 and 202 connected in reverse, the input of the latch circuit 20 is connected to the global bit line GBLX, and the output of the latch circuit 20 is the transfer circuit.AgeConnected to the global bit line GBLX via port 25. TransfAge25 is an activation signal / φ₂ Is supplied to the gate of the P-channel MOS transistor 251 and the activation signal φ₂ Is provided with an N-channel MOS transistor 252 supplied to the gate.
[0058]
Also in the embodiment shown in FIG. 6, the current mirror amplifier A uses the potential of the global bit line GBLZ in the real bit line portion RR as the reference potential for sensing V_R'It is designed to amplify differentially between. Each signal waveform of the read operation of data “1” shown in FIG. 7 is the same as the signal waveform of FIG. 4 described above, and the description thereof is omitted. Also in this embodiment, it is needless to say that the rewriting amplifier circuit A 'may be configured as a tri-state inverter as shown in FIG.
[0059]
FIG. 8 is a circuit diagram showing a modification of the semiconductor memory device of FIG. The modification shown in FIG. 8 includes a read amplifier circuit A and a rewrite amplifier circuit A ′ similar to those in the semiconductor memory device shown in FIG. 6, but the configuration of the control circuit B and the like is different. Yes. That is, in the semiconductor memory device shown in FIG. 8, the global bit line GBLX is connected to the data signal line DBX via the N-channel MOS transistor 320, and the transistors 34 and 33 in the semiconductor memory device of FIG. 3 are removed. Has been. Further, in the control circuit B, since it is not necessary to take the logic with the write column selection signal CLW, the activation signal / φ is generated by the inverter 40 without providing the NOR gate 41.₂, φ₂To control the transistors 251 and 252 of the transfer gate.
[0060]
Here, the transistor 34 connected to the data signal line DBZ in the semiconductor memory device of FIG. 3 can be removed because a sufficient read operation is possible by the data read to the data signal line DBX and the latch circuit 20 This is because data can be sufficiently rewritten by the rewriting amplifier circuit A ′ having the transfer gate 25.
[0061]
FIG. 9 is a diagram schematically showing the overall configuration of the semiconductor memory device of the present invention. 9A to 9C, reference numeral 6 denotes a memory array, 60, 61,... Denote memory blocks, and 600, 601,. Each sub-array (600) includes, for example, 128 global bit lines (global bit lines GBLZ in the real bit line portion). 9A to 9C, reference numerals 600A, 600B, 601A, 601B, ...; 600C, 601C, ...; and 60A, 60B, 61A, 61B are dummy bit line portions (D1), respectively. , D2).
[0062]
In the embodiment of the semiconductor memory device shown in FIG. 9A, the dummy bit line portions 600A, 600B, 601A, 601B,... Are provided on both sides of each subarray 600, 601,. It is supposed to be. That is, dummy bit line portions 600A and 600B are provided on both sides of the subarray 600, and dummy bit line portions 601A and 601B are provided on both sides of the subarray 601.
[0063]
In the embodiment of the semiconductor memory device shown in FIG. 9B, the dummy bit line portions 600C, 601C,... Are provided on one side with respect to the respective subarrays 600, 601,. It has become. That is, the dummy bit line portion 600C is provided on one side of the subarray 600, and the dummy bit line portion 601C is provided on one side of the subarray 601.
[0064]
In the embodiment of the semiconductor memory device shown in FIG. 9C, the dummy bit line portions 60A, 60B, 61A, 61B are provided on both sides of the memory blocks 60, 61. That is, dummy bit line portions 60A and 60B are provided on both sides of the memory block 60, and dummy bit line portions 61A and 61B are provided on both sides of the memory block 61.
[0065]
In each of the embodiments shown in FIGS. 9A to 9C, the dummy bit line portions 600A, 600B, 601A, 601B,..., 600C, 601C,. Considering the wiring capacity of the bit line (global bit line of the real bit line part) in the memory block etc., the influence corresponding to the change applied to the global bit line GBLZ of the real bit line part is affected by the global of the dummy bit line part. Bit line DGBLZ (sense reference voltage V_RAppropriate configuration can be selected to join '). Here, dummy bit line portions 600A, 600B, 601A, 601B, ...; 600C, 601C, ...; and; positions provided by 60A, 60B, 61A, 61B are word line lining parts (word lines such as polysilicon) The portion is in contact with the aluminum wiring) and the sub-word decoder portion, so that it is not necessary to provide a special region for the dummy bit line portion.
[0066]
As described above, according to each embodiment of the semiconductor memory device of the present invention, in the single bit line system using the hierarchical bit line structure, the reference potential is caused by a sudden change in power supply or noise generated by the output of various signals. It is possible to reduce the difference between the potentials to be read generated on the bit lines without increasing the memory cell array area.
[0067]
【The invention's effect】
As described above in detail, according to the semiconductor memory device of the present invention, the sense reference potential is supplied via the dummy bit line section, and the dummy bit line is charged up to the precharge reference potential during standby. In addition, by setting the floating state during active, correct data can always be read even when the power supply potential fluctuates or noise occurs.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a principle configuration of a semiconductor memory device according to the present invention.
2 is a diagram showing signal waveforms for explaining the operation of the semiconductor memory device of FIG. 1; FIG.
FIG. 3 is a circuit diagram showing one embodiment of a semiconductor memory device of the present invention.
4 is a diagram showing signal waveforms for explaining a read operation of data “1” in the semiconductor memory device of FIG. 3;
FIG. 5 is a circuit diagram showing another embodiment of the semiconductor memory device of the present invention.
FIG. 6 is a circuit diagram showing still another embodiment of the semiconductor memory device of the present invention.
7 is a diagram showing signal waveforms for explaining a read operation of data “1” in the semiconductor memory device of FIG. 6;
FIG. 8 is a circuit diagram showing a modification of the semiconductor memory device of FIG. 6;
FIG. 9 is a diagram schematically showing an overall configuration of a semiconductor memory device of the present invention.
FIG. 10 is a circuit diagram showing an example of a semiconductor memory device as a related technique corresponding to the present invention.
FIG. 11 illustrates an example of a memory cell in a semiconductor memory device.
12 is a diagram showing signal waveforms for explaining the operation of the semiconductor memory device of FIG. 10;
FIG. 13 is a circuit diagram showing another example of a semiconductor memory device as related technology corresponding to the present invention;
14 is a diagram showing signal waveforms for explaining a read operation of data “1” in the semiconductor memory device of FIG. 13;
[Explanation of symbols]
6 ... Memory array
60,61… memory block
600 ~ 617 ... Subarray
600A, 600B to 617A, 617B; 600C to 617C; 60A, 60B, 61A, 61B ... Dummy bit line
A ... Current mirror amplifier (amplification circuit for reading)
A '... Tri-state inverter (amplification circuit for rewriting)
B ... Control circuit
S ... Sense amplifier
RR ... Real bit line
D1, D2 ... Dummy bit line part
CLR ... Column selection signal for reading
CLW ... Column selection signal for writing
DBX, DBZ… Data signal line
GBLZ, (GBLX) ... Global bit line in the real bit line section
LBLZ0, LBLZ1 ... Real bit line local bit line
DGBLZ ... Global bit line in the dummy bit line section
DLBLZ0, DLBLZ1 ... Dummy bit line local bit line
MC ... Memory cell
TG0, TG1 ... Transfer gate
V_R... Reference voltage for precharge
V_R'… Sense reference voltage
φ₁... Current mirror amplifier activation signal
/ φ₂... Reactivation inverter activation signal
φ_B... Bit line reset signal
φ_X0, φ_X1... Local bit line selection signal

Claims (5)

Real bit line portion and the dummy bit line portions are both a semiconductor memory device of the hierarchical bit line system consisting of local bit lines and global bit lines,
A transfer gate connecting the local bit line and the global bit line provided near the center of the local bit line;
A read amplifier circuit that differentially amplifies between the potential of the global bit line of the real bit line portion and a reference potential for sensing;
A rewrite amplifier circuit that inverts an output signal of the read amplifier circuit and supplies the signal to the global bit line of the real bit line section via a rewrite transfer gate controlled by a predetermined activation signal; ,
The global bit line of the dummy bit line portion that is charged up to a reference potential for precharging during standby by the bit line precharge control signal and is floating during active,
The semiconductor memory is configured such that data is not written to the memory cells in the dummy bit line portion, and the potential of the global bit line in the dummy bit line portion is supplied as the reference potential for sensing. apparatus. The read amplifier circuit is a current mirror amplifier, and
2. The semiconductor memory device according to claim 1, wherein the rewrite amplifier circuit is a tristate inverter or a latch circuit. Real bit line portion and the dummy bit line portions are both a semiconductor memory device of the hierarchical bit line system consisting of local bit lines and global bit lines,
Multiple memory blocks;
A transfer gate connecting the local bit line and the global bit line provided near the center of the local bit line;
A read amplifier circuit that differentially amplifies between the potential of the global bit line of the real bit line portion and a reference potential for sensing;
A rewrite amplifier circuit that inverts an output signal of the read amplifier circuit and supplies the signal to the global bit line of the real bit line section via a rewrite transfer gate controlled by a predetermined activation signal; ,
The global bit line of the dummy bit line portion that is charged up to a reference potential for precharging during standby by the bit line precharge control signal and is floating during active,
The dummy bit line portion is provided on each side of each memory block ,
The semiconductor memory is configured such that data is not written to the memory cells in the dummy bit line portion, and the potential of the global bit line in the dummy bit line portion is supplied as the reference potential for sensing. apparatus. Real bit line portion and the dummy bit line portions are both a semiconductor memory device of the hierarchical bit line system consisting of local bit lines and global bit lines,
A plurality of subarrays constituting a memory block;
A transfer gate connecting the local bit line and the global bit line provided near the center of the local bit line;
A read amplifier circuit that differentially amplifies between the potential of the global bit line of the real bit line portion and a reference potential for sensing;
A rewrite amplifier circuit that inverts an output signal of the read amplifier circuit and supplies the signal to the global bit line of the real bit line section via a rewrite transfer gate controlled by a predetermined activation signal; ,
The global bit line of the dummy bit line portion that is charged up to a reference potential for precharging during standby by the bit line precharge control signal and is floating during active,
The dummy bit line portion, respectively provided on one side of the sub-arrays to said plurality of sub-arrays,
The semiconductor memory is configured such that data is not written to the memory cells in the dummy bit line portion, and the potential of the global bit line in the dummy bit line portion is supplied as the reference potential for sensing. apparatus. Real bit line portion and the dummy bit line portions are both a semiconductor memory device of the hierarchical bit line system consisting of local bit lines and global bit lines,
A plurality of subarrays constituting a memory block;
A transfer gate connecting the local bit line and the global bit line provided near the center of the local bit line;
A read amplifier circuit that differentially amplifies between the potential of the global bit line of the real bit line portion and a reference potential for sensing;
A rewrite amplifier circuit that inverts an output signal of the read amplifier circuit and supplies the signal to the global bit line of the real bit line section via a rewrite transfer gate controlled by a predetermined activation signal; ,
The global bit line of the dummy bit line portion that is charged up to a reference potential for precharging during standby by the bit line precharge control signal and is floating during active,
The dummy bit line portion, respectively provided on both sides of the sub-arrays to said plurality of sub-arrays,
The semiconductor memory is configured such that data is not written to the memory cells in the dummy bit line portion, and the potential of the global bit line in the dummy bit line portion is supplied as the reference potential for sensing. apparatus.

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