JPS6024740A - Muting circuit - Google Patents

Abstract

PURPOSE:To obtain a muting circuit which stably operates under receiving condition with a large amount of error frequency by judging output of a four-phase DPSK demodulation circuit and generating muting signals. CONSTITUTION:The output A of the four multiplying frequency circuit 34 and output B of the voltage control generator 37 operate the phase lock loop so that the edge of L level will be equal to that of H level under phase lock condition. With edge timing from L level of signal C which delays output of the generator 37 through the delay circuit 40 to H level, the above-mentioned output A is latched through the latch circuit 41. When the phase lock is unlocked due to noise and so on, equality of the edge from L level to H level of output A and B signals disappears, and the output D becomes L level. Then switches 30-33 become open as muting condition.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a muting circuit for a rear door signal in a digital audio communication device using a carrier wave.

(b) Conventional technology As a digital communication system for voice, for example, "12G,
Sound in Hz band satellite broadcasting? PCM f' shown in "Report on Signals" (Radio Certification Council, 4th Division, November 1982)
There is a subcarrier method, and this method uses the back door input terminal 11021(3)14+ as shown in FIGS. 1(a) and (b).
The input sound P signal is converted into a digital signal by an A/D converter (5), and then encoded by an encoder (6) emitted from an error correction circuit, a scrambling circuit, etc. The coded signal is 4-phase DP5K (4-phase Dif
ferenciag Phaee Ethift Ke
After being converted into a subcarrier signal by the ying) circuit (7), it is added to the video signal input from the video signal input terminal (8), and converted to an FM signal by the frequency modulator (9). This IPM signal t! 12G only 2 band transmitter (
1υ, it is transmitted as a radio wave from the parabolic antenna circle. Radio waves transmitted from the parabolic antenna (111) are received by a receiver via a broadcasting satellite α-kun.

On the receiving side (b), after being received by the receiving parabolic antenna t131, it is supplied to the 12 GHz band reception M (141) and applied to the 7M demodulator C151 as an intermediate frequency signal.

The signal demodulated by the demodulator is a video signal and a 4-phase oP.
sK subcarrier signals and separated into 11.sK subcarrier signals. The subcarrier signal is output from each output terminal (Lη and 161st).The subcarrier signal is further demodulated into a 4-phase DP8 by a demodulation circuit α&, and returned to a baseband digital signal T't-
After the TC, it passes through a decoder consisting of a descrambling circuit, an error correction circuit, etc., and a D/A converter circuit, where it is returned to the original audio signal and sent to an audio output terminal.In such a digital audio communication system.

The 4-phase DPEL is
'Digital data errors after demodulation become a problem. Although it is possible to correct the data errors by using the decoder (191 error correction circuits) in FIG. A strong noise is generated.The noise reaches the maximum output level of the audio signal, which is extremely harmful to the sense of hearing.As a countermeasure against this, the output audio signal is usually suppressed by a muting circuit. will be briefly explained with reference to Fig. 2.The digital data demodulated by the 4-phase DPSK demodulation circuit (18) is input to the decoder indicated by the broken line 8 and 3. After the frame-by-frame periodic signal in the data is detected by the circuit (in the circuit), the data is descrambled by the descrambling circuit (in the descrambling circuit).

A data error input to the error correction circuit (a) and the error detection circuit) is detected by the error detection circuit.

The detection signal causes the error correction circuit (a) to perform a correction operation, and if the frequency of data errors is high, the signal is sent to the error correction circuit (a) and then to the data extraction circuit
/ A switch (7) C31 that controls the audio signal output from the A converter (20) to the error detection circuit.
) It is shut off by Kanso, and the output state at the audio output terminal a is set to the no-shinzuki state. 1mJ error detection circuit (foundation)
has an instantaneous error detection function and an error frequency detection function within a certain period of time! Both shall be provided.

According to such a groove bottom, when the frequency of data errors increases, the output audio signal is blocked by the output signal, making it possible to avoid strong noise that is harmful to the auditory sense. However, the error frequency increases further - when the reception state becomes difficult, for example, the synchronization signal detector in the synchronization detection circuit), a detection error occurs in the error detection circuit), and the error occurs. An error also occurs in the operation of the switch GD (to) (c) that operates depending on the detection number, and a strong noise is caused by the back door output Mizuko Q1) @
There is a possibility that it will be output in (e) and (c).

(c) Purpose *In order to resolve such problems with the invention, it is possible to transmit audio to the output terminal without malfunction even in a reception state where the frequency of errors is extremely high. This provides a so-called audio output signal muting circuit.

(D) Structure In the present invention, the method of operating the Mu7177 circuit by the error detection signal of the error detection circuit (E) of the decoder 09 shown in FIG. P
The configuration is such that an accurate muting operation signal can be obtained by detecting the reception state in the SK demodulation circuit θ&.

(e) Examples An embodiment of the present invention will be described with reference to FIG.

From the input terminal output to fL, a 4-phase DP8K signal is manually input to the 4-phase DPSK demodulation circuit shown within the broken line (181). First, the frequency 4 is input to the 4-phase DPSK signal.
After the modulation has been refined by the multiplier circuit (b), the phase comparator (
to).

A phase lock circuit consisting of a loop filter giJ and a voltage controlled oscillator (2) reproduces the carrier wave fl+ after the jitter has been settled. The carrier wave is collected from the output of the voltage controlled oscillator and sent to the data reproducing circuit (C6+1θ Rege
nerator C1rcuit) (c). At the same time, the data reproducing circuit receives the four-phase opsx signal and the output signal of a timing reproducing circuit (Retiming C1rcut) 99, which completely regenerates the timing clock from the signal, and reproduces the data. to the playback data.

Similarly to the above, after being input to the decoder (L9), it is returned to the P double by the D/8 conversion circuit (20), and then output to the output terminal ( 21)
The output is calculated from (4)) and (c). Here, switch (
1) C31) (2) □□□ is an audio signal muting switch, which is opened and closed by the output signal of the latch circuit (6) and the signal smoothed by the integrator (6).
It is structured so that

The latch circuit (6) uses the output of the frequency quadrupling circuit as a data input, and latches a signal obtained by passing the output of the voltage controlled oscillator (9) through a delay circuit. To explain with reference to Fig. 4, in the same figure (A) ld shows the output of the frequency quadrupling circuit (to) in Fig. 3, and [8] shows the output of the voltage controlled oscillator @. 'JL et al. IA) [S) signal, in phase lock state, I, OW level to HIG
The G111 lock loop operates as the edge to level 1 is -iT. (Strictly speaking, it does not match completely,
Also, depending on the type of phase comparator (to) in Fig. 6, the phase lock timing differs depending on the type of phase comparator (to).
Due to the edge timing/gear from the OW level to the I/G GH level, the HIGH level will continue to drop in (A) when the G Z latch 1- is in the phase lock state.If for some reason the lock or ST In the case of In Fig. 4 [1], the state of not being locked is shown as LOW, but even in the state of actually being locked, there is a mixture of LOW and HIGH levels, so the output signal of the latch circuit (6) is After smoothing, it is desirable to open and close the muting switch, and therefore, in the present invention, an integrating circuit (6) is added for this purpose.In one embodiment of the present invention, FIG. Although the delay circuit is connected to the output terminal of the voltage controlled oscillator (b), there is no change in the basic operation even if it is connected to the small output terminal of the frequency quadrupling circuit. ,
Even if the data input and latch clock input of the latch circuit 11) are exchanged, the same operation will occur, only that the logic level indicating the lock state will be inverted.

Although the above description has been made using a four-phase phase modulation method, it can also be applied to a two-phase method if the circuit configuration is properly TR.

(f) Effect: According to the present invention, when the phase-locked loop for reproducing the subcarrier goes out of lock, the out-of-lock state is detected, and the audio signal is cut off by the muting circuit. Ru. In normal digital communication systems, as the received carrier signal level decreases, the S/N of the demodulated subcarrier deteriorates, causing the phase-locked loop that regenerates the subcarrier to lose lock. An out-of-lock state generates strong noise in the demodulated audio signal.

Therefore, according to the muting circuit of the present invention σ) Jin P41, even if the reception condition is extremely deteriorated, it is possible to completely avoid the intense noise that is harmful to the audibility.

[Brief explanation of the drawing]

Fig. 1 is a block circuit diagram for explaining the digital transmission of audio, Fig. 2 is a conventional example of a muting method for sound P signals according to the present invention. FIG. 4 is a block circuit diagram showing a loading circuit, and FIG. 4 is a drawing for explaining the present invention in detail. (161-...Input terminal,...4-phase DPSK demodulation circuit, (Da...Frequency 4 multiplier circuit,)...Phase comparison circuit, (7)...Rougu filter, □□□ ...Voltage controlled oscillator, (g)...Data regeneration circuit, working...
Decoding circuit, (a)...delay circuit, (4D...latch circuit, pronunciation...integrator circuit).

Claims (1)

[Scope of Claims] (1) A phase-locked loop circuit for reproducing the transferred wave 7 from a modulated wave signal modulated by a 7A digital signal, and a phase comparison circuit included in the phase-locked loop circuit. a latch circuit that uses a signal from a first phase input terminal as a data input and uses a first phase input terminal signal as a latch clock input;
an integrating circuit connected to the output side of the latch circuit; a data reproducing circuit that performs modulation using the carrier wave signal regenerated by the phase-locked loop circuit and the modulated wave signal; and the output side of the data reproducing circuit. A decoding circuit connected to the decoding circuit, a digital-to-analog conversion circuit connected to the output side of the decoding circuit, and a switch circuit connected between the output end of the digital-to-analog conversion circuit and the back door output terminal. , the switch circuit '&0N-OFF is turned off by the output of the integration circuit.
Control I11] An audio signal muting circuit for a digital communication device characterized by: (2) Claim 1 wherein a delay circuit is connected between the first phase input terminal or the second phase input terminal of the phase comparison circuit and the data input or latch clock input of the latch circuit. muting circuit.