JPH09321811A - Digital communication system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the communication system surely conducting digital signal demodulation even when a demodulator with a narrow demodulation frequency range is used. SOLUTION: A digital modulator 1 applies digital modulation to input data in matching with a clock signal (CLK), the digital signal is modulated on a carrier outputted from a phase locked loop(PLL) synthesizer 5a and the resulting signal is sent to a digital demodulator 6, a reception signal is modulated on a reception signal carrier outputted from a PLL synthesizer 5b at the demodulator 6 and fed to the digital demodulator 6, the signal is demodulated in matching with the clock signal CLK recovered by a clock recovery circuit 7 and data are extracted. The CLK is given to a PLL synthesizer 5a and the clock signal CLK recovered by the clock recovery circuit 7 is fed to the PLL synthesizer 5b to obtain a reference frequency of the PLL synthesizers 5a, 5b from the same signal source (CLK) to make a local frequency of the carrier outputted from the PLL synthesizers 5a, 5b in matching with each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital communication system using a modulator and a demodulator having a phase lock circuit.

[0002]

2. Description of the Related Art FIG. 3 shows an example of a digital communication system in which input data is digitally modulated on a modulator side, a digital signal is transmitted, and the digital signal is received on a demodulator side and demodulated and taken out. .

In the figure, a PLL synthesizer (phase synchronization circuit) 5a is provided on the digital modulator 1 side as a modulator via a mixer 2a, and a mixer 2b on the digital demodulator 6 side as a demodulator. A PLL synthesizer 5b is provided through the PLL synthesizer 5a, and the PLL synthesizers 5a and 5b are respectively provided with reference signal generation circuits 4a and 4b functioning as reference frequency generators. These PLL synthesizers 5a and 5b function as local oscillators that output a carrier wave of a local frequency that is phase-locked (phase-locked) with the reference frequency f _ref generated from the reference signal generation circuits 4a and 4b. The reference frequencies generated by the reference signal generating circuits 4a and 4b are equal to each other at the frequency _fref .

In this system, the digital modulator 1 digitally modulates input data in accordance with a clock signal (CLK) and outputs it at a frequency f _IF1 , and this digital signal is converted into a carrier wave from a PLL synthesizer 5a by a mixer 2a. After being conveyed, it is amplified by the amplifier 3a and transmitted.

The transmission signal (f _RF ) is amplified by the amplifier 3b and added to the digital demodulator 6 side. The reception signal is a local signal for carrying the reception signal output from the PLL synthesizer 5b by the mixer 2b. Different frequencies f _IF2 are mixed into carrier waves having different frequencies.
Is frequency-converted to and is applied to the digital demodulator 6. Further, the clock signal reproduced by the clock reproduction circuit 7 is added to the digital demodulator 6, and the digital demodulator 6 digitally demodulates the received signal in accordance with the reproduced clock signal to take out data.

[0006]

By the way, the local frequencies of the carrier waves output from the PLL synthesizers 5a and 5b are different if the reference frequencies are different. Therefore, in the system as shown in FIG. 3, variations in accuracy of the reference signal generation circuits 4a and 4b, temperature difference,
If there is a difference in aging, the reference signal generation circuits 4a and 4b.
There is a problem that the local frequencies of the PLL synthesizers 5a and 5b are also different because the reference frequencies generated from the are different. Then, when the demodulation frequency range of the digital demodulator 6 is narrow, the frequency of the signal input to the digital demodulator 6 deviates from the frequency that can be demodulated by the digital demodulator 6, and there is a problem that data cannot be demodulated. It was

The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to demodulate a digital signal digitally modulated by the modulator side even if the demodulation frequency range of the demodulator is narrow. The purpose of the present invention is to provide a digital communication system that can surely demodulate.

[0008]

Means for Solving the Problems To achieve the above object, the present invention provides means for solving the problems by the following constitution. That is, according to the present invention, in a digital communication system in which input data is digitally modulated on the modulator side, the digital signal is received on the demodulator side, demodulated and taken out, the digital signal is provided on the modulator side. From the same signal source, the reference frequency of one or more phase-locked circuits that output carrier waves for carrier and the reference frequency of one or more phase-locked circuits that are provided on the demodulator side and output carrier waves for receiving signals are transmitted from the same signal source. The feature is that it is obtained.

Further, the signal source is a clock signal of input data, the modulator side inputs the clock signal to a phase synchronization circuit, and the demodulator side clocks the clock signal via a clock regeneration circuit for regenerating the clock signal. It is also a characteristic configuration of the present invention that the signals are input to the phase-locked loops and the reference frequencies of these phase-locked loops are set to integral multiples or fractions of the clock signal.

Further, the demodulator side is provided with a delay circuit that delays the digital signal demodulation timing by a delay time that is equal to or longer than the total time required for the clock recovery circuit to recover the clock and the phase synchronization circuit synchronizes with the clock signal. That is, the modulator side is provided with a frequency conversion circuit that frequency-converts the clock signal of the input data and adds it to the phase synchronization circuit, and the modulator side frequency-converts the clock signal reproduced by the clock reproduction circuit. A frequency conversion circuit added to the phase synchronization circuit is also a characteristic configuration of the present invention.

In the present invention having the above-mentioned structure, the reference frequency of the phase locked loop circuit provided on the modulator side and the reference frequency of the phase locked loop circuit provided on the demodulator side are the same, for example, a clock signal of input data. Since the configuration is obtained from the signal source, the local frequency output from the phase synchronization circuit on the modulator side becomes equal to the local frequency output from the phase synchronization circuit on the demodulator side, and it is used to carry the received signal received by the demodulator. The frequency change of the carrier wave disappears. Therefore, even if the temperature difference between the modulator side and the demodulator side or a difference due to aging occurs, the frequency of the received signal received by the demodulator does not change, and even if the demodulator demodulation frequency range is narrow, It becomes possible to perform demodulation, and the above problems are solved.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. In the description of the present embodiment, the same reference numerals are given to the same parts as those in the conventional example, and the overlapping description will be omitted. FIG. 1 shows a main configuration of a first embodiment of a digital communication system according to the present invention. The most characteristic feature of the present invention, which is different from the conventional example, is that it is provided on the digital modulator 1 side. PLL synthesizer 5
The reference frequency of a and the reference frequency of the PLL synthesizer 5b provided on the digital demodulator 6 side are obtained from the same signal source. That is, in this embodiment, the signal source is the clock signal (CLK) of the input data, the clock signal is input to the PLL synthesizer 5a on the digital modulator 1 side, and the clock recovery circuit 7 is input on the digital demodulator 6 side. The clock signal is input to the PLL synthesizer 5b via the PLL.
The reference frequency of the synthesizers 5a and 5b is an integral multiple or an integral fraction of the clock signal.

Further, in this embodiment, the time required for the clock recovery circuit 7 to recover the clock and the time required for the PLL synthesizer 5b to synchronize with the clock signal after the digital signal f _ref is input to the digital demodulator 6 side. The delay circuit 8 is provided to delay the digital signal demodulation timing by a time equal to or longer than the total time.

The example of the present embodiment is configured as described above, and in the example of the present embodiment as well, the digital signal from the digital modulator 1 is carried to the carrier wave output from the PLL synthesizer 5a by substantially the same operation, and the digital signal is transmitted. The reception signal transmitted to the demodulator 6 side and output on the carrier wave output from the PLL synthesizer 5b is demodulated by the digital demodulator 6, but in the present embodiment, the reference frequency of the PLL synthesizer 5a and the PLL synthesizer 5b. Since the reference frequency is obtained from the clock signal of the input data, which is the same signal source, each PLL synthesizer 5a,
The local frequencies output from 5b become equal, and the frequency change caused by the frequency conversion by the mixers 2a and 2b disappears. Therefore, even if a temperature difference between the digital modulator 1 side and the digital demodulator 6 side or a difference due to secular change occurs, the frequency f _{IF2 of the} received signal does not change, and therefore the demodulation frequency range of the digital demodulator 6 is narrow. Even in this case, the digital signal demodulation can be surely performed.

Further, in this embodiment, the delay circuit 8 is provided, and the delay time is equal to or more than the total time of the clock recovery circuit 7 for clock recovery and the time until the PLL synthesizer 5b synchronizes with the clock signal. , Because the digital signal demodulation timing is delayed,
It is possible to perform demodulation by the digital demodulator 6 after the frequency becomes stable, and it is possible to reliably prevent data loss.

FIG. 2 shows a main configuration of a second embodiment of the digital communication system according to the present invention. This example of the present embodiment is configured almost in the same manner as the example of the first embodiment, and the characteristic of the example of the present embodiment different from the example of the first embodiment is that the digital modulator 1 side and the digital demodulator 6 side are different. That is, the frequency conversion circuits 9a and 9b are provided respectively. The frequency conversion circuit 9a is a circuit that frequency-converts the clock signal of the input data and adds it to the PLL synthesizer 5a. The frequency conversion circuit 9b frequency-converts the clock signal reproduced by the clock reproduction circuit 7 and applies it to the PLL synthesizer 5b. This is a circuit that converts each clock signal into the same frequency as a reference frequency and adds it to the PLL synthesizers 5a and 5b.

Generally, in a digital communication system,
When the data transmission rate changes, the baseband clock signal frequency changes, which changes the frequency f _ref of the digital signal. However, as in the present embodiment, the frequency conversion circuit 9a converts the clock signal of the input data into the frequency conversion circuit 9a. The frequency f _RF of the digital modulation wave does not change even if the data transmission rate changes, if the frequency is converted via the frequency converter and is applied to the PLL synthesizer 5a and the carrier for digital signal carrier is output from the PLL synthesizer 5a.

The example of the present embodiment is configured as described above, and the example of the present embodiment can achieve the same effect by the operation substantially similar to that of the example of the first embodiment.

Further, according to the present embodiment, since the frequency modulator 9a is provided on the digital modulator 1 side and the clock signal of the input data is frequency-converted and added to the PLL synthesizer 5a, the PLL synthesizer 5a is provided. It becomes possible to keep the reference frequency constant.
Even if the data transmission rate changes, the frequency f _RF of the digital modulated wave to be transmitted can be _kept constant. In the present embodiment, the frequency conversion circuit 9b is also provided on the digital demodulator 6 side to frequency-convert the clock signal reproduced by the clock reproduction circuit 7 and perform PLL.
Since the configuration is added to the synthesizer 5b, it is possible to perform demodulation without changing _fIF2, and it is possible to achieve the same effect of reliably demodulating a signal even when the demodulation frequency of the digital demodulator 6 is narrow. it can.

It should be noted that the present invention is not limited to the above-described embodiment, but can adopt various embodiments. For example,
In each of the above embodiments, the delay circuit 8 is provided on the digital demodulator 6 side, but the delay circuit 8 can be omitted. However, the clock recovery circuit 7 is provided by providing the delay circuit 8.
Time required for clock recovery and PLL synthesizer 5b
By delaying the digital signal demodulation timing by a delay time that is equal to or longer than the total time required to synchronize with the clock signal, the digital demodulator 6 performs demodulation after the frequency is reliably stabilized, and data loss is reliably prevented. Therefore, it is preferable to provide the delay circuit 8.

Further, in the above embodiment, one PLL synthesizer 5a is provided on the digital modulator 1 side and one PLL synthesizer 5b is also provided on the digital demodulator 6 side to configure the digital communication system. Also, the number of PLL synthesizers provided on the demodulator side is not always one, and two PLL synthesizers are provided on either side of the modulator and the demodulator.
The digital communication system may be configured by providing at least two PLL synthesizers, or the digital communication system may be configured by providing at least two PLL synthesizers on both the modulator side and the demodulator side.

[0022]

According to the present invention, the reference frequency of the phase locked loop circuit provided on the modulator side and the reference frequency of the phase locked loop circuit provided on the demodulator side are obtained from the same signal source. Even if there is a large variation in accuracy, a large temperature difference, or a large difference in aging between the demodulator side and the demodulator side, the local frequencies of the respective phase-locked circuits output corresponding to the reference frequency can be made equal. Therefore, it becomes possible to eliminate the frequency change when the frequency is converted by the carrier of this local frequency, and even if the demodulation frequency range on the demodulator side used in the system is narrow, the demodulator reliably demodulates the digital signal. You can take it out.

Further, the signal source is a clock signal of input data, the modulator side inputs the clock signal into a phase synchronization circuit, and the demodulator side clocks the clock signal via a clock regeneration circuit for regenerating the clock signal. According to the present invention, in which signals are input to the phase-locked loop circuit and the reference frequency of these phase-locked loop circuits is an integral multiple or a fraction of the clock signal, the clock signal of the input data can be used to facilitate the operation. Further, it is possible to surely make the reference frequency of the phase synchronization circuit on the modulator side and the reference frequency of the phase synchronization circuit on the demodulator side coincide with each other to obtain the above effect.

Further, the demodulator side is provided with a delay circuit for delaying the digital signal demodulation timing by a delay time which is equal to or longer than the total time required for the clock recovery circuit to recover the clock and the phase synchronization circuit to synchronize with the clock signal. According to the present invention, it becomes possible to perform digital signal demodulation on the demodulator side after the frequency of the received signal is reliably stabilized, and it is possible to reliably prevent data loss and the like.

Further, the modulator side is provided with a frequency conversion circuit for frequency-converting the clock signal of the input data and adding it to the phase synchronization circuit, and the modulator side frequency-converts the clock signal reproduced by the clock reproduction circuit. According to the present invention in which the frequency conversion circuit added to the phase synchronization circuit is provided, even if the data transmission rate changes and the frequency of the clock signal changes, the reference frequency applied to the phase synchronization circuit on the modulator side is changed. Since the reference frequency can be made constant and the demodulator side can also make the same constant frequency, the frequency of the digital modulation signal does not change even in systems with different data transmission rates, and is applied as is. It is possible to

[Brief description of drawings]

FIG. 1 is a main part configuration diagram showing a first embodiment of a digital communication system according to the present invention.

FIG. 2 is a main part configuration diagram showing a second exemplary embodiment of a digital communication system according to the present invention.

FIG. 3 is an explanatory diagram showing an example of a conventional digital communication system.

[Explanation of symbols]

 1 Digital Modulator 2a, 2b Mixer 5a, 5b PLL Synthesizer 6 Digital Demodulator 7 Clock Recovery Circuit 8 Delay Circuit 9a, 9b Frequency Converter Circuit

Claims (4)

[Claims] 1. A digital communication system for transmitting a digital signal obtained by digitally modulating input data on the modulator side, receiving the digital signal on the demodulator side, demodulating and extracting the digital signal, and providing a digital signal carrier on the modulator side. Is provided on the demodulator side and the reference frequency of one or more phase-locked loop circuits for outputting a carrier wave for receiving 1
A digital communication system characterized in that the reference frequencies of a plurality of phase-locked loops are obtained from the same signal source. 2. The signal source is a clock signal of input data, the modulator side inputs the clock signal to a phase synchronization circuit, and the demodulator side reproduces the clock signal via a clock regeneration circuit. 3. The digital communication system according to claim 1, wherein the phase synchronization circuits are input to the phase synchronization circuits, and the reference frequencies of these phase synchronization circuits are set to integral multiples or fractions of the clock signal. 3. The demodulator side is provided with a delay circuit that delays the digital signal demodulation timing by a delay time that is equal to or longer than the total time required for the clock recovery circuit to recover the clock and the phase synchronization circuit synchronizes with the clock signal. The digital communication system according to claim 2, wherein 4. A frequency converter circuit is provided on the modulator side for frequency-converting a clock signal of input data and adding it to a phase synchronization circuit, and a demodulator side is for frequency-converting the clock signal reproduced by the clock reproducing circuit. 4. The digital communication system according to claim 2, further comprising a frequency conversion circuit added to the phase synchronization circuit.