JP2992116B2 - Digital modulation scheme for spread spectrum communication. - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a digital modulation system in spread spectrum communication. For example, it is applied to weak wireless communication, mobile wireless communication, and private wireless communication.

[0002]

2. Description of the Related Art In order to transmit a digital signal, a voltage-controlled oscillator (FSK) which directly modulates with a modulation data is usually used.
(Frequency Shift Keying)
Although a modulation method is used, since the clock frequency is not stable in this method, there is a possibility that a pseudo-noise (PN) signal may be out of synchronization or a demodulation error may occur on the receiver side. For the spread spectrum communication method using clock speed modulation, see “Latest Spread Spectrum Communication Method” (RCDixon
Author, Tateno, Kataoka, Iida translation, Jatec Publishing, pp.125-127
53.11.30). According to this, as a concrete method of realizing clock speed modulation, a method of stabilizing by a PLL (phase locked loop) is introduced. This is intended for transmitting analog signals.
Not suitable for digital signal transmission. The present invention aims at transmitting digital information in spread spectrum communication using clock rate modulation, and aims at stabilizing a pseudo-noise (PN) clock frequency to be modulated.

[0003]

OBJECTIVE present invention has been made in view of such circumstances described above, by there use the clock by the digital logic circuit to the reference frequency, a sufficiently stable frequency frequency modulated output of the pseudo-noise (PN) Clock It is possible,
It is an object of the present invention to provide a digital modulation method in spread spectrum communication in which synchronization is not lost on the receiver side beyond a tracking range of a delay lock loop (DLL) and digital data transmission is reliably performed. It is a thing.

[0004]

To achieve the above object, the present invention provides (1)
The spread spectrum communication system by the clock speed modulation
Ri, your a digital modulation scheme for transmitting a digital signal
A predetermined reference clock signal according to the modulation data ,
Alternatively, a signal obtained by removing the number of clocks corresponding to the frequency division ratio N ( an integer of 2 or more) of the reference clock set in the frequency divider from the reference clock signal is output, and the signal is phase-locked with a phase locked loop.
(PLL) is input as a reference signal to perform phase synchronization ,
The output signal of the phase locked loop (PLL) is converted to pseudo noise (P
N) applying a frequency modulation by the generator clock or to transmit more digital signal to spread spectrum communication system according to (2) clock speed modulation di
In digital modulation scheme, in accordance with the modulation data, a predetermined <br/> reference clock signal or from the reference clock signal, min
And outputs the removed signal the number of clocks corresponding to the division ratio of the reference clock set to divider N (2 or more integer), by dividing the signal to the frequency of the pseudo-noise (PN) clock, the
Be between the divided signal of the pseudo-noise (PN) generator clock
Applying a frequency modulation in Rukoto, or in a digital modulation scheme and more, to transmit a digital signal to spread spectrum communication system according to (3) clock speed modulation,
A predetermined reference clock signal or a predetermined reference clock signal
The reference clock signal the number of clocks and outputs a removal or addition signal corresponding to the division ratio of the reference clock is set to the divider N (2 or more integer) from the phase of the signal locked loop (PLL) of multiplying the phase synchronization by entering as a reference signal, the output signal of the phase locked loop (PLL) applying a frequency modulation by the clock of the pseudo-noise (PN) generator, or (4) clock speed more spread spectrum communication system by the modulation, the digital modulation scheme for transmitting a digital signal, in accordance with the modulation data,
A predetermined reference clock signal or a signal obtained by removing or adding the number of clocks from the reference clock signal in accordance with the frequency division ratio N ( an integer of 2 or more) of the reference clock set in the frequency divider is output. divides up the frequency of the pseudo-noise (PN) clock, pseudo-noise (PN) flights then frequency dividing the signal
Applying frequency modulation by using the clock of the genital ,
Alternatively, (5) More spread spectrum communication system according to clock speed modulation, and transmits the digital signal digital
In the modulation method, in accordance with the modulation data, pseudo-noise (P
N) A reference clock signal having a frequency obtained by dividing the clock by M (an integer of 2 or more), and a signal obtained by removing or adding the number of clocks from the reference clock signal according to the frequency division ratio of the reference clock (an integer of 2 or more). And outputs the signal as a reference signal of a phase locked loop (PLL).
A signal obtained by dividing the output signal of L) by M is input as a comparison signal of the phase locked loop (PLL) to perform phase synchronization ,
The output of the phase locked loop (PLL) is converted to pseudo noise (PN).
The frequency modulation is performed by using the clock of the generator . Hereinafter, a description will be given based on examples of the present invention.

FIG. 1 is a circuit diagram of a transmitter for explaining one embodiment of a digital modulation method in spread spectrum communication according to the present invention. In the figure, reference numeral 1 denotes a crystal oscillator, 2 denotes a frequency divider, and 3 denotes a frequency divider. D flip-flops, 4, 7, 8 are AND
Gate circuits, 5, 6 are inverters, 9 is an OR gate circuit, 10 is a phase comparator, 11 is a loop filter, 12 is a voltage controlled oscillator (VCO: Voltage Controlled Oscillat).
or) and 13 are phase locked loops (PLL: Phase Locked).
Reference numeral 14 denotes a pseudo noise (PN) signal generator, reference numeral 15 denotes a frequency conversion circuit, and reference numeral 16 denotes a power amplification circuit. 2 (a) to 2 (h) are diagrams showing a signal waveform at the time of modulation and a state of a demodulated signal. Here, the dividing ratio N of the reference clock is 8, and the ratio k between the modulation data rate and the reference clock is k = 1
It is 6.

The output frequency of the crystal oscillator 1 is a reference clock frequency fc of a pseudo noise (PN) signal, and the reference clock frequency fc is divided by the frequency divider 2 into 1 / N (FIG. 2B). Next, the modulation data shown in FIG. 2A is synchronized with the clock frequency fc / N obtained by frequency division by the D flip-flop 3. The divided clock is gated with the modulation data, and the frequency-divided clock is output from the AND gate circuit only when the modulation data is "1" (FIG. 2).
(E)). On the other hand, the reference clock shown in FIG.
An inverted clock fci (FIG. 2D) of (c) is prepared,
By the logic of the next inverter 6, AND gate circuit 7, and OR gate circuit 9, the inverted clock fci is output when the divided clock is H, and the reference clock fc is output when the divided clock is L. Therefore, while the modulation data is "1", the reference clock fc and the inverted clock fci are output alternately every half cycle of the divided clock (FIG. 2 (f)). By these operations, every one cycle of the divided clock, 1
Since the number of clocks is reduced by the number of clocks, the frequency is correspondingly reduced.

This signal is input to a reference signal input of a phase locked loop (PLL) 13 including a phase comparator 10, a loop filter 11, and a voltage controlled oscillator (VCO) 12. Thus, when the modulation data is "0", the reference clock f
A stable pseudo noise (PN) clock is generated in synchronization with c. When the modulation data is "1", the phase is suddenly changed to synchronize with the signal shown in FIG. 2F, so that the phase changes smoothly. This state is shown in FIG. By doing so, loss of synchronization due to a sudden phase change on the receiver side can be prevented. The average frequency during which the modulation data is “1” is represented by f _L (<f
c).

By the above operation, the clock frequency of the pseudo noise (PN) signal becomes f _L ,
When it is “0”, fh (= fc) is obtained, and frequency shift modulation (FSK) is applied to the clock of the pseudo noise (PN) signal.
At this time, the reference signal input of the phase locked loop (PLL) is very stable because it is based on a digital logic circuit, and the phase locked loop (PLL) is applied.
fh (= fc) and f _L have very stable frequencies. Therefore, on the receiver side, there is no possibility that the pseudo noise (PN) clock frequency exceeds the tracking range of the delay locked loop (DLL). Also, according to this method, the average frequency f _L can be changed by changing the frequency division ratio N, and thus FSK (frequency shift keying)
Can be changed.

Next, an output clock (FIG. 2 (g)) from the phase locked loop (PLL) is input as a clock of the pseudo noise (PN) signal generator 14 to generate a pseudo noise (PN) signal. The signal is multiplied by a carrier frequency, frequency-converted by a frequency conversion circuit 15, and the signal is amplified by a power amplification circuit 16, and then a radio wave is output from an antenna.

FIG. 3 is a circuit diagram of a receiver for explaining an embodiment of a digital modulation system in spread spectrum communication according to the present invention. In FIG. 3, reference numeral 21 denotes a radio frequency (R).
F) an amplification circuit, 22 is a frequency conversion circuit, 23 is a correlation network, 24 is a loop filter, 25 is a voltage controlled oscillator (VCO), 26 is a pseudo noise (PN) signal generator, 2
7 is a delay locked loop (DLL), 28 is an identification circuit, 2
9 is a timing generation circuit.

A signal input from the antenna is dropped to an intermediate frequency by a frequency conversion circuit 22, and the correlation network 23, a loop filter 24, and a voltage controlled oscillator (VC
O) 25, and input to a delay lock loop (DLL) 27 comprising a pseudo noise (PN) signal generator 26. By this delay lock loop (DLL) 27, pseudo noise (P
N) Synchronize the signals and use a voltage controlled oscillator (VC
O) The demodulated signal of the FSK-modulated pseudo noise (PN) clock is output to the control voltage of 25, that is, the output of the loop filter 24 (FIG. 2 (h)). The clock timing of the data is reproduced from this signal by a timing generation circuit 29 such as a phase locked loop (PLL), and the identification circuit 2
The demodulated data can be obtained by judging "1" and "0" of the data at 8.

Next, a modulation index when a pseudo noise (PN) clock is subjected to FSK (Frequency Shift Keying) modulation according to the present invention will be described. Data rate of modulated data: fd (period Td = 1 / f
d), reference clock: fc, and fc = k · fd (k is a positive integer). Assuming that the division ratio of the reference clock is N, the frequency of the divided clock is fb = fc / N =
k · fd / N Here, N is an integer of N ≧ 2 and fb ≧ fd, so k is an integer of k ≧ 2. Frequency f _L of the modulated pseudo noise (PN) clock when the modulation data is “1”
Is one cycle (1 / fb) of the divided clock from FIG.
Since the reference clock is reduced by one clock every time, f _L = (N−1) / (1 / fb) = [(N−1) / N] · fc. Therefore, the modulation index m is obtained by multiplying the difference between the respective frequencies by the period of the data, so that m = (fh−f _L ) · Td = {fc− (N−1) · fc / N} · Td = fc / (N · fd) Since fc = k · fd, m = k / N. Therefore, the ratio k between the modulated data and the reference clock is
Is a predetermined value, it can be seen that the modulation index can be changed as in the above equation by the frequency division ratio N of the reference clock of the pseudo noise (PN) signal. However, 1 ≦ m ≦ k / 2 under given conditions.

In the above, a phase locked loop (PLL) is used.
L) has a point that the circuit is complicated and expensive, and the calculation of the circuit constant is troublesome. To solve that point,
According to another embodiment of the present invention described below.
FIG. 4 is a circuit diagram of a transmitter for explaining another embodiment of the digital modulation system in spread spectrum communication according to the present invention. In the figure, reference numeral 30 denotes a frequency divider, which otherwise operates in the same manner as in FIG. The parts have the same reference numbers. FIGS. 5A to 5H are diagrams showing a signal waveform at the time of modulation and a state of a demodulated signal.

The output frequency fc of the crystal oscillator 1, and M times of pseudo-noise (PN) clock frequency, divides to 1 / N the standard clock frequency fc by the frequency divider 2 (FIG. 5
(B)). Next, the modulation data shown in FIG. 5A is synchronized with the clock frequency fc / N obtained by frequency division by the D flip-flop 3. The divided clock is gated with the modulation data, and the frequency-divided clock is output from the AND gate circuit only when the modulation data is "1" (FIG. 5).
(E)). On the other hand, the reference clock shown in FIG.
The inverted clock fci (FIG. 5D) of (c) is prepared,
By the logic of the next inverter 6, AND gate circuit 7, and OR gate circuit 9, the inverted clock fci is output when the divided clock is H, and the reference clock fc is output when the divided clock is L. Therefore, while the modulation data is "1", the reference clock fc and the inverted clock fci are alternately output every half cycle of the divided clock (FIG. 5 (f)). By these operations, every one cycle of the divided clock,
Since the number of clocks is reduced by one clock, the frequency is correspondingly reduced.

A pseudo noise (PN) clock is obtained by dividing this signal by M by the frequency divider 30. As a result, when the modulation data is "0", a stable pseudo noise (PN) clock is generated by dividing the reference clock fc by M. Also,
When the modulation data is "1", the signal shown in FIG.
In order to divide the frequency, an abrupt change in the phase is smoothed so that the phase changes smoothly. This state is shown in FIG. By doing so, loss of synchronization due to a sudden phase change on the receiver side can be prevented. The average frequency during which the modulation data is “1” is f _L (<fc).

By the above operation, the clock frequency of the pseudo noise (PN) signal becomes f _L , when the modulation data is “1”.
When it is “0”, fh (= fc / M) is obtained, and the pseudo noise (P
N) Frequency shift modulation (FSK) is applied to the clock of the signal. Since the generation of the pseudo noise (PN) clock described above is performed by a digital logic circuit, fh and f _L
Has a very stable frequency. Therefore, on the receiver side, there is no possibility that the pseudo noise (PN) clock frequency exceeds the tracking range of the delay locked loop (DLL). Further, according to this method, the average frequency f _L can be changed by changing the frequency division ratios N and M, and therefore, the modulation index of FSK (frequency shift keying) can be changed.

Next, a pseudo noise (PN) clock (FIG. 5)
(G)) is input as a clock of the pseudo noise (PN) signal generator 14 to generate a pseudo noise (PN) signal. The signal is multiplied by a carrier frequency, frequency-converted by a frequency conversion circuit 15, and the signal is amplified by a power amplification circuit 16, and then a radio wave is output from an antenna. Note that the circuit configuration of the receiver in this embodiment is the same as that described in FIG.

Next, a modulation index when a pseudo noise (PN) clock is subjected to FSK (Frequency Shift Keying) modulation according to the present invention will be described. Data rate of modulated data: fd (period Td = 1 / f
d), reference clock: fc, and fc = k · fd (k is a positive integer). Assuming that the division ratio of the reference clock is N, the frequency of the divided clock is fb = fc / N =
k · fd / N Here, N is an integer of N ≧ 2 and fb ≧ fd, so k is an integer of k ≧ 2. In addition, pseudo noise (P
N) The clock is obtained by dividing the reference clock by M. Modulated pseudo noise (P) when the modulation data is "1"
N) The frequency f _L of the clock is such that the reference clock is reduced by one clock every one cycle (1 / fb) of the divided clock from FIG.
The frequency f _L ′ of (f) is expressed as f _L ′ = (N−1) / (1 / fb) = [(N−1) / N] · fc. F _L = [(N−1) / N · M] · fc Since the frequency division by M is performed to obtain a pseudo noise (PN) clock, the modulation index m is obtained by multiplying the difference between the respective frequencies by the data period. M = (fh−f _L ) · Td = {fc− (N−1) · fc / N · M} · Td = fc / N · M · fd Since fc = k · fd, m = K / (N · M).

Therefore, since the ratio k between the modulated data and the reference clock is a predetermined value, the frequency division ratio N of the reference clock of the pseudo noise (PN) signal and the division ratio for obtaining the pseudo noise (PN) clock are obtained. It can be seen that the modulation index can be changed as in the above equation by changing the circumference ratio M. However, 1 ≦ m ≦ k / 2 under given conditions.

If the frequency modulation can be applied only to lower the frequency with respect to the center frequency, the center frequency changes to the lower side every time the modulation index changes on the receiving side. In this case, it is necessary to adjust the determination level, but in order to solve this point, a further embodiment according to the present invention described below may be used. FIG. 6 is a diagram showing still another embodiment of the digital modulation system in the spread spectrum communication according to the present invention.
Is a crystal oscillator, 32 and 34 are 1/2 frequency dividers, 33 is 1 /
N frequency dividers, 35 and 36 are D flip-flops, 38a to
38f is an AND gate circuit, 39a to 39f are inverters, 40 is an OR gate circuit, and other parts having the same functions as those in FIG. 1 are denoted by the same reference numerals.

FIGS. 7 and 8 show signal waveforms and demodulated signals during modulation. FIG. 7 shows a case where the modulation data is "1" and FIG. 8 shows a case where the modulation data is "0". . Here, the division ratio N of the reference clock is set to 4. The output frequency of the crystal oscillator 31 is set to 2fc, which is twice the reference clock frequency fc of the pseudo noise (PN) signal (FIG. 7D), and the reference clock fc (FIG. 7E) by the 1/2 frequency divider 32. Get) This fc is divided by the frequency divider 33 into 1 / N (FIG. 7B), and further divided by the 1/2 frequency divider 34 into fc / 2N.
(FIG. 7C). Next, the modulated data is synchronized with the clock fc / 2N obtained by dividing the frequency by the D flip-flop 35.

The signal when the modulation data is "1" will be described with reference to FIG. When the N-divided clock is “1” and the 2N-divided clock is “1”, a signal (A) obtained by delaying the reference clock by 負 cycle with a negative signal of the frequency clock 2fc which is twice the frequency is output. When the N-divided clock is “0” and the 2N-divided clock is “1”, the reference signal (B) is output.
When the N-divided clock is “1” and the 2N-divided clock is “0”, a negative signal (C) of the signal (A) is output. When the N-divided clock is “0” and the 2N-divided clock is “0”, a negative signal (D) of the reference signal is output. Therefore, while the modulation data is "1", the signals (A), (B), (C), and (D) are output in order for each half cycle of the N-divided clock (FIG. 7 (f)). Will be. By these operations,
Since the number of clocks increases by one clock for each cycle of the 2N frequency-divided clock, the frequency increases accordingly.

The signal when the modulation data is "0" will be described with reference to FIG. When the N-divided clock is “1” and the 2N-divided clock is “1”, a signal (A) is output in which the reference clock is delayed by a quarter period with a negative signal of the frequency clock 2fc which is twice the frequency. When the N-divided clock is “0” and the 2N-divided clock is “1”, a negative signal (D ′) of the reference signal is output. When the N-divided clock is “1” and the 2N-divided clock is “0”, a negative signal (C) of the signal (A) is output. When the N-divided clock is "0" and the 2N-divided clock is "0", the reference signal (B ') is output. Therefore, during the modulation data “0”, the signals (A), (D ′), (C), and (B ′) are output in order for each half cycle of the N-divided clock (FIG. 8F). ) By these operations, the number of clocks is reduced by one clock every one cycle of the 2N frequency-divided clock, so that the frequency is reduced accordingly. This signal is converted into a phase locked loop (PL) comprising a phase comparator 10, a loop filter 11, and a voltage controlled oscillator (VCO) 12.
L) Input to 13 reference signal input. Thereby, the rapid change of the phase is smoothed, and the phase is smoothly changed. This state is shown in FIGS. 7 (g) and 8 (g).
By doing so, it is possible to prevent loss of synchronization due to a sudden phase change on the receiver side. Modulation data is "1"
The average frequency between “0” and “0” is fh (> fc) and f _L (<fc).

According to the above operation, the clock frequency of the pseudo noise (PN) signal becomes fh when the modulation data is "1",
When it is “0”, it becomes f _L , and the frequency shift modulation (FS
K). At this time, the reference signal input to the phase locked loop (PLL) is very stable because it is based on a digital logic circuit. Further, since the phase locked loop (PLL) is applied, fh and f _L have very stable frequencies. Becomes Therefore, on the receiver side, the pseudo-noise (PN) clock frequency is reduced by the delay locked loop (DLL).
There is no danger of exceeding the following range. Further, according to this method, by changing the dividing ratio N, the average frequencies fh and f _L can be changed, and therefore, the modulation index of FSK (frequency shift keying) can be changed. Further, in the frequency modulation according to this embodiment, the same modulation is applied to the higher and lower frequencies around the reference signal frequency. Therefore, on the receiving side, the demodulation level for judging whether data is "1" or "0" at the time of demodulation is adjusted to the center frequency, so that accurate demodulation can be performed without changing the modulation index. Can be.

Next, the output clock (FIG. 7 (g) and FIG. 8 (g)) from the phase locked loop (PLL) is converted into a pseudo noise (P
N) Pseudo noise (P) input as signal generator clock
N) Generate a signal. The signal is subjected to frequency conversion by multiplying the carrier frequency of the signal, the signal is amplified by a power amplifier circuit, and then a radio wave is output from the antenna. Note that the circuit configuration of the receiver in this embodiment is the same as that described in FIG. That is, the signal input from the antenna is dropped to the intermediate frequency by the frequency conversion circuit 22, and a delay lock comprising a correlation network 23, a loop filter 24, a voltage controlled oscillator (VCO) 25, and a pseudo noise (PN) signal generator 26 is provided. The signal is input to a loop (DLL) 27.
The delay lock loop (DLL) 27 synchronizes the pseudo noise (PN) signal and controls the control voltage of the voltage controlled oscillator (VCO) 25, that is, the loop filter 2.
4 output a demodulated signal of a pseudo noise (PN) clock subjected to FSK modulation (FIG. 7 (h), FIG. 8).
(H)). From this signal, the clock timing of the data is reproduced by a timing generation circuit 29 such as a phase locked loop (PLL) and the like, and “1” and “0” of the data are discriminated by the identification circuit 28.
, Demodulated data can be obtained.
At this time, even if the modulation index is changed, “1” in the identification circuit,
The determination level of “0” does not need to be changed.

Next, a modulation index when a pseudo noise (PN) clock is subjected to FSK modulation according to the present invention will be described. Data rate of modulated data: fd (period Td = 1 / f
d), reference clock: fc, and fc = k · fd (k is a positive integer). If the frequency division ratio of the reference clock is N, the frequency of the 2N frequency-divided clock is fb = fc / 2 · N = k · fd / 2 · N

Here, N is an integer of N ≧ 2 and fb ≧ fd, so k is an integer of k ≧ 4. Frequency fh of the modulated pseudo noise (PN) clock when the modulation data is "1"
From FIG. 7F, one cycle of the 2N frequency-divided clock (1 / f
Since the reference clock is increased by one for each b), fh = (2 · N + 1) / (1 / fb) = [(2 · N +
1) / 2 · N] · fc. The frequency f _L of the modulated pseudo noise (PN) clock when the modulation data is “0” is 2N from FIG.
Since the reference clock is reduced by one clock every one cycle (1 / fb) of the divided clock, f _L = (2 · N−1) / (1 / fb) = [(2 · N−
1) / 2 · N] · fc. Therefore, since the modulation index m is obtained by multiplying the difference between the frequencies by the data period, m = (fh−f _L ) · Td = ｛(2 · N + 1) · fc / 2 · N− (2 · N-1) · fc / 2 · N｝ · Td = fc / (N · fd) Since fc = k · fd, m = k / N

Therefore, since the ratio k between the modulation data and the reference clock is a predetermined value, the modulation index can be changed as shown above by the division ratio N of the reference clock of the pseudo noise (PN) signal. You can see what you can do. However, 2 ≦ m ≦ k / 2 under the given conditions. In the embodiment described above, a PLL (Phase Locked Loop) is used. However, this PLL has a complicated and expensive circuit, and the calculation of circuit constants has been complicated.
An embodiment that improves this point will be described below.

FIG. 9 is a circuit diagram of a transmitter for explaining another embodiment of a digital modulation system in spread spectrum communication according to the present invention. In FIG.
42, 46 are 1/2 frequency dividers, 43, 49, 50, 51,
52 and 53 are inverters, 44 and 47 are D flip-flops, 45 is a 1 / N divider, 8, 54 to 59 are AND gate circuits, 60 is an OR gate circuit, 61 is a divider, 62
Is a pseudo noise (PN) signal generator, 63 is a frequency conversion circuit, and 64 is a power amplification circuit.

FIGS. 10A to 10H and FIG.
(A) to (h) are diagrams showing a signal waveform and a demodulated signal at the time of modulation. FIG. 10 shows a case where the modulation data is “1”, and FIG. 11 shows a case where the modulation data is “0”. Here, the frequency division ratio of the reference clock is N = 4. The output frequency of the crystal oscillator 41 is set to 2M times the clock frequency of the PN signal (FIG. 10 (d)).
c (FIG. 10E) is obtained. This reference clock fc is divided by the frequency divider 5 into 1 / N (FIG. 10B), and further divided by the 1/2 frequency divider 6 into fc / 2N (FIG. 10C). Next, the modulated data is synchronized with the clock fc / 2N obtained by dividing the frequency by the D flip-flop 7.

The signal when the modulation data is "1" will be described with reference to FIG. When the N-divided clock is “1” and the 2N-divided clock is “1”, a signal (A) obtained by delaying the reference clock by 負 cycle with a negative signal of the frequency clock 2fc which is twice the frequency is output. When the N-divided clock is “0” and the 2N-divided clock is “1”, the reference signal (B) is output.
When the N-divided clock is “1” and the 2N-divided clock is “0”, a negative signal (C) of the signal (A) is output. When the N-divided clock is “0” and the 2N-divided clock is “0”, a negative signal (D) of the reference signal is output. Therefore, while the modulation data is "1", the signals (A), (B), (C), and (D) are output in order for every half cycle of the N-divided clock (FIG. 10 (f)). Will be. With these operations, the number of clocks is increased by one clock for each period of the 2N frequency-divided clock, so that the frequency is correspondingly increased.

The signal when the modulation data is "0" will be described with reference to FIG. When the N-divided clock is “1” and the 2N-divided clock is “1”, a signal (A) obtained by delaying the reference clock by 負 cycle with a negative signal of the frequency clock 2fc which is twice the frequency is output. When the N-divided clock is “0” and the 2N-divided clock is “1”, a negative signal (D ′) of the reference signal is output. When the N-divided clock is “1” and the 2N-divided clock is “0”, a negative signal (C) of the signal (A) is output. When the N-divided clock is "0" and the 2N-divided clock is "0", the reference signal (B ') is output. Therefore, while the modulation data is "0", the signals (A), (D '), (C), and (B') are output in order every half cycle of the N-divided clock (FIG. 11 (f) )) By these operations, the number of clocks is reduced by one clock for each period of the 2N frequency-divided clock, so that the frequency is correspondingly reduced.

This signal is frequency-divided by M by a frequency divider 61, and this is used as a clock of a pseudo noise (PN) signal. Thereby, the rapid change of the phase is smoothed, and the phase is smoothly changed. This situation is shown in FIG. 10 (g) and FIG.
(G). By doing so, the period can be prevented from being shifted due to a sudden phase change on the receiver side. The average frequency during which the modulation data is "1" is fh (> fc),
Let the average frequency during “0” be f _L (<fc).

By the above operation, the clock frequency of the pseudo noise (PN) signal becomes fh when the modulation data is "1",
When it is “0”, it becomes f _L , and the frequency shift modulation (FS
K). Since this modulation signal is generated by a digital logic circuit, fh and f _L have very stable frequencies. Therefore, the pseudo noise (P
N) There is no danger that the clock frequency will exceed the tracking range of the delay lock loop (DLL). Further, according to this method, by changing the frequency division ratio N, the average frequencies fh and f _L can be changed, and therefore, the modulation index of FSK can be changed. Further, in the frequency modulation according to the present method, the same modulation is applied to the higher and lower frequencies around the reference signal frequency. Therefore, the receiving side adjusts the determination level for determining whether data is "1" or "0" at the time of demodulation to the center frequency,
Even if the modulation index is changed, accurate demodulation can be performed as it is.

Next, a pseudo noise (PN) clock (FIG. 10)
(G) and FIG. 11 (g)) as a clock of a pseudo noise (PN) signal generator to generate a pseudo noise (PN) signal. The signal is multiplied by a carrier frequency to perform frequency conversion, and the signal is amplified by a power amplifier circuit, and then a radio wave is output from an antenna. The circuit configuration diagram of the receiver in the above-described embodiment is the same as FIG.

Next, a modulation index when a pseudo noise (PN) clock is subjected to FSK modulation according to the present invention will be described. Data rate of modulated data: fd (period Td = 1 / f
d), reference clock: fc, and fc = k · fd (k is a positive integer). If the frequency division ratio of the reference clock is N, the frequency of the 2N frequency-divided clock is fb = fc / 2 · N = k · fd / 2 · N

Here, N is an integer of N ≧ 2 and fb ≧ fd, so k is an integer of k ≧ 4. The pseudo noise (PN) clock is obtained by dividing the reference clock by M.
The signal before the frequency division by M when the modulation data is "1" (FIG. 10)
In the frequency fh ′ of (f)), the reference clock is increased by one clock for each cycle (1 / fb) of the 2N frequency-divided clock, so that fh = (2 · N + 1) / (1 / fb) = [ (2 · N +
1) / 2 · N] · fc. Since the frequency is divided by M to obtain a pseudo noise (PN) clock, fh = [(2 · N + 1) / 2 · N · M] · fc. When the modulation data is “0”, the frequency f _L ′ of the signal before frequency division by M (FIG. 11F) is such that the reference clock is one clock every one cycle (1 / fb) of the 2N frequency-divided clock. F _L ′ = (2 · N−1) / (1 / fb) = [(2 · N−
1) / 2 · N] · fc. Similarly, since the frequency is divided by M to obtain the PN clock, f _L = [(2 · N−1) / 2 · N · M] · fc

Therefore, the modulation index m is obtained by multiplying the difference between the respective frequencies by the data period, so that m = (fh−f _L ) · Td = ｛(2 · N + 1) · fc / 2 · N・ M- (2 ・ N-1) ・ fc
/ 2 · N · MＴ · Td = fc / (N · M · fd) Since fc = k · fd, m = k / (N · M) Therefore, the ratio k between the modulation data and the reference clock is given in advance. It can be seen that the modulation index can be changed as in the above equation by the dividing ratio N of the reference clock of the pseudo noise (PN) signal. However, according to given conditions, 2 ≦ m ≦ k / 2.

In the embodiment described above, the logical circuit
The frequency of the signal output by the path is the frequency of the PN signal clock
For the same or was more and, it is necessary to operate the logic circuit at a high frequency in order to widen the spread bandwidth. Therefore, PN depends on the operating frequency of the logic circuit.
The clock frequency, ie the spreading band, was limited.
An embodiment that improves this point will be described below. FIG.
2 is a circuit diagram of a transmitter for explaining still another example of the digital modulation system in the spread spectrum communication according to the present invention. In FIG.
/ 2 frequency divider, 73, 78, 79, 80, 81, 82 are inverters, 74, 77 are D flip-flops, 75 is 1
/ N divider, 83 to 88 are AND gate circuits, 89 is O
R gate circuit, 90 is a phase comparator, 91 is a loop filter, 92 is a voltage controlled oscillator (VCO), 93 is a 1 / M frequency divider, 94 is a pseudo noise (PN) signal generator, 95 is a frequency conversion circuit, Reference numeral 96 denotes a power amplifier circuit.

FIGS. 13A to 13I and FIG.
(A) to (i) are diagrams showing a signal waveform and a demodulated signal at the time of modulation. FIG. 13 shows a case where the modulation data is “1”, and FIG. 14 shows a case where the modulation data is “0”. Here, the dividing ratio of the reference clock is N = 4 and M = 2. The center frequency of the reference signal input to the phase locked loop (PLL) generated by the logic circuit is 1 / M of the PN clock, and
It was used as a reference clock represented by fc. The output frequency of the crystal oscillator 71 is set to 2fc, which is twice the reference clock frequency fc (FIG. 13D), and the reference clock fc (FIG. 13E) is obtained by the 1/2 frequency divider 72. This fc is frequency-divided by a frequency divider to 1 / N (FIG. 13 (b)).
The frequency is divided into fc / 2N by the frequency divider 76 (FIG. 13C).
I do. Next, the modulation data is synchronized with the clock fc / 2N obtained by dividing the frequency by the D flip-flop 77.

The signal when the modulation data is "1" will be described with reference to FIG. When the N-divided clock is “1” and the 2N-divided clock is “1”, a signal (A) obtained by delaying the reference clock by 負 cycle with a negative signal of the frequency clock 2fc which is twice the frequency is output. When the N-divided clock is “0” and the 2N-divided clock is “1”, the reference signal (B) is output.
When the N-divided clock is “1” and the 2N-divided clock is “0”, a negative signal (C) of the signal (A) is output. When the N-divided clock is “0” and the 2N-divided clock is “0”, a negative signal (D) of the reference signal is output. Therefore, while the data is "1" in the modulation, the signals (A), (B), (C), and (D) are output in order for every half cycle of the N-divided clock (FIG. 13 (f)). ) These operations increase the number of clocks for each cycle of the 2N frequency-divided clock, thereby increasing the frequency accordingly.

A signal when the modulation data is "0" will be described with reference to FIG. When the N-divided clock is “1” and the 2N-divided clock is “1”, a signal (A) obtained by delaying the reference clock by 負 cycle with a negative signal of the frequency clock 2fc which is twice the frequency is output. When the N-divided clock is “0” and the 2N-divided clock is “1”, a negative signal (D ′) of the reference signal is output. When the N-divided clock is “1” and the 2N-divided clock is “0”, a negative signal (C) of the signal (A) is output. When the N-divided clock is "0" and the 2N-divided clock is "0", a negative signal (B ') of the reference signal is output.
Therefore, while the data is "0" in the modulation, the signals (A), (D '), (C),
(B ') are output in order (FIG. 14 (f)). By these operations, the number of 1N clocks is reduced for each cycle of the 2N frequency-divided clock, so that the frequency is correspondingly reduced.

This signal is converted to a phase comparator, a loop filter,
A phase-locked loop (P) composed of a voltage controlled oscillator (VCO)
LL) . Voltage controlled oscillator (VO
The output of C) is input to a PN signal generator , and 1 /
The frequency is divided by the M frequency divider and the comparison signal of the PLL is input (FIG. 13)
(G) and FIG. 14 (g)). Therefore, the reference signal input generated by the logic circuit is 1 / M of the PN signal clock.
Frequency. This can prevent loss of synchronization due to a sudden phase change. The average frequency during which the modulation data is "1" is fh (> fc), "0"
Let f _L (<fc) be the average frequency between.

The clock frequency of the PN signal by the above operations, fh when the modulation data is "1", "0" f L next time of, FPN the center frequency of the PN signal clock (M ·
fc) and frequency shift modulation (FSK). Next, the output clock from the PLL (FIG. 13 (h), FIG. 14)
(H)) as the clock of the PN signal generator
Generate a signal. The signal is multiplied by a carrier frequency to perform frequency conversion, and the signal is amplified by a power amplifier circuit, and then a radio wave is output from an antenna. The circuit configuration diagram of the receiver in the above-described embodiment is the same as FIG.

Next, a modulation index when a pseudo noise (PN) clock is subjected to FSK modulation according to the present invention will be described. Data rate of modulated data: fd (period Td = 1 / f
d), reference clock: fc, and fc = k · fd (k is a positive integer). If the frequency division ratio of the reference clock is N, the frequency of the 2N frequency-divided clock is fb = fc / 2 · N = k · fd / 2 · N

Here, N is an integer of N ≧ 2 and fb ≧ fd, so k is an integer of k ≧ 4. Further, the frequency division ratio of the output of the phase locked loop (PLL) is set to M (≧ 2). The frequency fh of the modulated pseudo noise (PN) clock when the modulation data is "1" is such that the reference clock is increased by one clock every one cycle (1 / fb) of the 2N frequency-divided clock from FIG. Fh = M · (2 · N + 1) / (1 / fb) = [(2 · N + 1)
/ 2 · N] · M · fc. The frequency f _L of the modulated pseudo noise (PN) clock when the modulation data is “0” is 2 from FIG.
Since the reference clock is reduced by one clock every one cycle (1 / fb) of the N-divided clock and becomes M times larger, fL = M _L (2 ・ N-1) / (1 / fb) = [(2 · N-1) /
2 · N] · M · fc. Therefore, the modulation index m can be obtained by multiplying the difference between the respective frequencies by the data period, so that m = (fh−f _L ) · Td = ｛(2 · N + 1) · M · fc / 2 · N− ( 2 · N−1) · M · fc / 2 · N｝ · Td = M · fc / (N · fd) Since fc = k · fd, m = M · k / N

Therefore, since the ratio k between the modulation data and the reference clock is a predetermined value, it is possible to change the modulation index as shown in the above equation by the division ratio N of the reference clock of the pseudo noise (PN) signal. You can see what you can do.
However, according to given conditions, 4 ≦ m ≦ M · k / 2.

[0048]

As apparent from the above description, the present invention has the following effects. (1) In the spread spectrum communication apparatus according to the present invention, a phase locked loop (PLL) that supplies a clock by a digital logic circuit to a reference frequency is used, so that the frequency modulation output of the pseudo noise (PN) clock is set to a sufficiently stable frequency. can do. As a result, the receiver does not lose synchronization beyond the delay lock loop (DLL) tracking range, and digital data transmission can be reliably performed. (2) A signal having a higher frequency than a pseudo-noise (PN) clock is used as a reference clock, and by dividing the frequency, a phase shift can be smoothed in the same manner. ) No circuit is required. (3) Since frequency modulation is performed symmetrically around the center frequency, when the modulation index is changed, it is not necessary to change the determination level of “1” or “0” when demodulating on the receiving side. (4) By dividing the frequency of the PN signal clock and applying PLL with the frequency of the signal output by the logic circuit,
The PN clock frequency can be increased without operating the logic circuit at a high frequency, that is, the spreading band can be widened.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a transmitter for explaining an embodiment of a digital modulation method in spread spectrum communication according to the present invention.

FIG. 2 is a diagram illustrating a signal waveform at the time of modulation and a state of a demodulated signal.

FIG. 3 is a circuit configuration diagram of a receiver for explaining one embodiment of a digital modulation method in spread spectrum communication according to the present invention.

FIG. 4 is a diagram showing another embodiment of a digital modulation system in spread spectrum communication according to the present invention.

FIG. 5 is a diagram showing a signal waveform at the time of modulation and a state of a demodulated signal in FIG. 4;

FIG. 6 is a diagram showing still another embodiment of a digital modulation system in spread spectrum communication according to the present invention.

FIG. 7 is a diagram showing a signal waveform after modulation and a state of a demodulated signal in FIG. 6;

8 is a diagram showing a state of a signal waveform after modulation and a demodulated signal in FIG. 6;

FIG. 9 is a circuit diagram of a transmitter for explaining another embodiment of the digital modulation system in the spread spectrum path according to the present invention.

FIG. 10 is a diagram showing a signal waveform and a demodulated signal at the time of modulation when the modulation data is “1”.

FIG. 11 is a diagram showing a signal waveform and a demodulated signal at the time of modulation when the modulation data is “0”.

FIG. 12 is a circuit diagram of a transmitter for explaining still another example of a digital modulation method in spread spectrum communication according to the present invention.

FIG. 13 is a diagram showing a signal waveform and a demodulated signal at the time of modulation when the modulation data is “1”.

FIG. 14 is a diagram showing a signal waveform and a demodulated signal at the time of modulation when the modulation data is “0”.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Crystal oscillator, 2 ... Divider, 3 ... D flip-flop, 4, 7, 8 ... AND gate circuit, 5, 6 ... Inverter, 9 ... OR gate circuit, 10 ... Phase comparator, 11 ... Loop filter, 12 ... voltage controlled oscillator (VCO), 13 ...
Phase locked loop (PLL), 14 ... Pseudo noise (PN) signal generator, 15 ... Frequency conversion circuit, 16 ... Power amplification circuit.

Claims (5)

(57) [Claims] 1. A digital more spread spectrum communication method according to clock speed modulation, for transmitting digital signals
In the modulation method, a predetermined reference clock signal or a frequency divider from the reference clock signal is used in accordance with modulation data.
A signal from which the number of clocks corresponding to the frequency division ratio N ( an integer of 2 or more) of the set reference clock is removed is output, and the signal is input as a reference signal of a phase locked loop (PLL) to perform phase synchronization ; A digital modulation method wherein frequency modulation is performed by using an output signal of the phase locked loop (PLL) as a clock of a pseudo noise (PN) generator . 2. A digital more spread spectrum communication method according to clock speed modulation, for transmitting digital signals
In the modulation method, a predetermined reference clock signal or a frequency divider from the reference clock signal is used in accordance with modulation data.
A signal from which the number of clocks corresponding to the division ratio N ( an integer of 2 or more) of the set reference clock has been removed is output, the signal is frequency- divided to the frequency of a pseudo noise (PN) clock, and the frequency division is performed.
The generated signal as a clock for a pseudo-noise (PN) generator
Digital modulation system, characterized in that applying a frequency modulation in. 3. A digital more spread spectrum communication method according to clock speed modulation, for transmitting digital signals
In the modulation method, a predetermined reference clock signal or a frequency divider from the reference clock signal is used in accordance with modulation data.
A signal obtained by removing or adding the number of clocks according to the set dividing ratio N ( an integer of 2 or more) of the reference clock is output, and the signal is used as a reference signal of a phase locked loop (PLL).
Multiplied by the phase synchronization by entering Te, the phase-locked loop (PL
L) is output from a pseudo noise (PN) generator clock .
A digital modulation method characterized by applying frequency modulation by performing 4. A digital more spread spectrum communication method according to clock speed modulation, for transmitting digital signals
In the modulation method, a predetermined reference clock signal or a frequency divider from the reference clock signal is used in accordance with modulation data.
A signal obtained by removing or adding the number of clocks corresponding to the frequency division ratio N ( an integer of 2 or more) of the set reference clock is output, and the signal is frequency- divided to the frequency of a pseudo noise (PN) clock. digital modulation method in the spread spectrum communication, characterized by applying a frequency modulation to a signal by a black <br/> click pseudo-noise (PN) generator. 5. More spread spectrum communication system according to clock speed modulation, and transmits the digital signal digital
In the modulation method , pseudo noise (P
N) A reference clock signal having a frequency obtained by dividing the clock by M (an integer of 2 or more), and a signal obtained by removing or adding the number of clocks from the reference clock signal according to the frequency division ratio of the reference clock (an integer of 2 or more). And outputs the signal as a reference signal of a phase locked loop (PLL).
A signal obtained by dividing the output signal of L) by M is input as a comparison signal of the phase locked loop (PLL) to perform phase synchronization ,
The output of the phase locked loop (PLL) is converted to pseudo noise (PN).
A digital modulation method in which frequency modulation is performed by using the clock of a generator .