JPS60246445A - Microcomputer - Google Patents

Abstract

PURPOSE:To improve an internal monitoring capacity of a microcomputer by outputting a data on an internal bus line on which internal information is concentrated, from an output terminal by a regular output and a time division. CONSTITUTION:A test instruction code 11 in an instruction register 10 is decoded by an instruction decoder 14 and sent to an output mode register 17. It determines an internal bus line data time division output mode. A multiplexer 23 inputs the test instruction code 11 from the output mode register 17, an immediate data 12 from the instruction register 10, a data of a bus line 18, and a clock signal group 13, and selects one from in the clock group. The data of the bus line 18, and an output of an output latching circuit 20 are outputted by a time division, when a clock signal is on, and when it is of, respectively, amplified by an output buffer 24, and outputted from an output terminal 25.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a microcomputer, particularly a Vcl chip microcomputer KrJAf.

(Prior Art) Conventionally, it is often necessary to monitor the internal state of a microcomputer, but monitoring the internal state requires a great deal of effort.

FIG. 1 is a block diagram of a circuit portion near an output terminal of an example of a conventional microcomputer.

The output data signal 1 is taken into an output latch circuit 2 as a take-in signal 3, latched, and output as a sweep signal 4, amplified by an output buffer 5, and outputted from an output terminal 6.

With such a circuit configuration, only the value of a single type of signal (ie, output data signal 1) can be output from the output terminal 6. Moreover, the take-in signal 3 taken into the output latch circuit 2
Since is determined by the internal clock signal, changes in the output data signal 1 while the acquisition signal 3 is not turned on are not seen at the output terminal 6. As described above, microcomputers with conventional configurations often have the disadvantage that it is difficult to sufficiently monitor the data on the path lines in which various internal data are accumulated.

(Object of the Invention) An object of the present invention is to eliminate the above-mentioned drawbacks, to make it possible to output data on the internal path line where internal information is concentrated from the output terminal in a time-sharing manner with the normal output, and to have the ability to monitor the internal state. The Microconbeater T- has a lot to offer.

(Structure of the Invention) The -r microcomputer of the present invention includes an instruction register having a part for storing test instruction codes and a part for storing immediate data, an instruction decoder for decoding the test instruction codes, and internal pass line data. an output mode register for determining a time division output mode and temporarily storing the decoded test instruction code;
an output latch circuit that inputs and temporarily stores an output data signal, an internal clock signal group, immediate data output from the instrafsilon register, a test instruction code output from the output mode register, and an output from the output latch circuit. input the output data and the data of the pass line, select one clock 1K 4ir t-'S from the internal clock signal group, and input the data of the pass line only during the period when the selected one clock signal is on.
The selection off period includes an i multiplexer that selects and time-divisionally outputs the output data of the output latch circuit.

(Example) Next, embodiments of the present invention will be described using the drawings.

FIG. 2 is a block diagram of one embodiment of the present invention.

This embodiment includes an infrastructural register 10 that combines a part for storing test instruction codes and a part for storing immediate data, an instruction decoder 14 for decoding test instruction codes 11, and an internal pass line data time division output mode. an output mode register 17 that temporarily stores all determined and decoded test instruction codes; an output latch circuit 20 that inputs and temporarily stores the output data signal 19;
Internal clock signal group 13, immediate data 12 output from instruction register IO, and test instruction code 11 output from output mode register 17
, the output data output from the output latch circuit 20 and the data of the pass line 18 are input, and the internal clock signal group 13 is
a multiplexer 23 that selects one clock signal from the list, selects the data of the pass line 18 only while the selected clock signal is on, and selects the output data of the output latch circuit 20 during the off period, and outputs the data in a time-division manner; It consists of:

Next, the operation of this embodiment will be explained.

Test instruction code 11 stored in instruction register 10 is decoded by instruction decoder 14 and sent to output mode register 17.

The output mode register 14 is a register that determines the internal bus line data time-division output mode, and the stored contents can be reset by a reset signal 16.

The multiplexer 23 receives the test instruction code 11. which is output from the output mode register 17. Immediate data 12 sent from the infrastructural register 1o. The data l' of the pass line 18 is inputted with the internal lock signal group 13, and one clock signal is selected from the internal clock signal group 13.

Data on the pass line 18 is selected only while the selected clock signal is on, and output data from the output latch circuit 20 is selected during the off period, and is output in a time-division manner.

The output is amplified by an output buffer 24 and output from an output terminal 25 in a time-division manner.

With this configuration, read-only memory (ROM),
Temporary memory memo! A path line 18 where various internal data such as address data and memory data of TtAM, and input/output data of the logic processing unit (ALU) are accumulated.
data can be monitored at each timing of the internal clock signal, improving the ability to monitor internal states.

In the above embodiment, the output terminal 25 is shown to be dedicated, but it may also be used for both input and output purposes. Also, the multiplexer can be displayed as one, or two multiplexers can be used to share the functions.

(Effects of the Invention) As explained in detail above, according to the present invention, the ability to monitor internal conditions is improved, the rate of finding defective products in the product inspection process is increased, and products of excellent quality are produced. A microcomputer can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a circuit near the output gate of a conventional microcomputer, and FIG. 2 is a block diagram of an embodiment of the present invention. l...Output data signal, 2...Output latch circuit, 3...Intake signal, 4...
Sweeping signal, 5... Output buffer, 6...
...Output terminal, 10...Instruction date register, 11...Test instruction code, 12...
...Immediate data, 13...Internal clock signal group, 14...Instruction decoder, 16
...Reset signal, 17...Output mode register, 18...Pass line, 19...
...Output data signal, 20...Output latch circuit, 21...Take-in signal, 22...Sweeping signal, 23...Multiplexer, 24...
...output buffer, 25...output terminal.

Claims (1)

[Claims] an instruction register having a part for storing a test instruction code and a part for storing immediate data; an instruction decoder for decoding the test instruction code; and an instruction decoder for determining an internal pass line data time division output mode and for determining the decoded test instruction. An output mode register that temporarily stores code, an output latch circuit that inputs and temporarily stores an output data signal, a group of internal clock signals, immediate data output from the instruction register, and a test instruction output from the output mode register. The output data output from the hood and the output latch circuit and the pass line data are input, one clock signal is selected from the internal clock signal group, and the pass line is activated only during the period when the selected one clock signal is on. The off period includes a multiplexer that selects the output data of the output latch circuit and outputs it in a time-division manner.
- A microcomputer with a percentage value.