JPH0767083B2 - Pulse counting method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] According to the present invention, when a count value of a pulse counter that counts pulses is periodically read and processed, a register that stores overflow of a counter that operates in an endless system is provided and processed. By reading the output of the pulse counter and the output of the register and resetting the register in response to a read command from the device, even if there is a periodic interruption of reading due to a failure of the processing device, an incorrect count is given when the operation of the processing device is restarted. It prevents reading the value.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse counting method in a device that counts pulse outputs from a sensor or a device that detects various variables and performs processing such as measurement and control.

[Prior Art] In a device that counts and processes the pulse output from various equipment such as sensors, even if the processing device becomes incapable of processing due to a power failure or the like, continue to count the pulse input. Is often required.

In this case, conventionally, a method has been generally adopted in which only the pulse counter is powered by a battery, pulses are counted, and the processor reads the value of the counter when power is restored.

FIG. 3 shows a block configuration of a conventional pulse counting method and an operation explanatory diagram.

In (1) and (4) of FIG. 3, 30 is a pulse counter, 31 is a processor, 32 is a gate circuit, 33 is a read signal,
Reference numeral 34 represents an output line (bus) for the count value of the pulse counter.

As a conventional pulse counting method, there are a read reset method shown in (1) and an endless method shown in (4) of FIG.

As shown in (2) and (3) of FIG. 3, the read reset method opens the gate circuit 32 each time a read signal 33 from the processing device 31 is generated, and outputs the count value output line 34 of the pulse counter 30. The pulse counter 30 is reset when the signal is input to the processing device 31 and the read signal 33 is also applied to the reset terminal R.

In the endless system, as shown in (5) and (6) of FIG. 3, the gate circuit 32 opens every time the read signal 33 from the processing device 31 is generated, and the output line of the count value of the pulse counter 30 is output. The point that the operation of supplying the signal of 34 to the processing device 31 is performed is the same as the above read reset method, but the pulse counter 30 does not reset at the time of reading and continues counting as it is, and when it overflows beyond the maximum count value. It returns to "0".

[Problems to be Solved by the Invention] Among the conventional methods, the read reset method resets the pulse counter each time the processing device reads, so
There is an advantage that the count value from one reading to the next reading can be read directly, but if an abnormal state such as a power failure occurs in the processing unit while reading the count value, the processing unit is not reading. There was a drawback that only the counter was reset.

In addition, the endless method has a problem that when the processor stops due to a power failure or the like and only the counter operates and the counter reaches a value of one cycle or more and then the power is restored, the value for one cycle cannot be read. Has become. For example, with a pulse counter that counts 8 bits = 256, if more than 256 pulses are input during a power failure, even if the output of this counter is read when the power is restored, it cannot be determined whether or not one cycle has been completed. It's a problem.

[Means for Solving Problems] In order to solve the above problems, the present invention provides a register for storing overflow of a counter operating in an endless system, and outputs a pulse counter by a read signal from a processing device. By reading out the output of the register and resetting the register, even if there is a periodic interruption of the reading due to the occurrence of a failure in the processing device, an incorrect reading of the count value is prevented when the operation of the processing device is restarted.

The principle structure of the present invention is shown in FIG.

In FIG. 1, 10 is a pulse counter, 11 is a register,
12, 13 are gate circuits, 14 is a processor, 15 is an output line of the pulse counter, 16 is an overflow output line of the pulse counter, 17 is an output line of the register 11, and 18 is a read signal line.

[Operation] The pulse counter 10 receives a pulse input and performs a counting operation. When an overflow occurs, the pulse counter 10 is supplied to the register 11 from the output line 16 and counts and stores it.

The processing device 14 generates a read signal generated on the read signal line 18 at a constant period shorter than the time required to count the pulse input of the pulse counter 10 and count the maximum count value, and outputs the read signal to the gate circuits 12, 13 Drive and open the gate. As a result, the outputs of the pulse counter 10 and the register 11 are input to the processing device, and the processing is performed in the processing device.

Further, in parallel with this read operation, the register 11 receives the read signal at the reset terminal and is reset. Actually, the register is reset immediately after the gate circuit 12 is opened and the signal on the output line 17 is output.

[Embodiment] The configuration of an embodiment of the present invention is shown in FIG.

In FIG. 2 (a), 20 is a pulse counter, 21 and 22 are registers for counting and holding overflow signals, and 23 and 2
4 is a gate circuit, 25 is a processing unit (CPU), 26 is a memory, 27 is a logic circuit, and 28 is a read signal line.

The operation of this embodiment will be described with reference to the operation explanatory diagram of FIG.

The cycle of the read signal generated from the processing unit (CPU) 25 on the read signal line 28 is shorter than the time required for the pulse counter 20 to count the pulse input and count the maximum count value.

The pulse counter 20 is an n-bit endless counter, and when the maximum count value of all "1" is reached,
When the next pulse is input, all are automatically set to "0" and an overflow signal is generated at the same time.

The operation will be described below.

First, in the case of (a) of FIG. 2 (b), the pulse counter 20
Is read twice before the overflow occurs, the first reading reads the value "m" and the next reading the value "n". Since the processing unit 25 holds the value (m) read last time in the memory 26, the value (m) is subtracted (nm) from the value (n) read this time, and the number of pulses up to You can know.

Next, in the case of (b) in FIG. 2 (b), the pulse counter
20 is a case where an overflow occurs once after the first reading and then the processing unit 25 issues a reading signal.
When this overflow occurs, the flag Q2 of the register 22 is off (0 output). Therefore, an overflow signal is passed through the logic circuit 27 to the register 21 to set it, and the flag Q1 is turned on (1 output). To When reading is done in this state, the value n is read and at the same time the register is
21 is reset and flag Q1 is off.

In this case, the processing unit 25 can know the pulse count value by the following calculation. However, L is the maximum value of the pulse counter 20.

When m> n Number of pulses = L− (m−n) When m ≦ n Number of pulses = L + (n−m) Next, as shown in (c) of FIG. After the power failure occurs in the processing unit 25 and then the power is restored and the reading is performed, the overflow 2
If it occurs more than once, the register 22 is set by the second overflow. When the register 22 is set, its output is supplied to the logic circuit 27 as a prohibition input as shown in FIG. 2, and thereafter, even if an overflow signal is generated, it is not input to the register 21. In this case, the processing unit 25 detects that the flag Q2 of the register 22 is on, and determines that the read count value at that time is unusable (untrustworthy) and processes it.

[Effects of the Invention] As described above, even if a failure such as a power failure occurs in the processing unit after the previous reading, the overflow of the pulse counter 20 is 1
If the next reading is performed within the period in which the count has occurred twice, the correct count value can be known, and even if the overflow occurs twice or more, the count value at that time may be incorrect due to the output of the register. Is displayed.

Further, according to the present invention, it is possible to realize overflow detection and reading with a relatively simple configuration, taking advantage of the advantages of the endless method.

[Brief description of drawings]

FIG. 1 is a diagram showing a principle configuration of the present invention, FIG. 2 (a) is a diagram showing a configuration of an embodiment of the present invention, FIG. 2 (b) is an operation explanatory diagram of the embodiment, and FIG. It is a structure and operation explanatory drawing of a prior art example. In FIG. 1, 10: pulse counter 11: register 12, 13: gate circuit 14: processor 15: pulse counter output line 16: overflow output line 17: register 11 output line 18: read signal line

Claims (1)

[Claims] 1. A pulse counting system for periodically reading a counter value of pulse output by a processing device for processing, counting the pulse output, generating an overflow output next to the maximum count value, and resetting. An endless type pulse counter (10) and an overflow output of the pulse counter are inputted through a logic circuit, and the memory stores whether or not the number of occurrences of overflow output is one or more times, and a read signal from the processing device. The two-stage register (11) provided corresponding to the number of overflows reset by (18) and the other input of the logic circuit are supplied with the second-stage output of the register as a prohibited input. The count state output of the pulse counter and the state output of the register count the maximum count value of the pulse counter. The processing device (14) is provided with a gate circuit (12, 13) for outputting to a bus connected to the processing device in response to a read signal from the processing device (14) generated in a cycle shorter than the time, and the processing device outputs the status output of the read register. When the pulse count number is discriminated based on the previous and present count state outputs of the pulse counter, and reading is performed after the reading is interrupted due to a power failure or the like of the processing apparatus and the failure is recovered, the processing apparatus , The status output of the register is discriminated. If the second stage register is not set, the normal pulse count number is discriminated, and if it is set, the read counter value is not used. A pulse counting method characterized in that