JPS60242658A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a reference voltage generator, a temperature change thereof is small, by forming reference voltage on the basis of the threshold voltage difference of an IGFET having a threshold voltage difference corresponding to the Fermi level difference of a gate electrode and controlling a bias voltage generating circuit by an output signal from a voltage comparison circuit. CONSTITUTION:Two IGFETs having silicon-gate electrodes having different conduction types are formed in an silicon-monolithic semiconductor integrated circuit chip. Since these FETs are manufactured under approximately the same conditions with the exception of the conduction types of the gate electrodes, a difference between both Vth is approximately equial to differences among the Fermi levels of P type silicon, N type silicon and I type (an intrinsic semiconductor) silicon. Each impurity is doped to sections close to saturation concentration in the P type and N type gate electrdes, a difference between the saturation concentration is made approximately the same as the energe-gap Eg (approximately 1.1V) or Eg/2 (0.55V) of silicon, and the difference is utilized as a reference voltage source. A reference voltage generator based on such constitution can be used as the reference voltage generator for various electronic circuits because it has small temperature dependence and also a small deviation on manufacture.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to electronic devices, particularly to reference voltage generators and their applications, as well as insulated gate field effect transistors and methods of manufacturing the same.

In various semiconductor electronic circuits, in order to generate a reference voltage, it is essential to use a physical quantity having the dimension of voltage. Until now, the physical quantities have mainly been the forward voltage drop of a PN junction diode (■), the reverse breakdown voltage (Zena voltage) (2), and the threshold of an insulated gate field effect transistor (often represented by IGFET1MO8FET). Value voltage Vth etc. are used.

These physical quantities do not indicate absolute voltage values, and the voltage values are subject to fluctuations depending on various factors. Therefore, in order to utilize these physical quantities as a reference voltage generating device for various electronic circuits, K must pay attention to the fluctuation factors of the obtained voltage value and the permissible fluctuation range.

First, regarding the temperature characteristics of these physical quantities,
and Vth usually have a temperature dependence of about 2 to 3 mV/C, and the temperature change in the reference voltage that accompanies this temperature change trap is so large that it may be necessary to give up on practical use depending on the application.

For example, if you want to create a battery checker for an electronic watch that uses a nominal 1.5V silver oxide battery to warn that the battery voltage has dropped,
It is necessary to judge whether the battery voltage is high or low, with the boundary (detection level) at about 1.4V.

This is the MOSFET threshold voltage vt of about 0.6V.
Or, if you try to configure it using the diode's forward drop voltage (2), the detection level with a target of 1.4V has a temperature dependence of = 4.67 to 7.0 (mV/C). , Practical operating temperature range oc~50C
Even if we narrowly estimate "C", it will fluctuate greatly by 1.23V to 1.57V, so it cannot be used as a practical battery checker.

Next, regarding manufacturing variations in these physical quantities, MO8
FET17) The threshold voltage Vth has a variation of about ±0.2 V, and this variation is larger than the temperature change. Therefore, use the battery checker mentioned above. When making an IC (integrated circuit) using this, not only external parts and connection pins (terminals) for correcting the reference voltage are required, but also the effort of adjustment after the ICff is manufactured is required.

Also, in MO8FET integrated circuits such as semiconductor RAM,
Substrate (back gate) (by applying reverse bias voltage,
If you want to control the threshold voltage of a FET, you need a reference voltage source that is independent of temperature dependence and manufacturing variations, and it also needs to be possible to integrate it. Difficult to hire for a number of reasons. Also,
Zener voltage v2 is limited to about 3V at low voltage,
It is unsuitable as a reference voltage to be used in a low voltage range of 3V or less, and a voltage of several mA to several tens of m
It is necessary to flow a current of about A, which is inappropriate in terms of reducing power consumption.

As is clear from the above explanation, conventional reference voltage generators using Vth, v, and vz are not necessarily suitable for all uses, considering temperature characteristics, manufacturing variations, power consumption, voltage levels, etc. In many cases, practical application and mass production had to be abandoned for applications requiring extremely strict characteristics.

From the above studies, the present inventors learned that there are physical limits to the improvement of conventional reference voltage generators, and decided to research and develop a reference voltage generator with new ideas and ideas.

As for the reference voltage generator, for example,
The one shown in Japanese Patent No.-63257 is publicly known.

An object of the present invention is to provide a reference voltage generation circuit based on a completely new idea not seen in the past, and to facilitate the design and mass production of electronic circuits.

Another object of the present invention is to provide a reference voltage generator with small temperature changes.

Another object of the present invention is to ensure that fluctuations in voltage values obtained are small compared to fluctuations in manufacturing conditions, such as manufacturing variations between lots (
It is an object of the present invention to provide a reference voltage generating device with a small deviation).

Another object of the present invention is to provide an integrated circuit reference voltage generating device that can reduce manufacturing variations to such an extent that post-manufacturing adjustments are unnecessary.

Another object of the present invention is to provide an integrated electronic circuit device including a reference voltage generating device that can be manufactured with a large margin of tolerance to target specifications.

Another object of the present invention is to provide an integrated electronic circuit device including a reference voltage generator with high manufacturing yield.

Another object of the present invention is to provide a reference voltage generator suitable for IGFET integrated circuits.

Still another object of the present invention is to provide a reference voltage generator and a voltage comparator that consume less power.

Another object of the present invention is to provide a reference voltage generator capable of obtaining a low voltage (1.1 V or less) with excellent accuracy.

Another object of the present invention is to provide a reference voltage generator that is compatible with relatively low voltage (approximately 1 to 3 V) power sources, such as 1.5 V silver oxide batteries and 1.3 V mercury batteries. .

Another object of the present invention is to provide a reference voltage generator suitable for semiconductor integrated circuits.

Another object of the present invention is to provide a highly accurate voltage comparator, stabilized power supply device, constant current circuit, and battery a checker.

Another object of the present invention is to provide a semiconductor integrated circuit device for an electronic watch that has a built-in highly accurate battery checker and has a small number of external terminals.

Another object of the present invention is to provide a back-biased IG
An object of the present invention is to provide an IGFET integrated circuit in which the threshold voltage of an FET can be maintained at a substantially constant voltage independent of manufacturing variations and temperature changes, thereby improving manufacturing yield.

Another object of the present invention is to manufacture complementary insulated gate field effect transistor integrated circuits (0MO8IC) and N-channel MO8I
It is an object of the present invention to provide a reference voltage generator compatible with C- and P-channel MO8ICs, and a method for manufacturing the same.

The present invention returns to the origin of the physical properties of semiconductors and metals, and in particular, the energy gap Eg, work function φ, Fermi level E
It was created with a focus on Cape F.

That is, it is well known that semiconductors have an energy gear of 2p, but the physical properties of these semiconductors, especially energy, -
・A reference voltage generator that focuses on the gap Eg and the Fermi level E has never been seen before, having made remarkable progress in a wide range of fields since the discovery of semiconductors.

In terms of results, the present inventors determined the energy gap E, the work function φ, and the Fermi level E.

We thought of using Gin as a reference voltage source, and succeeded in realizing it. Using energy gap E, Fermi level E, etc. as a reference voltage source is not a difficult theory in itself, and the results are easy to understand and accept. However, in the field of semiconductor industry, which is no longer a short history, this success story, which is believed to be unprecedented and unprecedented by the present inventors, is original and groundbreaking, as we have returned to the origins of semiconductor physical properties. It is expected that it will make a significant contribution to the further development of the electronic circuit and semiconductor industries in the future.

According to one embodiment of the present invention, two IGFETs with different silicon-gate electrode conductivity groups are fabricated within a silicon monolithic semiconductor integrated circuit chip. These FETs
are manufactured under almost the same conditions except for the conductivity of the gate electrode, so the difference in vth between the two is equal to the difference in Fermi level of PIF-type silicon, N-type silicon, and i-type (intrinsic semiconductor) silicon. . The P-type and N-type gate electrodes are doped with respective impurities near the saturation concentration, and this difference is determined by the silicon energy gap Egl11. IV) or E,/2 (0,55■), which is used as a reference voltage source.

A reference voltage generating device based on such a configuration has low temperature dependence and small manufacturing deviation, so it can be used as a reference voltage generating device for various electronic circuits.

The present invention and further objects thereof will be more clearly understood from the following description with reference to the drawings.

Numerous documents explain the physical properties of semiconductors, starting from the crystal structure of semiconductors and expanding to the energy bands of semiconductors and the phenomena caused by donor and acceptor impurities in semiconductors.

It goes without saying that semiconductors with different compositions each have a unique energy gap Eg, and that the energy gap Eg expressed in eV has the dimension of voltage. However, as mentioned above, there has never been an example in which a semiconductor has a unique energy gap Eg and this temperature dependence is small, and this is used as a reference voltage source.

Since this embodiment was developed starting from the basics of semiconductor physical properties, a detailed explanation of the present invention will first start from the fundamentals of the present invention with reference to the physical properties of semiconductors. The physical properties of semiconductors are explained in detail in many documents.
Sem1conductorDevices”, 19
Published by John Wiley & 5ons in 1969 1 Especially Chapter 2 “Physics and Pr.
operations of Sem1 conductors
-A Resume” 11j [to be briefly explained with the help of page 65.

There are various compositions of applied semiconductors for the energy gap Eg, among which the representative semiconductors currently used industrially are non-compound semiconductors such as germanium (Ge) and silicon (Si), and gallium and silicon (Si). It is an arsenic (GaAs) compound semiconductor. The relationship between these energy ψ gaps Eg and temperature is explained on page 24 of the aforementioned book, and this is
Reprinted in Figure a As can be understood from Figure 1, 51C, Ge*Si and G
The Eg of a A s is at room temperature (300°K), respectively.
0.80 (eV), 1.12 (eV) and 1.43 (
eV). Moreover, its temperature dependence is o,
a9 (meV/'K), 0.24 (meV/'K
) and 0.43 (men/@K). Therefore,
By extracting a voltage corresponding to or close to these energy gaps Eg, the above-mentioned P
A reference voltage generator can be obtained that has a temperature dependence that is one order of magnitude smaller than the temperature dependence of the forward voltage drop 5 of an N-junction diode or the threshold voltage Vth of an IGFET. moreover,
The voltage obtained is the energy specific to the semiconductor, −・Gap E
For example, in the case of Sl, it is determined as approximately 1.12 (V) at room temperature, almost independently of other factors, and it is possible to obtain a reference voltage that is not easily influenced by variations in manufacturing conditions.

Now, an example will be explained based on which principle the voltage corresponding to the energy gap Eg of this semiconductor can be extracted.

Application of the difference in (work a) The energy unit state when a semiconductor is doped with donor and acceptor impurities is well known. What we particularly focused on in the present invention is that the Fermi energies of Nff1 and P-type semiconductor 10 are located at 2 points toward the conduction band and valence band, respectively, based on the Fermi energy level 'Ei of the intrinsic semiconductor. It is a physical property of being separated. As the concentration of acceptor and donor impurities increases, the Fermi level EfP of the P-type semiconductor tends to be further away from the Fermi level B1Th of the intrinsic semiconductor, and the Fermi level EfP of the P-type semiconductor approaches the uppermost level Ev of the valence band, and the N
The 7-luminium level Efn of an adult conductor is the lowest level E of the conduction band.
As cK approaches, if we take the difference between both 7 Hermi levels (Efn - Efp), this is the energy gap Eg of the semiconductor.
, and its temperature dependence also becomes close to that of the energy gap Eg. The same is true for the difference (Efn-5E1) and (Ei-Efp) in 7 lumi units between a P-type semiconductor and an intrinsic semiconductor, and between an N-type semiconductor and an intrinsic semiconductor, but in this case, the absolute value is E g/2 approach. The explanation of the difference with the intrinsic semiconductor will be omitted here, as it is the same as the difference between PW and N type. The details will be described later, but the higher the impurity concentration (Efn-Ef,
) has a small temperature dependence, and it is preferable to make the concentration as close as possible to the saturation concentration.

The Fermi level Efn, "fp is related not only to the concentration of donor and acceptor impurities, but also to the donor and acceptor levels Ed and E, which levels Ed, E,
varies depending on the impurity material. The closer the levels Id, E, and L are to the conduction band and the valence electron WVC, respectively, the closer the Fermi levels Efd and 'Efa are to each other (in other words, the impurity levels Ed, E of the donor and acceptor
The shallower f is, the difference in 7-factor lumi levels (Efn-Efp'')
becomes close to the energy gap Eg of the semiconductor.

Donor and acceptor impurity levels Ed.

zl-b = The closer to the Fermi level EiK of the intrinsic semiconductor, that is, the deeper the Fermi level difference (Efn-Efp)
is the semiconductor energy gap E, which is even further apart.

However, this does not necessarily mean that the temperature dependence becomes worse, but the difference in Fermi level (
This means that the absolute value of Efn-E4p) becomes smaller. Therefore, the difference in Fermi level (Efn-Efp) and the difference in work function are unique to materials such as semiconductor materials and impurity materials.From another perspective, the energy gap E of semiconductors and the category J Gap E in %
.

It can be used as a reference voltage source along with . In other words, the Fermi unit difference ("fn-"fp) itself has less temperature dependence than the forward voltage drop V of a PN junction or the threshold voltage Vth of an IGFET, and is not affected by manufacturing variations. Extracting the Fermi unit difference (“fn”−, Ef,) using an impurity material that can serve as a reference voltage source and exhibits shallow donor and acceptor levels Ed, Ef reduces the semiconductor energy gap EgKfi. This can be one way to extract voltages with similar values. On the other hand, when it comes to setting the voltage value to be obtained, if the purpose is to obtain a relatively large reference voltage equivalent to the energy gap of a semiconductor, an impurity exhibiting a shallow unit is used, and a relatively small If the purpose is to obtain a reference voltage, it is best to use an impurity that indicates a deep unit.

Specific example of selection of impurity materials 7 Luminous level Ef, donor level Ed, acceptor level E
c, donor concentration Nd, acceptor concentration N& and temperature T
The relationship between the two will be explained in more detail with reference to the vXz diagram and FIG. Now, in order to understand how to utilize these impurities, the data from page 30 of the above-mentioned literature is reproduced as FIG. 4, and an explanation will be added.

Figures 3(a), (b) and (c) are, respectively,
It is a diagram showing the energy distribution of various impurities with respect to GetSl and GaAs, and the numbers in each diagram indicate the energy from the lowest level Ec of the conduction band for units located above the center Ei of the gap represented by the broken line. The difference (E, -Ed) is shown, and for the lower level, the energy difference from the uppermost level E of the valence band (Ea-
Ev), and the unit for both is (eV).

Therefore, the impurity material indicated by a small value in the figure indicates that its level is close to the lowest unit Ec of the conduction band or the highest level EvK of the valence band, and the energy gap E, It is suitable as an impurity to obtain a similar voltage. For example, 8iK, which is currently being used extensively.
For the unit difference (EC-Ed) of the donor impurities of As and Bi and the acceptor impurities of B, AJ and Ga, (1,-E
, ) are the smallest, and each level difference is about 6% or less of the energy gap E2 of Sl.

Using these impurities, the Fermi unit difference (Eta - Efa) of Nho S l and past is equal to the energy gap E of Sl, if the temperature change from 0°K is ignored.
It is about 94% to 97% of 2, which is a value that is easy on Eg. In addition, the level difference (Ec-Ed
), (E, -Ev), the donor impurity is S (approximately 16% of Eg), and the acceptor impurity is In (approximately 14% of Eg).
%), and N-type S1 and Plu using each impurity
Fermi unit difference of s i (Ef, 1-"th,,;'
is about 0.85 Kg at 00K, and the deviation from the energy gap Eg of Sl is as much as about 15%, and it can be seen that the deviation becomes extremely wide with respect to the above-mentioned impurities.

Therefore, impurity materials for P-type and N-type Sl to obtain a voltage approximately equal to the energy gap Eg of Sl are L l , S b * P , A s' and B
One donor impurity selected from the group 1 and one acceptor impurity selected from the group B, A-6 and Ga are preferred; the other impurities are S
It would be suitable for the purpose of obtaining a voltage much smaller than the energy gap E of i.

Next, regarding the Fermi level difference CBfn-Efp),
The physical properties will be explained with reference to FIG. Figure 2 is a diagram showing the energy level 1 of a semiconductor.
Figure b) shows an energy level model of a NW semiconductor and its temperature characteristics, and Figures (c) and (d) each show an energy level model of a PW semiconductor and its temperature characteristics.

Carriers in the semiconductor are electrons nd generated by ionization of the donor impurity Nd, and bare electrons and holes excited from the valence band. When the impurity Nd is sufficiently large, the excited electron and hole pairs can be ignored, and the number n of conduction electrons is n+nd (1). nd is the probability of being trapped in the donor level,
Further, n is determined from the number of electrons present in the conduction band, and is determined by the number of electrons present in the conduction band. Here, h: blank constant, m'': effective mass of electron.

Here, the first term of equation (5) can be ignored since the Fermi level is determined for the case where it is located close to EeK.

This equation shows that when the temperature is low, the Fermi level is located between the lower end of the conduction band and the donor level, and the temperature dependence is approximately equal to the temperature characteristic of Ec.

Margins belowHowever, if the temperature is sufficiently high, there will be a large number of electrons and holes excited from the valence band, the influence of impurities will be reduced, and the Fermi unit will be close to the level Ei of the intrinsic semiconductor. The above relationship is shown in Figure 2).

The same is true for a P-type semiconductor containing only acceptor impurities as shown in Figure 2(C); at low temperatures and when the acceptor impurity concentration is high, the Fermi level is
It is located approximately between the top of the low electron band and the 7 receptor level, and as the temperature increases, it approaches the Fermi level of an intrinsic semiconductor.

This relationship is shown in FIG. 2(d).

Having explained the physical properties of the relationship between the temperature dependence of the Fermi level Efp*fn and the impurity concentration, next we will use the Si semiconductor, which is currently the most commonly used semiconductor, as a specific example.
The Fermi level difference (Efn-Bfp') and its temperature dependence in practical use will be explained with reference to the data in the aforementioned book 11:37.

The data is shown in Figure 3.

In the normal Si semiconductor integrated circuit manufacturing process, boron B and phosphorus P are mostly used as impurity materials, and in areas where the impurity concentration is high, 101° (atoms
/ctn, but even if the impurity concentration is 10''(atoms/c+a'), which is two orders of magnitude lower than that, as can be read from Figure 3, the Fermi level difference (Efn) between the N-type semiconductor and the P-type semiconductor is -Efp))'!, 300″
0.5-(-0,5)-1,0(eV) at K
And the energy gap at the same temperature E g = 1.
The value is relatively close to 1 eV. Changes with temperature range from 200 oIc to 400 °K (-7 (1 to 13 oC), approximately 1.04 (eV) to 0.86 (eV)
The rate of change is 0.9 (mV/C).

This is a small value of about 1/3 of the above-described rate of change of the threshold voltage Vth of the IGFET and the forward drop voltage vP of the diode with respect to temperature, which is 2 to 3 mV/C.

If the impurity concentration is 10!0ell' or more, silicon E* /"f -'f' + y F(E g )
i-1,1(V) is equal to , and the rate of change in temperature is approximately 0.2 mV/1:', which is a sufficiently small value.

Therefore, if the impurity concentration is about I Q I S Cm-3 or more, it is possible to obtain a temperature dependence that is at least 1/2 to 1/3 smaller than that of the conventional one, and more preferably 102
The concentration is OC@-3 or higher (improved to about 1/10), and most preferably saturation concentration.

7 Extraction of Lumi Level Ω Difference In the FA theory and practical example, this Fermi level difference (Efn - Efp).

On what principle can the voltage corresponding to (Efn-Ei) w (Ei-Elp) be derived? An example is when semiconductor gate electrodes of different conductivity types are formed on the same semiconductor substrate surface. 2 MOSFETs
The method is to utilize the difference in the threshold voltages Vth. A specific example will be explained below.

FIG. 5 shows a conceptual cross-sectional structure of each FET. From now on, for the sake of simplicity, we will refer to the MO8) transistor with a P+ type semiconductor as the gate electrode as P'-Ga) MOS, N-
A MOS transistor with a 1'-type half as a gate [pole] is an N+ gate MO5 an i-type semiconductor is a MOS transistor with a gate electrode as an i-gate 1! Let's call it extreme. In the same figure, the left half is the P+, i and N+ Gegu P channel MO8) transistors,
Right half is N+, i and P+ gate N channel MOS
) is a transistor.

MOS FET (Q+) ~ (Q8) in Fig. 5
, (Q4) to (Q6) are as shown in the table below.

Tables Figures 6(a), (b) to 11(a),
(b) shows a plane pattern actually used in the circuit structure and a section A-A of the plane pattern for P+ gate and i gate.

Each P-channel and N-channel MOS of JP-A-Sho GO-242658 (8) N-channel)
) The transistor is shown together with its cross-sectional structure.

In each of the above figures, the P-type regions of the source and drain are formed by diffusion of impurities using polycrystalline Si as a mask. In order to ensure a margin for mask alignment between the mask for selectively diffusing P-type impurities and N-type impurities and the source and drain regions, the gate 1! The same impurities as the source and drain regions are diffused into both end portions of the poles in contact with the source and drain of both the MOS and the N+GEG MO8. For example, in the P-channel MO8, boron, which is a P-type impurity, is diffused. In the center of the gate electrode, P
+ goo) MOS has P type impurity, N + goo MO8 has N
Type impurities are diffused.

The above figures 6, 7 and 8 show the P channel of P channel.
+ gate, i gate, N+ gate MO8 are shown in plan view and cross-sectional view, and FIGS. 9, 10, and 11 are N channel N+ gate, I gate N+ gate M, respectively.
A plan view and a cross-sectional view of O8 are shown.

In FIGS. 6 to 11, the same impurity diffusion regions as the source and drain regions of the gate taken for SE/I/7 alignment are not aligned on the left or right side (source side or In order to minimize the deviation (change) in the effective channel length of the MOS) 9 transistor due to biasing to one side of the drain side, the rows of source regions and drain regions are arranged alternately, and the rows of source regions and drain regions are arranged to the left as a whole. The half and right half are arranged so as to be line symmetrical with respect to the channel direction. Therefore, even if the (left and right) misalignment of the mask alignment in the channel direction changes the effective channel length of the FETs in each column, the P+G) MO8i gate G8 of each column connected in parallel. and N+Doug-M
The average effective channel length of the OS is approximately constant as the deviations are canceled out as a whole.

tlc12 diagram shows how P+Goo)MOS and N+
This shows how the Doug-MOS is configured.

In Figure 12(a), 101 is a specific resistance of 1Ω to 8Ω.
A thermal oxide film 102 is grown on the side N-type silicon semiconductor to a thickness of about 4000 Å to 16000 Å, and windows for diffusion are selectively opened using photoetching technology. P
Boron as a type impurity at 50KeV to 200KeV
Ion implantation is performed with an energy of about 10''-1Q1 mcm-'', followed by thermal diffusion for about 20 hours from 8 o'clock to form a P-well 103, which is the substrate of an N-channel MOS transistor.

In FIG. 2B, the thermal oxide film 102 is removed, a thermal oxide film 104 is formed with a thickness of about 1.beta.m to 2 .mu.m, and the regions that will become the source, drain, and gate of the MOS transistor are removed by etching. Thereafter, a gate oxide film 105 having a thickness of about 300^ to 1500^ is formed. On top of that, polycrystalline 5i1
06 is grown to about 2000 to 6000 A and removed by etching leaving the gate portion of the MOS transistor.

In the same figure (C), an oxide film 107 is formed by vapor phase growth and removed by photoetching in the region where P-type impurities are diffused. After that, IQIG~10"elm"@
Diffusion of boron, which becomes a high-concentration P impurity, into the P channel, +MO8) source and drain regions of the Runsister
At the same time, a P-type semiconductor gate electrode is formed.

In the same figure, an oxide film 1 is formed by vapor phase growth as before.
09 is formed, and a region where N-type impurities are diffused is removed by photoetching. After that, 10! O～l Q
Phosphorus serving as an N-type impurity is diffused at a high concentration such as RI Ca1-'' to form two-channel source and drain regions 110 on the N-channel MOS, and at the same time form an N-type semiconductor gate electrode.

Next, the oxide film 109 is removed and 4000
An oxide film of about A to 8000 A is formed, and the electrode lead portion is removed by photoetching. Then metal (
An electrode wiring portion is formed by vapor depositing An and photo-etching.

Next, lAm is covered with a 2 μm oxide film by vapor phase growth.

Here, in FIG. 12(d), Q-=Q4 is the general C
MOS that constitutes a MOS inverter, Ql, Q
* is a P+ gate for generating reference voltage.

N+ Gegu MO3.

Figures 13(a) to d) show P-channel type P+
It shows a cross section of the manufacturing process of gate MOS and iGOO) MOS. In this example, up to (C) in the same figure is the 12th
Same as up to figure (C), but in figure (d) MO
N-type impurities are diffused without removing the oxide film 1096 on the gate of 3FETQ.

Figure 14 (a) or ([) is an N-channel type P+
It shows cross sections in the manufacturing process of a gate MOS and an N+ Doug-MOS.

FIGS. 15(a) to 15(d) show cross sections during the manufacturing process of an N-channel type N+ gate MOSFET, i-gate MO8.

Next, the threshold voltage of a MOS transistor using a semiconductor as a gate electrode will be explained with reference to FIG. First of all, in the case of P + goo) MOS, the energy band diagram in Figure 16 (a) is Q It is shown that something is true.

However, here V. #Potential difference between the semiconductor substrate and the gate electrode (P-sensor conductor)・Bote ÷ L Sealer ・ φ21 Fermi potential of the N-type semiconductor substrate based on the Fermi potential of the intrinsic semiconductor q Lower limit Eys Upper limit of the energy level of the valence band EHs Fermi level of an intrinsic semiconductor In equation (7), the work function of the gate electrode is expressed as a potential and is φMP0, and the work function of the semiconductor is similarly φ , i. Therefore, V, -=-VG ten axis-φB1-φ8 . . .

Also, from the charge relationship in Figure 16 6) -COX ・Vo +Q6s-1-Qi+QB-0 ・
It is a curved surface αυ. Here, COX + capacitance of the insulator per unit area Q8B + fixed charge in the insulator QB sFixed charge due to ionization of impurities in the semiconductor substrate Qi sCarrier formed along with the channel (10,Qυ) -COX (-Va+φ ■10-φ8-φsrf)”
Song α2”Qs a + (J +QB, 0 river...
・Mountain・・・・・・02.

Since the gate voltage v(2+ is the threshold voltage when the channel Qi is formed), if the MOS threshold voltage is Vthp+, then φB-2φr.

Hereafter, the same sK is applied, and in the N+GEG MO5) transistor, the difference is only in the work function φMN+ of the gate electrode, q φMN+
...Mountain...α4q. Therefore, its threshold voltage vthN+ is now φ
It becomes s-2φr.

From this, the difference between the threshold voltages of P+GeGeMO8 and N+GeGeG MOS, Vthp0-■thN+, is Vthp” V
thN"=%p+ 4wt+14vp+-hN+ ""
...aG, which is the difference in the Fel2 potential of the semiconductor forming the gate electrode. This is because comparing (a) and (C) in Figure 16, the gate voltage when the same charge distribution is busy is the difference in the work function of the gate electrode and the difference in the Fermi level. Easy to understand 2. From the above, we found that it is possible to extract a voltage approximately equal to the energy and gap Eg as the difference between the threshold voltages of P+ Gege Mos and N+ Dagu Mos, but there are other methods. The energy gap Eg is also determined by the difference between the threshold voltage of a MOS with an intrinsic semiconductor as a gate electrode (hereinafter referred to as i-gate MO8) and the threshold voltage of P+GeGe MO8 or N+GeGe MO8.
voltage can be extracted.

i) If the threshold voltage of the MOS is thi, then
MOS
The difference in threshold voltage between
,Eg "'...'"'Q", i-gate MO3
The difference between the threshold voltages of gate MO8 and N+ is 1vthi -vthN" l-1φFN+01 *
Eg −−−+−++−41, and it can be easily seen that the voltage is exactly half of the energy gap Eg.

This i gate MO8 and P+ gate or N+ Gegu M
The voltage obtained by the difference in threshold voltage of the OS is approximately 0.
It is suitable for a reference voltage source as low as 55V, and as described later, it can be easily applied not only to the manufacturing process of CMO8 but also to the manufacturing process of single-channel MOS, since the process of doping impurities to the gate electrode can be done in one step. This is very useful as it provides an accurate reference voltage source.

Next, a process in an N-channel MO8 semiconductor integrated circuit will be explained using the cross sections shown in FIGS. 17(a) to 17(e).

(1) A semiconductor substrate 101 having a specific resistance of 8 to 20 Ω is prepared, and a thermal oxide film 103 with a thickness of 1 μm is formed on the surface of this substrate.

(Thermal oxide film is selectively etched to expose the surface of the semiconductor substrate at the base portion where the 21 MISFET is formed.

(3) After that, a thickness of 750 mm is applied to the exposed semiconductor substrate surface.
Form a gate oxide film (Sin, ) 103 of ~1oooA (FIG. 17a) (4) Selectively etch the portion of the gate oxide film 103 that should be in direct contact with the polycrystalline silicon layer to form a direct contact hole 103a. form. (Iris 17 b
) (5) Oxide film 102. Gate oxide film 103. Silicon is deposited on the entire main surface of the semiconductor substrate 101 having the contact hole 103a by CVD (Chemical Vapor D).
A polycrystalline silicon layer having a thickness of 3,000 to 5,000 Å is formed by depositing using the e-position method.

(6) Selectively etching polycrystalline silicon layer 104. (Fig. 17C) (7) The entire main surface of the semiconductor substrate 101 is coated by CVD method.
Deposit a CVD SiOx film to a thickness of 2000 to 3000 mm.

(8) The above-mentioned C
VD-8402 film 105 is selectively left.

(Fig. 17d) (9) Using the polycrystalline silicon layer as a mask, the semiconductor substrate 10 is
Diffusion of phosphorus into the impurity concentration of 10” atoms/
C'll'' source and drain regions 106 are formed. At this time, impurities are also introduced into the polycrystalline silicon layer to form the gate electrode 104b and direct contact) 10.
4c and a polycrystalline silicon wiring portion 104d are formed.

(FIG. 17d) P S G (P
hosph.

5ilicate Glass) film 107 to 7ooo
~9oo.

Form to thickness A.

αυ After that, A! It is deposited on the entire main surface of the quasi-conductor substrate 101 to form an A4 film 108 with a thickness of 1 m.

α force The above A1 film is selectively etched and the wiring area 1 is etched.
08 is formed. (1/cI Figure 7e) The circuit explained below is the difference in the Fermi level (E(n-E(1)(
This can be one way to extract E(n-EH) and (E4-E(p), but other common methods include a reference voltage that uses a voltage based on the difference in Vth of FETs with different Vths as a reference voltage. Can be applied as a generator.

FIG. 18) is a circuit that generates a voltage corresponding to the threshold voltage of a MOS transistor. Tl5T constitutes a so-called MOS diode whose drain/gate is commonly connected.

■. is a constant current source, T, -Tt are different threshold voltages vt
h1. It is a MOSFET with a mutual conductance I approximately equal to vth2, and each drain voltage is set to Vl.
-Vt is ■. = ' ``” thx )” - β (Vx Vthz)' ・・・・・・・・・・・・
・・・・Since aη, V, + −■thi” 7Fπ force ・・・・・・・・・
...0ne'V'z -vthZ +A/2I. /β
−・・・・・・・・・・・・・・・・・・α bell,
By taking the difference in drain voltage, it is possible to extract the difference in threshold voltage.

As a constant current source, you can use a sufficiently large resistor (or a diffused resistor if it has the same characteristics).

Polycrystalline Si resistor, resistor made by ion implantation,
MOS) resistors can be used.

In this circuit, if we use the N+ gate MO8 and P+ gate MOS explained earlier as P+ and Tt as an example,
It is possible to extract the Fermi level difference (Efn Efp) between the N-type semiconductor and the P-type semiconductor, which is approximately equal to the difference in threshold voltage.

FIGS. 19 and 20 are examples of circuits in which FETs having different threshold voltages are connected in series in the form of MOS diodes to extract the difference in threshold voltage. It is assumed that T has a threshold voltage Vtht e and T2 has a threshold voltage Vth2.

Under conditions that are sufficiently large compared to V+ Vt + Vthl...
・・・・・・(c)■、φVth2 ・・・・・・・・・
...... (goods) Therefore, ■, ΦVthl −
Vth2 ・・・・・・・・・・・・・・・(c).

In FIG. 21(a), a voltage corresponding to the threshold voltage is applied to both terminals of a capacitor, and the voltage held in the capacitor is extracted as a differential voltage. ) in FIG. 21 represents the operation timing. T due to clock pulse φ1
,,T, is turned on to increase the capacitance CIIcT,tTRノLt
t i[ is charged with a differential voltage of V1ht t Vthz.

After φ, is turned off, turn on T by the clock φ,
Ground the node ■ of C1. At this time, since the differential voltage between the threshold voltages is held at C2, that potential is output as is to the node (2). When used in a voltage detection circuit as described later, the potential at node (2) at this time can be used as it is as a reference voltage. However, in order to be able to use it in a more general form, the clock φ is turned on by the clock φ during the time when the clock φ is on, and the transmission (T), T, is turned on, and the potential of the capacitor PC is reduced. If it is received by a so-called voltage follower that completely feeds back the output to the negative phase input (-) of the operational amplifier 5, its output will be s 'r, j 'r, with sufficiently low internal impedance. The difference between the threshold voltages is obtained as a reference voltage.

FIG. 22 shows a reference voltage generating device that similarly utilizes the capacitance fl:Ct. T is turned on by clock φ.

At this time, T is in an off state due to clock φ. The potential of node ■ is higher than the potential of node ■ by T, the threshold voltage V
The potential of the node (2) is lowered by the threshold voltage Vth2 of T than the potential of the node (2), and the difference voltage between the two is charged across the capacitor IC. Next, when T is turned off by φ and Ic and T is turned on by φ, a voltage difference between the threshold voltages is obtained at the node ■.

FIG. 23 shows an operational amplifier used in the circuit of FIG. 21. T, , T are differential pairs constituting a differential amplifier circuit, and Ts, T.

is its active load. T constitutes a constant current circuit together with a bias circuit formed by T, , T4.

T, , T, is a level conversion/output buffer circuit with T as a constant current source load. Although the figure shows an example of the circuit configuration using C-MOS, it goes without saying that it can also be configured with a single channel MO8.

FIG. 24 schematically represents a general operational amplifier by taking only its differential part.
S) The transistors T, , T, each have a different threshold voltage v
thl and vth2, and other characteristics are assumed to be equal. Also, (-”), (
The symbols +) mean that the output is in opposite phase and in phase with the output, respectively.

If the input of T is V, and the input of T is V, then vl
Vthl a-v, vth2 or Vs Vt -V
thl 'th2 ・・・・・・・・・・・・・・・
...The output level changes depending on the conditions of the wire.

An operational amplifier has an input offset equal to the difference between the threshold voltages, and if one of the inputs is connected to ground or the power supply, it can operate as a comparator using this offset voltage as the reference voltage. I can do it. Therefore, as shown in FIG. 24, by connecting the output to the (-) input terminal and grounding the +) input terminal, a difference in threshold voltage can be obtained at the output (out). In this case, in order to operate the operational amplifier, K and TR must be depletion mode. For example, P+ goo to T1) MOS, N+ to T,
When using Gegoo MOS, both MOSFETs
Ion implantation was performed under the same conditions in the channel section of
It may be a depression type.

In FIG. 25, the reference voltage can be arbitrarily set using the operational amplifier in FIG. 24. If the output is fed back to the (-) input through the voltage dividing means Rs=Ra, and the voltage dividing ratio is r, the output voltage vo will be vthl ``th2 VO-□ ・・・・・・・・・・・・・・・・・・・・・
・It becomes ■. The voltage dividing means R*-Re is preferably a linear resistance, but any resistance may be used as long as the characteristics are sufficiently uniform to an allowable extent.

The circuits shown in FIGS. 24 and 25 are based on the assumption that a depressed type MO8 is used, whereas the circuits shown in FIGS. 26 and 27 are designed to be operable even with an enhancement WMO8. Of course, it can also be of the Depledge Seal type.

The example shown in FIG. 26 is similar to the example shown in FIG. 24, in which the output is directly fed back to the (c) input, and the output is (iii). is the power supply voltage VD
If D, then Vo = VDn (Vtbs - ■thz) ”==
In the circuit shown in Figure 24.25, it is necessary to connect at least one of the differential pairs to the degree 1 pin and 7 pin.
Depending on the case, the number of manufacturing steps may have to be increased, but it is possible to extract the voltage difference between Vth and ε with reference to the ground potential.

Conversely, in the circuits shown in Figures 26 and 27, the reference for the resulting differential voltage is the power supply voltage other than the ground potential, but there are no particular conditions for the operation of the FET.

Which circuit format to adopt can be decided depending on which advantages and disadvantages are considered.

The example in FIG. 27 is the same as the example in FIG. 25, where the voltage dividing means Ry=R@
The output is fed back to the (-) input through
becomes.

Next, regarding the application of the reference voltage generator described above, the circuit, the structure of the IC chip, etc. will be explained.

Control of Threshold Voltage The threshold voltage (Vih) of the MOSFET, which is a local element in the MO8 integrated circuit, is an important parameter that determines the characteristics of the LSI. This Vth is subject to large variations due to manufacturing processes and changes due to temperature.
The control is MO8LSII! ! This is a constructional difficulty.

On the other hand, in the MOS memory shown as an example in FIG. 28, a bias voltage is applied to the substrate to reduce parasitic capacitance. A substrate bias generation circuit is used to obtain this bias voltage. The substrate bias generation circuit is! The configuration is shown in Figure 29. Conventional substrate bias generation circuits consist only of an oscillation section and a waveform shaping section, and generally do not provide feedback based on Vth. For this reason, differences in oscillation frequency and waveform shaping ability occur due to manufacturing variations and temperature, making it impossible to obtain a stable back bias voltage v0 and causing large fluctuations in Vth.

In the present invention, a comparator using the aforementioned work function difference between the gate electrodes is used in this substrate bias generation circuit to control Vth to a constant voltage.

Vth changes depending on the substrate bias and is expressed by the following formula.

Vih-Vlho ten K (2φ, +1VBB+-2φ,)
Kokote vt11o, VBB-OV, Vth, K is the basic effect constant, and φA represents the 7 Hermi level.

Therefore, vtlm can be controlled by changing the substrate bias VIB. In FIG. 29, the oscillation circuit section uses a ring onlator. This oscillation circuit may be replaced by another oscillation circuit. The waveform shaping section includes two MOS diodes Q1.

Q and a capacitor C1, and has the function of drawing out the charge of VBB to GND by a pumping action. Due to this pumping action, vBB is pulled to a negative voltage, but 1
The maximum voltage v0 of v□I is determined at the point where the pull-out voltage due to the pump action and the substrate leakage current are stable. As long as the oscillation circuit is operating, VBIi remains at this stable point VB! However, when the oscillation stops, the charge on the substrate leaks due to the substrate leakage current and approaches the GND level.

V! When IB approaches the GND level, Vth decreases.

The comparator section shown in FIG. 29 utilizes the aforementioned work function difference between the gate electrodes, and an example in an N-channel process is shown in FIG. 30. In FIG. 30, Ql uses an N-gate MOS for the intrinsic level gate MO81Qt. Also, the dip part is one resistor and MO8FE
Consists of TQ.

Here, the resistance may be either a polysilicon resistance diffusion layer resistance or a MOS resistance, but the resistance value is such that the Vth of Qs is 0.5
It is set so that when the voltage reaches 5V, the output becomes 0.55V. Now, when vBB is close to the GND level < Vth of Qs is 0.55V or less, the input terminal of the co/validation part becomes 0.55V or less, and the output of the comparator is 11'
Therefore, the oscillation circuit is operating at R. ■□ is VilBM
When Vth approaches 0.55V and exceeds 0.55V, the comparator output becomes 02, oscillation stops, and VBB approaches GND level due to leakage. That is, a feedback loop is formed, and Vth is controlled by this substrate bias generation circuit. Since the voltages o and ssv obtained at the comparator section become the - energy gap, they do not change much with temperature, manufacturing variations, and power supply voltage as described above, so it is possible to control vth with extremely high accuracy, and the temperature A MOSLSI with a wide margin manufacturing process margin and a wide power supply margin can be obtained. Furthermore, as will be described later, the memory cell shown in FIG. 32 also has different processes.

Since an intrinsic level MOS can be obtained using the same process used to obtain a resistor (KR), it can be easily realized using a conventional process.The level shift circuit MOSLSI uses a 5■ power supply as a power supply and inputs a signal from a TTL logic circuit as an input. When using a signal, 2. as high level. OV, a low level signal of 0.8v. When converting this TTL signal to a MOS level, the ratio of the conventional input inverter is taken and Δ(OS
However, there was a problem in that the input level margin became smaller due to Vth variations and temperature changes.

An example of a TTL-+MO8 conversion circuit using the reference voltage generation circuit using the work function difference between the gate N and the pole described above will be shown.

FIG. 32 shows a specific example in which this method is used in an address write circuit of a MOS memory.

As vref, the basic single voltage 1.
Generates 4v. Using the differential amplifier shown in FIG. 33 as an amplifier, an input buffer with an input logic Vth of 1.4V is created. This method provides a TTL→MO8 conversion circuit.

As another method, the path shown in FIG. 23 may be used to input vref, that is, the input line (2) to GND and the line (2) to the amplifier. In this case T,,T,J'! Depressi Blind WM
Use O8.

FIG. 34 shows the four-jigged threshold voltage of logic circuits including inverters, the threshold voltage of MOS transistors, the threshold voltage of MOS transistors, etc., which are always kept constant against changes in temperature, etc.

Inno (-Y1゜Q=
, Qs, Q-, respectively,
4 Sick Threshold (Fllllj) M O5
I have Ql-Q4.

Q,,Q,,Q is the above-mentioned Inno Kuichita J.

It is configured to be similar (MOS) (equal Kuhn size ratio) to inverter 2, and the human power and output as an inverter are combined to obtain exactly four chic threshold voltage. It has become.

CMP1 is a comparator circuit having the base single voltage described above as the offset of the differential circuit. CMPI compares this logic threshold with the internal reference voltage, and sets KQy so that the difference t between the two becomes Plo.
control the gate voltage of

〉Marilogic Threshold〉If the base voltage is present, the output of CMPI will be at Nozue Ken level and Q.

The equivalent resistance of is increased, which acts to lower the logic threshold. When the logic threshold blind voltage is less than iJjm voltage, the opposite is true, and an equilibrium state is reached where both are equal.

The gate voltage of Q, , Q4 is common to the gate voltage of Q7, and since the former and the latter have a similar relationship, this causes the inverter 1. Inno Ku Ichiyo 2's Logistics/Thresshi Words-
The voltage is equal to the reference voltage, and the inverter has very stable characteristics.

As mentioned at the beginning, this does not necessarily apply only to inverters.
It can be similarly applied to other logic circuits such as Nando's and Noah's.

Even if it is not a CMO8IN configuration, it can be easily applied to a logic circuit such as a normal single channel inverter.

These circuits are particularly useful as input interface circuits that can reliably digitally process signals even when the range of input level and logic amplitude is narrow.

The voltage detector shown in FIG.
This is a voltage detection circuit in which a voltage to be detected is applied to one input, and the level of the voltage to be detected relative to a reference voltage can be distinguished.

In the example shown in FIG. 36, a reference voltage from a reference voltage generator using a difference in Vth is added to the comparator, and the detected voltage is applied to the other input of the voltage dividing means Ro=R+.

This is a voltage detection circuit that applies voltage divided by .

The voltage division ratio is r, the reference voltage is ref, and the detection level is 5e.
nse, and the detection level vsense can be arbitrarily set by the partial pressure ratio r.

The example in FIG. 37 uses an operational amplifier with an offset corresponding to the difference in Vth, and uses an operational amplifier with an offset corresponding to the difference in Vth.
This is a voltage detection circuit that uses the set voltage as the base '1jIL voltage. Further, R, . . . R, are the same voltage dividing means as in the example of FIG.

In the example of Figures 36, 36, and 37, if the detected voltage is the power supply voltage, it can be used as a battery checker in a system that uses a battery as the power supply. Fig. 44 shows a specific example in which the voltage detection circuit shown in Fig. 37 is applied to a battery checker for an electronic watch, but a detailed explanation will be given later.The example shown in Fig. 38 is an example of a voltage regulator applied to a stabilized power supply circuit. It is. The reference voltage generation circuit is configured using the several methods described above, and compares a part of the stabilized output with the reference voltage using Rts*R14, and sets T, so that they match. control the gate voltage and stabilize the output voltage. Any operational amplifier may be used as long as its characteristics are acceptable.

The example in FIG. 39 is T, in the example in FIG. 938. Instead of using a transistor (MOS), a Bibo2 transistor T is used instead.
R, is used.

The example shown in FIG. 40 uses an operational amplifier having the offset voltage shown in the example shown in FIG. T□ may be a MO8 transistor, a bipolar transistor, or a junction field effect transistor.

Constant Current Device The example of FIG. 41 is a constant current circuit determined by the difference in threshold voltage between T and T.

Tt, Tt have the same transconductance β, and threshold voltages th, th with different v, v, respectively.

be. If the resistance R1° is sufficiently high compared to the impedance of T, the drain voltage (-gate voltage) vt of T1
becomes approximately equal to vthI.

When T is in the saturation region, the current 12 flowing through T is becomes.

The example in FIG. 42 is T2. ■ Voltage drop due to electric current flowing through the circuit. This is a constant current circuit that compares utR□ with a reference voltage ref and controls the gate voltage of T so that both are always equal.

becomes.

Here, the reference voltage may be obtained by providing an operational amplifier with an offset, as in the previous example.

The example in FIG. 43 is T3. , T, are the same transistor, and is a constant current circuit using a so-called current mirror circuit.

The example of an electronic watch shown in FIG. 44 is an example in which the battery checker shown in the example of FIG. 37 is applied to an electronic watch.

'r, e T, # T41-T4@ and R4m and Ro constitute a circuit that checks the voltage level of mercury battery E, nominally 1.5V. The transistor pair of the differential part is P
+Gate/N channel-MOS, N+Gate/N channel-MOS T + -T *The threshold voltage of both is 1.0V, which is the operating power supply range of electronic watches.
Ion implantation is done in the channel part so that the voltage is within ~1.5V.

In the case of silicon semiconductors, the difference in threshold voltages serving as reference voltages is approximately 1. 1V, and is adjusted by the resistance ratio of the resistor stages R, , R, in order to adjust the level at which the voltage of the battery is detected to be around 1.4V.

This battery checker operates intermittently for 5 times in response to the p-switch signal φ obtained through the branch timing circuit TM in order to make the current consumption negligible in terms of actual pressure.

The output of the battery checker is a NAND gate game.
The timing circuit TM is controlled by the logic level of this latch circuit output, thereby changing the drive output of the motor and changing the method of hand movement. IJ- indicates a decrease in pressure. A decrease in battery voltage can be indicated without changing the movement of the pointer, by blinking an electro-optical element such as a liquid crystal or a light emitting diode.

In the same figure, O8C is a crystal oscillator circuit composed of a CMOS inverter and includes a crystal Xta and capacitors CG and CD outside the IC, and WS is a waveform shaper that converts the oscillation output from a sine wave to a rectangular wave. Circuit, CM is the excitation coil of the step motor that drives the second hand, B F 1. B
F t is formed by a CMOS inverter and excitation coil C
This is a buffer for driving M with its polarity reversed every second.

All circuits within the IC are powered by a nominal 1.5v mercury cell E. Further, TM is the divided output of a plurality of different frequencies of the frequency dividing circuit FD and NA, , NA.

This is a timing pulse generation circuit that receives as input the control output of the latch generated by S and generates a pulse having an arbitrary period and pulse width. IC is St Gegu C shown in Figure 6.
This is a monolithic Si semiconductor chip for pointer type electronic wristwatches made using the MO8 process.

The present invention has been described above based on various embodiments, but
The technical idea described herein is not limited to this, and may be applied to electronic devices for various other uses.

Next, a specific example will be described in which the reference voltage generating means according to the present invention is applied to a state setting circuit, an auto clear circuit, etc. of an electronic device.

FIG. 45 is a circuit diagram showing an example of a state setting circuit;
It is composed of MOSFETs. In the same figure, a
If the potentials at points and points b are O, when the power ('-VDD) is turned on, MO8FET, T, )tN-MOSFET are both in the "ON" state, and points a and b are in the "ON" state when the power is turned on. At the same time, it is pulled by the t source @ (-Vno). At this time, the N-MOSFET of T3 uses the energy band difference of semiconductors, and the VthN of 7 is MO8FE.
Approximately three times that of TT (e.g. T+ Vth-0,45
v-Ts ■th-1,25V), so
During power down, N08FETs are turned off first.
"'. Since MO8FET continues to be in the "ON" state, point b is -VDD * point a is GND
It becomes stable at a potential of .

Also, when the power (-VDD) is cut off, OV at point a
.

When a charge remains at about 1V at point b, (1. VDD-840SFETT on the way down from the power supply.

T is in the "OFF" state until Vt hN of
Since it becomes 1N'' state at N, point a is QV, L in the initial state.
Even if point t is at about IV (or up to VtM of T), in a stable state, point b is at Vl)D and point a is at Ov. Furthermore, since this circuit is entirely composed of E-MOSFETs, the current in a stable state is almost zero.

FIG. 46 is a circuit diagram showing an example of a conventionally proposed state setting circuit. In the same figure, in order to increase the stability of the latch circuit,
OSFET is inserted. Kono D-MOS F E
TKJ: ')' When Wig (-VDD) is turned on, point a always falls at the same time as the power supply, and point b will not turn ON unless the power supply falls to the Vth of MO8FET, so in a stable state, point b VpDe a point becomes Ov. However, in this circuit, a D-MOSFET is used between point a and VDD, so next, in some form, point a VDp *
When point b becomes 0V (RESET) state, P-MO8F
ETTs becomes 'ON''', and a DC bus is generated due to T and T, resulting in a large current consumption.On the other hand, the state setting circuit of the present invention shown in Figure 5 #!45 ensures the state setting as described above. In addition, since the current consumption can be extremely small, it is possible to provide an effective state setting means.

Next, a voltage regulator according to the present invention and an example of its application will be explained.

7-- --Secondly, FIG. 47 shows a voltage regulator according to the present invention, and FIG.
Figure 8 shows its characteristic diagram.

The comparison type voltage regulator shown in Fig. 47 has a configuration similar to that of a known one, but when viewed from both the voltage comparator CP sicalas and negative input terminals, there is an asymmetric arc in the voltage level compared to a normal voltage comparator. It's different. In other words, this voltage comparator is not balanced when the voltage levels of both the positive and negative inputs are equal, but is balanced when a predetermined high input voltage (in absolute value) is applied to the negative side. In other words, the positive and negative input levels of this voltage comparator have an offset with respect to the balance point.

According to such a voltage regulator, the input voltage ■in
If the output voltage is high, ■. ut depends on the reference voltage vref and is 1. The difference between ut-・Vin l is large (it is taken, but
If the input voltage ■in is low, select ■. ut depends exclusively on Vin, and the difference between 1 and 1n-Vout' is made small. The change point P between the two is, regarding the input voltage ■in,
Vin, +V1 (L is the lowest operating voltage of the regulator load).

According to the voltage regulator configured in this way, when the input voltage vin is high, the load / is lowered to the lowest operating voltage vI
The output voltage V is higher than the input voltage Vffin but lower than the input voltage Vffin.
. Since it is operated at UT, power consumption is reduced while operation is guaranteed. Also, when the input voltage ■in is low,
The load Z is an output voltage V that is approximately the same as the input voltage vin or slightly smaller than it. Since it is operated at ut, a minimum operating voltage V is guaranteed for the input voltage vin of the load Z, and for a high input voltage vin, the output voltage V is adjusted to a voltage that matches the load. This voltage regulator has low power consumption and wide input voltage range for the load/load.
It can have a width of in.

These effects will be explained in detail in comparison with a voltage comparator regulator having no offset using the graph shown in the $48 diagram.

In the figure, the horizontal axis is the input voltage vln, and the vertical axis is the output ■. u
t and reference voltage ref. Curve a is Vi
■ Equal to n. In other words, it shows a hypothetical curve when the load / is operated directly at the input voltage ■in without using a voltage regulator.

Curve C shows the general reference voltage ref , v2, using the current amplification factor hfc of the bipolar transistor,
V, e (GEN's output voltage V, f is its electrical voltage ■i
Depends on n (vref = '(Vin month.

In the case where the voltage comparison circuit CpT uses such a reference voltage ■refl as the quasi-voltage, and the comparison circuit CP does not have an offset as described above.

Output voltage■. ut is equal to the reference voltage Vr,,1, which corresponds to the curve C - and the reference voltage vref1 is higher than the input voltage vin, so the output voltage vou
t is lower than the input voltage ■in in any range. As a result, the output voltage ■. The input voltage Vin4''i when ut becomes equal to the minimum operating voltage of the load Z (point R)
Vt (Vt >L) Tona'; b. Kzte, load/
The possible usable range of the input voltage vin is IV, -V,
A loss will occur by the voltage corresponding to l.

In order to reduce this loss, in the voltage regulator shown in FIG. 47, the comparator CP
Configure.

In addition, as a reference voltage, a reference voltage ■reft (curve id) that is smaller than the virtual reference voltage vrefs and has similar characteristics
, the actual comparison voltage (V,.f2+Δvoff) at the target normal input voltage V is the virtual reference voltage vre
The values of vref2 and ΔVoff are set to be equal to f1, that is, to match the target operating point S.

According to such a configuration, the voltage comparator CP has Vout
The input voltage ■in that is balanced under the condition of −■ref2+Δ■off and satisfies this equilibrium condition is only when ■in≧vref2+Δ■off because vin≧■out.

When the input voltage vin is smaller than (Vref2+Δ■off), the output voltage ■In is also smaller than that, so the comparator CP outputs the voltage V. However, this feedback control is limited when ut is made equal to the input voltage Vio (because vout41n).

9. Press the output ■. ut is V in −V r ef
2+Δvoff as the inflection point (P), the input voltage Vi
When o is higher than the inflection point P, vref2+ΔVoff
(song #jb1), and when ■in is lower than that, it is made approximately equal to the input voltage vAn (song #!at).

If this inflection point P is equal to or higher than the lowest operating voltage V+ (point Q) with respect to the input voltage vin (on the horizontal axis), the above-mentioned loss can be avoided.

This is because the curve has an intersection with the song ia due to Δ■off, and such an effect cannot be obtained when the curve does not have an intersection with the song Ha, such as the song id.

Note that the FET shown in FIG. 47 works as a source forwarder (as it is a depletion mode N-channel FET, so it is possible to set Vout="in" and there is no loss of its threshold voltage Vth. Therefore, this Input voltage ■i
This is effective when n is small.

However, this does not negate the use of an enforcement mode source follower FIT, and since the input voltage is large (vthPA loss is a serious problem), the depletion mode FET manufacturing process is It is extremely effective when it is difficult to adopt the lower output voltage V.ut (below the changing point P).
a, (Vout=”in) is only shifted downward by Vth (■.ut”■1n-Vth), and the output voltage is ■. It is still possible to give ut the effect described above.

Also, in the diagram, N channel y F E T is changed to P channel F
It can also be replaced with ET, in this case P channel FET
acts as a source ground, so there is no Vth loss as described above.

There is no essential difference whether a source-grounded or source-follower is used as a control FET, but if the source is grounded, special consideration must be given to threshold voltage Vth loss, such as when using a deblessing mode FET. 8 Not public. In addition, if a source follower is used, this FET can be This is useful because it works as a voltage follower. In other words, if the mutual conductance gm of this FET is sufficiently high, the output voltage is uniquely determined by the gate voltage.

It is also possible to use a bipolar transistor as the control transistor.

Offset■. Although it is not necessarily denied that ff is a function of the input voltage ■in, in setting the inflection point P, it is desirable that it be one foot smaller than ■in.

Also, as the reference voltage vraft, there is a variation similar to the load/9! If you use a reference voltage with a constant voltage, the output voltage will depend on the characteristics of the load. This is also convenient because you can get ut. In that case, if vref2 is set to the lowest voltage for operating the load, Δvoff can be used as a constant margin means.

The configuration that provides the offset Δvoff and its applied circuit will be described later, but here we will explain another method of providing the output voltage ■out with an inflection point using the circuit diagram in Figure 49 and the graph in Figure 50. .

In the following explanation and the graph of FIG. 50, all voltage values are absolute values.

In FIG. 49, Q. , are N-channel depleted mode FETs or control transistors o Q, os and Qtot and Q104 p Qros
constitutes a current mirror circuit S, and a drain current approximately equal to the drain current of QIo3 flows through the diode-grounded FET Q104 and Q+asK. Diode-connected P-channel FETQ+. 4. Voltage drop between source and drain of N channel/I/FET Qros■D8 is high impedance load QIwas Q
Each threshold voltage Vthp, depending on ros,
Vthn.

Therefore, voltages of Vthp and (vin - Vthn) are applied to both the plus and minus input terminals of the comparator CP, respectively (curves d and b in Figure 50).

Comparator CP has no offset and is therefore balanced when both inputs are equal. Therefore, the equilibrium condition is (■ou
t −Vthn ) ””■thn, j that is ■. ut
-vthp +■thn. ■in box■. From the conditions of ut, the output voltage vout is vjniThvthp+
■thn (1”) fICvthp +■thn)
Limited to・vjn'! When vthp+■thn, it becomes approximately equal to vin. Therefore, when the load Z is composed of CMO8, its operating lower limit voltage is normally (vthp+
Vthn)K, so the output voltage vout can compensate for it.

Note that the threshold voltage taken out by the MOS diode circuit is close to the original threshold #L voltage, but is not equal to it, and follows its drain current.

■ Output voltage at equilibrium point. Of course, it is better to make ut larger than the original (Vth, 10゛■thn), and for that purpose, the mutual conductance of FET Qros should be made small to reduce the current flowing through each MOS diode Q+04 and Qros. Good.

In addition, the near threshold voltage extracted by the MOS diode is predisposed by the flow of drain current, so
Even if the input voltage vin is low, the circuit must be configured so that current flows through both diodes.Next, an example of applying the voltage regulator shown in Figure 49 to an electronic watch will be explained using Figure 51. .

In FIG. 51, O20 is a crystal oscillator, WS is a waveform shaping circuit that converts the sine wave oscillation output into a rectangular wave, FD is a frequency dividing circuit, and TM is a timing diagram for creating a pulse with a predetermined period and width from the branch output. Pulse generation circuit, LF is a level shift circuit that converts a low level signal to a high level signal, BC is a battery life detector, VC is a voltage comparator, VR is a voltage regulator using it, H is a hold circuit %D
T is an oscillation state detector, and LM is a step for driving the second hand.
This is the excitation coil of the motor.

The detector DT detects the oscillation of O20 through the branch divider FD and the timing circuit TM, and when it oscillates, operates the voltage regulator VR to output the oscillators O8C and WS,
Reduce the operating power supply voltage of FD, TM, etc. from 1.5v.

'Ij1mE [1MJ, the input node of inverter I7 is connected to ground potential (logic 'O
'), so N channel FET Q,
. , is turned ON, and the output of the regulator is set to 1.5■ of the battery voltage. At this time, Qtos is also turned on and the FE
The gate node of TQ*ot is photoelectrically connected (this is done by activating the negative feedback loop of the regulator in advance so that the regulator output does not drop at the moment FET Q2゜, switches to 0FFK). It is for storing.

When the oscillator starts operating, the other logic circuits are already in operation, so a pulse φB is supplied from the timing circuit TM to the detector DT. Exclusive OR circuit EX
, detects the output of this pulse φ8, and one input has an inverter I41L and an integrator circuit C, , , R, for the other input. A pulse φ, delayed by , is applied. Therefore, when pulse φ8 is output, goo)EX
A pulse with a width corresponding to the delay time is generated at the output of .

This pulse is FETQ□1, inverter. , is integrated in a rectifier circuit consisting of capacitor C south, and for a while after φD starts appearing, 8 and N channel, FETQ,. I.

Turn off Qtos. Thereby, the regulator VR generates a predetermined output voltage (less than 1.5 V) only by its own control loop, contributing to low power consumption.

The operation of this regulator, particularly the voltage comparator VC, will be explained below. This comparator VC is based on the principle diagram in @47 and Figure 48.
Since the operation is similar to that of ratio IIi and device OP explained in the extensibility diagram in the figure, I will keep it to a simple explanation (.

P-channel MO5FETQx. 6. Ql. , is the offset voltage V. To obtain fft', Q,. , the gate of Ql in FIG. 5 is set to P-line as shown in FIG. 6, and the gate of Qtot is set to Qm -jl! of FIG. 5. It is made into an N type as shown in Figure 7. Therefore, Q. ) threshold voltage Vth is Q
It is approximately 0.55V higher than us, and this is the offset voltage V mentioned above. It becomes ff. N-channel FETQ,
. , and P Teyanne A/FETQ. , are both diode-connected, so Q, which is the positive input of comparator VC,
,. , both Vth phases (Vthp+■thn
) is applied, which is the song mc in FIGS. 48 and 50.
It becomes the voltage of ref2 shown by trc.

Therefore, the output voltage of voltage regulator VR is ■. ut is v
out″″vtbp+vthn+ΔVoff (■in
! , vthp''Vthn+Δvoff).

When the input voltage vin is low, proceed as described above ■. ut"■i
It becomes n.

This comparator uses a timing signal φA to reduce power consumption.
Operating time is limited by vc. Of course the reference voltage■
The same goes for the circuit that obtains refz, and the capacitor CIO is set to hold the refz voltage.
2 or Q. , to hold the gate voltage of capacitor CI0! It is added separately from parasitic capacitance such as gate capacitance. The capacitor clos is used to prevent oscillation caused by phase rotation caused by several FETs connected in cascade in the feedback loop.

Since the battery checker BC' has the same structure as shown in FIG. 44, the explanation thereof will be omitted.

In addition, the excitation coil driver I3, (2) in the output stage of the IC is directly powered by a 1.5V battery in order to increase its driving capacity.

FIG. 52 shows an example in which the voltage regulator VR and battery checker BC according to the present invention are applied to a digital display electronic watch.

In the same figure, 08C, WS, and FD are powered by an regulated voltage lower than 1.5V, similar to the example in FIG. 51.

In addition, internal IC circuits such as the deco radar DC time adjustment circuit TO also use a low voltage as a power source.

DB has a voltage of 1.5V. This is a signal voltage circuit that boosts the voltage to Ov, and this voltage is used as a driving voltage for the liquid crystal display device DP (the driver is omitted and is shown at 0.degree. C.).

/S is a level shift circuit that converts a low signal level to a high DC voltage and supplies it to one circuit with a high power supply voltage.In this way, a normal logic circuit inside an IC that operates at a low operating voltage has a low A supplementary operating power supply is used for display drivers, etc. that require high operating voltages for IC input/output interfaces.

This is effective in reducing power consumption and expanding the range of power sources used.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the energy gap Eg of GaAs, Si, and Ge semiconductors and its temperature dependence. Figure 2 is a diagram showing the semiconductor level and Fermi level E ((al, (bl) is for an N-type semiconductor, (c), (d) is for a P-type semiconductor. Figure 3 shows the Nokund structure and Fermi level.
FIG. 7 is a diagram illustrating temperature characteristics of the Fermi level of type 8i and P type 8i, with impurity concentration as a parameter. Figure 4 (a
). (b) and (c) are Ge, Si and GaA, respectively
FIG. 3 is a diagram showing the distribution of energy levels of an s-semiconductor and various donor and acceptor impurity cars. Figure 5 shows the Fermi level difference (E
fn−”rp) can be used to retrieve P+
The cross-sectional structure of the gate and N+Gege MO8FET is schematically shown, with the left half showing the P-channel NFET and the right half showing the N-channel NFET. Figures 6(a) and (b) respectively show a plan view and a cross-sectional view of a P+ gate P channel/L/MO8FET, and Figure 7(1)
, (b) k-guo/i-gu) P-channel MO8FET's plan view and cross-sectional view, FIG.
Figures (a) and (b) are N+gege N channel A/MO
The plan view and cross-sectional view of the 8FET are shown in Figure 10(a) and (
b) shows a plan view and a cross-sectional view of an i-gate N-channel MO8FET, and FIG. 11(a). (b) shows a plan view and a cross-sectional view of a P+gege N-channel MO8FET. Figures 12(a) to (d), Figures 13(a) to (d), Figures 14(a) to (d), and Figures 15(a) to (d) are
FIG. 7 is a cross-sectional view of the main steps when manufacturing complementary MO8s together. Fig. 16(a) and (b) are respectively P”!semiconductor-
Figures (c) and (d) show the energy state and charge state of the N+ type semiconductor-insulator-N type semiconductor structure, respectively. be. Figure 17 (a) or e) is an N-channel MO8FE
It is sectional drawing in each manufacturing process of T. FIGS. 18(a) and 18(b) are diagrams showing characteristics of a saving MOS diode circuit and its circuit for extracting the difference in Vth of two FETs having different threshold voltages Vth. Figures m19 and 20 each show an example of a reference voltage generation circuit that utilizes the difference in Vth, Figure 21 (a) shows an example of another reference voltage generation circuit, and Figure 21 (b) shows its timing. Shows the signal waveform. FIGS. 22 to 27 show reference voltage generating circuits according to still other embodiments. Section 28 shows a block diagram of the semiconductor memory, and FIG. 29 shows a detailed circuit diagram of the substrate bias generation circuit of FIG. 28. FIG. 30, FIG. 31, FIG. 32, and FIG. 33 show circuit diagrams of a comparator circuit, a memory cell circuit, an address pack 7 circuit, and a differential amplifier, respectively. FIG. 34 shows a circuit diagram of the logic circuit. Figures 35 to 37 show examples in which the basic S voltage generation circuit is applied to voltage detection circuits, Figures 38 to 40 show examples in which it is applied to voltage regulators, and Figures 41 to 43 show examples in which the basic S voltage generation circuit is applied to voltage detection circuits. FIG. 44 shows an example applied to a battery checker for an electronic wristwatch. FIGS. 45 and 46 are circuit diagrams for explaining examples of the present invention and conventional state setting circuits, respectively. FIG. 47 is a circuit diagram for explaining an example of the voltage regulator according to the present invention, and FIG. 48 is an electrical characteristic diagram for explaining its operation. FIG. 49 is a circuit diagram for explaining another example of the voltage regulator according to the present invention, and FIG. 50 is an electrical characteristic diagram for explaining its operation. FIG. 51 is a circuit diagram for explaining an example in which the present invention is applied to an electronic timepiece, and FIG. 52 is a circuit system diagram for explaining an example in which the invention is applied to a digital display electronic timepiece. T...MOSFET, R...resistance, C...capacitor, Xtal...crystal sensor, OSC...crystal oscillation circuit, WS...sine wave-square wave conversion waveform shaping circuit,
FD...Binary power Kunta multi-stage connection branch circuit, TM...
Timing circuit, CM...excitation coil for the step motor for driving the second hand, BF...buffer for CMf>E1m, NA...N person ND game), IC...monolithic Si semiconductor integrated circuit chip, φ.・Clock pulse,
Eg -- Semiconductor energy gap, Ev...
Upper limit level of valence band, EC...lower limit level of conduction band, Ei...Fermi unit of odorous semiconductor, B(ne
Ef,...Fermi level of N-type and P-type semiconductors, E d
T E B...Donor, acceptor level. Fig. 1 Fig. 3 Fig. 4 (a-) Fig. 18 Fig. 19 Fig. 20 Fig. 21 (b) Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 kr Figure 34 Figure 35 Figure 36 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 46 Figure 45 Figure 47 Figure 48 □■ Figure 52 Procedural amendment (method) Display of case 1982 Patent Application No. 222169 Person making the amendment Case and Section 1 Patent Applicant Name Name 75101 Stock Company R1 Manufactured by Hitachi Inc. Address: Hitachi, Ltd., 5-1 Marunouchi, Chiyoda-ku, Tokyo 100 Telephone: Ji□l+212-11
Detailed description of the invention in the specification subject to amendment Contents of amendment 4; ≧, as attached

Claims (1)

[Claims] 1. A plurality of IGFETs, a bias voltage generation circuit that applies a bias voltage to the back gate of each IGFET, and a first IGFET that is one of the plurality of IGFETs.
and a voltage comparator circuit that forms an output signal in response to a difference between a voltage corresponding to a threshold voltage of the gate electrode and a reference voltage, the reference voltage being a threshold voltage corresponding to a 7-luminium level difference of the gate electrode. The second with a value voltage difference. It is formed based on the threshold voltage difference of the third IGFET, and the bias voltage generation circuit is controlled by the output signal of the voltage comparison circuit.
A semiconductor integrated circuit characterized in that a bias voltage applied to the back gate of each of the IGFETs is set to a predetermined value. 2. The voltage comparator circuit has the same function as the second voltage comparison circuit. a third IGFET; The sources of each of the third IGFETs are coupled to each other, the gate of the second IGFET is supplied with a voltage corresponding to the threshold voltage of the first IGFET, the gate of the third IGFET is supplied with a predetermined voltage, and at least 2. The semiconductor integrated circuit according to claim 1, wherein the output signal is formed based on a signal taken out from the drain of the second or third IGFET. 3. The semiconductor integrated circuit according to claim 2, wherein the gate and drain of the first IGFET are coupled, and the voltage extracted from the drain is supplied to the gate of the second IGFET. circuit. 4. Above 2. 3. The semiconductor integrated circuit according to claim 1, wherein each gate electrode of the third IGFET has a semiconductor layer portion having a different conductivity type. Margin below