JPS60143011A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a reference voltage generator with less temperature change by setting a logical threshold value of a semiconductor integrated circuit based on the difference between the 1st and 2nd threshold voltages different from each other. CONSTITUTION:An IGFETT1 having a threshold voltage Vth1 and an IGFETT2 having a threshold voltage Vth2 are connected in series in a form of MOS diode. In setting resistors R1, R2 to a sufficiently large value in comparison with the impedance of the T1, T2 respectively, since the difference between the gate voltage of the T1 and an output voltage V2 is expressed as V1-V2 Vth1 and V1 Vth2, the reference V2 Vth1-Vth2 is obtained and the logical threshold voltage is set to the difference of the threshold voltages of the T1 and T2. Since the threshold voltage is controlled at manufactured based on the energy gap specific to the semiconductor, a reference voltage generator with less temprature dependancy and less variance between manufacture lots is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic device, a special voltage reference voltage generator and its applications, as well as an insulated gate field effect transistor and a manufacturing method thereof.

In various semiconductor electronic circuits, in order to generate a reference voltage, it is essential to use a physical quantity having the dimension of voltage. Until now, the physical quantities have mainly been the forward voltage drop of a PN junction diode, the reverse breakdown voltage (Zener voltage), and the voltage of an insulated gate field effect transistor (often represented by IGFET or MOSFET). Threshold voltage Vth, etc. are used.

These physical quantities do not indicate absolute voltage values, and the voltage values are subject to fluctuations depending on various factors. Therefore, in order to utilize these physical quantities as a reference voltage generating device for various electronic circuits, it is necessary to pay attention to the fluctuation factors of the obtained voltage value and the permissible fluctuation range.

First, regarding the temperature characteristics of these physical quantities, the above V
F and Vth usually have a temperature dependence of about 2 to 3 mV/c, and the temperature change in the reference voltage that accompanies this temperature change is so large that it may be necessary to give up on practical use depending on the application.

For example, if you want to create a battery checker for an electronic watch that uses a nominal 1.5V silver oxide battery to warn that the battery voltage has dropped,
It is necessary to judge whether the battery voltage is high or low, with the boundary (detection level) at about 1.4V.

This is the MOSFET threshold voltage vt of about 0.6V.
Or, if you try to configure it using the diode's forward drop voltage (2), the detection level with a target of 1.4V has a temperature dependence of = 4.67 to 7.0 (mV/C). , the practical operating temperature range is OC~50C
The narrow estimate is 1.23V to 1.57V (
Since it fluctuates, it cannot be used as a practical battery checker.

Next, regarding manufacturing variations in these physical quantities, MOS
The threshold voltage Vth of the FET varies by approximately ±0.2 V, and this variation is larger than the temperature change. Therefore, if the above-mentioned battery checker is made into an IC (integrated circuit) using vth, not only external parts and connection pins (terminals) for correcting the reference voltage but also adjustment after the IC is manufactured are required. .

Also, in MO8FET integrated circuits such as semiconductor RAM,
By applying a reverse bias voltage to the substrate (back gate),
If you want to control the threshold voltage of a FET, you need a reference voltage source that is independent of temperature dependence and manufacturing variations, and it also needs to be possible to integrate it. Difficult to hire for a number of reasons. Also,
Zener voltage ■2 has a low voltage limit of about 3V,
It is unsuitable as a reference voltage to be used in the low voltage range of 3.
It is necessary to flow a current of about A, which is inappropriate in terms of reducing power consumption.

As is clear from the above explanation, conventional reference voltage generators using KVth, VF, and V2 are not necessarily suitable for all uses, considering temperature characteristics, manufacturing variations, power consumption, voltage levels, etc. In many cases, practical application and mass production had to be abandoned for applications requiring extremely strict characteristics.

From the above studies, the present inventors learned that there are physical limits to the improvement of conventional reference voltage generators, and decided to research and develop a reference voltage generator with new ideas and ideas.

As a reference voltage generator, for example, Japanese Patent Application Laid-Open No. 48-632
The one shown in Publication No. 57 is publicly known.

An object of the present invention is to provide a reference voltage generation circuit based on a completely new idea not seen in the past, and to facilitate the design and mass production of electronic circuits.

Another object of the present invention is to provide a reference voltage generator with small temperature changes.

Another object of the present invention is to keep fluctuations in voltage values small relative to fluctuations in production conditions, such as manufacturing variations between lots (
It is an object of the present invention to provide a reference voltage generating device with a small deviation).

Another object of the present invention is to provide an integrated circuit reference voltage generating device that can reduce manufacturing variations to such an extent that post-manufacturing adjustments are unnecessary.

Another object of the present invention is to provide an integrated electronic circuit device including a reference voltage generating device that can be manufactured with a large margin of tolerance to target specifications.

Another object of the present invention is to provide an integrated electronic circuit device including a reference voltage generator with high manufacturing yield.

Another object of the present invention is to provide a reference voltage generator suitable for IGFET integrated circuits.

Still another object of the present invention is to provide a reference voltage generator and a voltage comparator that consume less power.

Another object of the present invention is to provide a reference voltage generator capable of obtaining a low voltage (1.IV or less) with excellent accuracy.

Another object of the present invention is to provide a reference voltage generator that is compatible with relatively low voltage power sources (approximately 1 to 3 µm), such as 1.5 µm silver oxide batteries and 1.3 µm mercury batteries. be.

Another object of the present invention is to provide a reference voltage generator suitable for semiconductor integrated circuits.

Another object of the present invention is to provide a highly accurate voltage comparator, regulated power supply, constant current circuit, and battery checker.

Another object of the present invention is to provide a semiconductor integrated circuit device for electronic time-opening, which has a built-in highly accurate battery checker and has a small number of external terminals.

Another object of the present invention is to provide a back-biased IG
An object of the present invention is to provide an IGFET integrated circuit in which the threshold voltage of an FET can be maintained at a substantially constant voltage independent of manufacturing variations and temperature changes, thereby improving manufacturing yield.

Another object of the present invention is to provide complementary insulated gate field effect transistor integrated circuits (CMO8IC) and N-channel MO8I
It is an object of the present invention to provide a reference voltage generator compatible with C- and P-channel MO8ICs, and a method for manufacturing the same.

The present invention returns to the origin of physical properties of semiconductors and metals, and in particular, energy gap E, work function φ, Fermi level Ef
It was created by focusing on the following.

That is, it is well known that semiconductors have various levels such as energy gap Eg, donor, acceptor, and Fermi level, but the physical properties of these semiconductors, especially energy-
A reference voltage generator that focuses on the gap Eg or the Fermi level Ef has made remarkable progress in a wide range of fields since the discovery of semiconductors, and has never been seen before.

In terms of results, the present inventors determined the energy gap E, the work function φ, and the Fermi level E.

etc. as a reference voltage source, and succeeded in realizing it. Using the energy gap Eg, the luminescence level E, etc. as a reference voltage source is by no means a difficult theory (and the results are easy to understand and agree with. However, it is no longer a shallow history. In the field of semiconductor industry, this success story, which is believed to be unprecedented, brought about by the inventors of the present invention by going back to the origins of semiconductor (physical properties), is original and groundbreaking, and will lead to future electronic circuits and semiconductor industry. It is expected that this will greatly contribute to the further development of the world.

According to one embodiment of the invention, two IGFETs with different conductivity types of silicon gate electrodes are fabricated within a silicon monolithic semiconductor integrated circuit chip. These FETs
are manufactured under almost the same conditions except for the conductivity type of the gate electrode, so the difference in v and h between the two is almost the same as the difference in the Fermi level of P-type silicon, N-type silicon, and i-type (intrinsic semiconductor) silicon. be equal. The P-type and N-type gate electrodes are doped with respective impurities near the saturation concentration, and this difference is approximately equal to the silicon energy m-gap Eg (approximately 1.1■) or Eg/2 (0.55Vl). , which is used as a reference voltage source.

A reference voltage generating device based on such a configuration has low temperature dependence and small manufacturing deviation, so it can be used as a reference voltage generating device for various electronic circuits.

The present invention and further objects thereof will be more clearly understood from the following description with reference to the drawings.

It begins with the crystal structure of semiconductors, and expands to the energy bands of semiconductors and the phenomena brought about by donor and acceptor impurities in semiconductors (the theory of physical properties of semiconductors is explained in numerous literatures).

It is of course well known that semiconductors of different compositions each have their own energy gap Eg, and that the energy gap Eg, expressed in eV, has the dimension of voltage. However, as mentioned above, there has never been an example in which a semiconductor has a unique energy gap Eg and this temperature dependence is small, and this is utilized as a reference voltage source.

Since this embodiment was developed starting from the basics of semiconductor physical properties, a detailed explanation of the present invention will first start from the fundamentals of the present invention with reference to the physical properties of semiconductors. The physical properties of semiconductors are explained in detail in many documents, and the following will refer to one of those documents, “physics of
Sem1conductorDevices”, 196
Published by John Wi Iey & 5ons in 1999, especially Chapter 2 “Physics and Pr.
operations of Sem1 conductors
-A Resume” will be briefly explained with the help of pages 11 to 65.

There are various compositions of applied semiconductors for the energy gap Eg, among which the representative semiconductors currently used industrially are non-compound semiconductors such as germanium (Ge) and silicon (Si), and gallium and silicon (Si). It is an arsenic (GaAs) compound semiconductor. The relationship between these energy gaps Eg and temperature is explained on page 24 of the aforementioned book, and this is
As can be understood from Figure 1, Ge, Si and G
The Eg of a A s is at room temperature (300'K), respectively.
0.80 (eV), 1.12 (eV) and 1.43 (
eV). Moreover, the temperature dependence is 0.
39 (meV/”K), 0.24 (meV/”K
) and 0.43 (meV/”K). Therefore,
By extracting a voltage corresponding to or close to these energy gaps Eg, the above-mentioned P
Forward voltage drop V of an N-junction diode.

Thus, a reference voltage generating device can be obtained that has a temperature dependence that is one order of magnitude smaller than the temperature dependence of the threshold voltage Vth of the IGFET. Furthermore, the voltage obtained is determined by the energy gap Eg specific to the semiconductor; for example, in Si, it is approximately t at room temperature.
, 12 (V) almost independently of other factors, and it is possible to obtain a high reference voltage regardless of variations in manufacturing conditions and the like.

Now, an example will be explained based on which principle the voltage corresponding to the energy gap Eg of this semiconductor can be extracted.

The state of energy levels when a semiconductor is doped with donor and acceptor impurities is well known. In particular, what we have focused on in this invention is that the Fermi energies of N-type and P-type semiconductors are located at 2 points toward the conduction band and valence band, respectively, based on the Fermi energy level El of the intrinsic semiconductor. It is a physical property of being separated. The higher the concentration of acceptor and donor impurities, the higher the Fermi level El of the intrinsic semiconductor.
The Fermi level Ef of the P-type semiconductor tends to be further away from
'p approaches the upper limit level Ev of the valence band, and the 7-luminium level Efn of the N-type semiconductor approaches the lower limit level Ec of the conduction band, and the difference between both Fermi levels (Efn - Ef, ) If it is, this will be closer to the energy gap Eg of the semiconductor, and its temperature dependence will also be closer to that of the energy gap Eg. The same is true for the Fermi level difference (Efn-El) and (Ei-E4.) between a P-type semiconductor and an intrinsic semiconductor, and between an N-type semiconductor and an intrinsic semiconductor, but in this case, the absolute value is E g/2 approach. Hereinafter, the difference from the intrinsic semiconductor will be omitted because it is half the difference between P type and N type. As will be described in detail later, the higher the impurity concentration, the smaller the temperature dependence (Efn-Efp), and it is preferable to keep the concentration as close to the saturation concentration as possible.

The Fermi level Efn, T2fp is related not only to the concentration of donor and acceptor impurities, but also to the donor and acceptor levels Ed and E&, and this level Ed l
Ba varies depending on the impurity material. Levels Ed and E
, are closer to the conduction band and the valence band, respectively, the closer the Fermi levels Efd and Efa are to the respective ones. In other words, the donor and acceptor impurity levels Ed, E
The shallower f is, the closer the Fermi level difference (Efn-Ef,) is to the semiconductor energy gap E2.

Donor and acceptor impurity levels Ed.

The closer Ef is to the Fermi level Ei of the intrinsic semiconductor, that is, the deeper it is, the farther the Fermi level difference (Efn-Efp) is from the energy gap E of the semiconductor. However, this does not necessarily mean that the temperature dependence becomes worse, but the difference in Fermi units (Ef
This means that the absolute value of n-EfP) becomes small. Therefore, the difference in the 7-Eluminum level (Efn-Efp) and the difference in work function are unique to materials such as semiconductor materials and impurity materials. It can serve as a reference voltage source that is different from the gap Eg. In other words, the Fermi unit difference (Bfn-El,) by itself has less temperature dependence than the threshold voltage Vth of the PN junction forward voltage drop VFJPIGFET, and is less dependent on manufacturing variations than the reference voltage K. Extracting the Fermi level difference ("fn - Ef,") using an impurity material that can serve as a source and exhibits shallow donor and acceptor levels Ed, gf produces a voltage that is approximately close to the energy gap Eg of the semiconductor. On the other hand, when it comes to setting the voltage value to be obtained, if the purpose is to obtain a relatively large reference voltage equivalent to the energy gap of a semiconductor, shallow When an impurity exhibiting a deep level is used and the purpose is to obtain a relatively small reference voltage, an impurity exhibiting a deep level may be used.

Variant example of impurity material selection: Fermi level Ef, donor level Ed, acceptor level E
c, donor concentration Nd, acceptor concentration N& and temperature T
The relationship between Ge, Sl and G will be explained in more detail with reference to FIGS. 2 and 3.
In order to understand what level each impurity exhibits in the aAs semiconductor and how to utilize these impurities in the present invention, the data on page 30 of the above-mentioned document are used as Figure 4. Restate and add explanation.

Figures 3(a), (b) and (c) are, respectively,
It is a diagram showing the energy distribution of various impurities with respect to G e +Si and GaAs, and the numbers in each diagram are the lowest level of the conduction band Ec for the level located above the center Ei of the gap represented by the broken line. For the lower level, the energy difference from the lowest level E of the valence band (E
, -Ev), and their units are all (eV).

Therefore, impurity materials indicated by small numbers in the figure indicate that their levels are close to the lowest level Ec of the conduction band or the highest level Ev of the valence band, and are close to the energy gap Eg. It is suitable as an impurity to obtain voltage. For example, for St, which is currently being used extensively, The smallest level difference is about 6% or less of the energy gap Eg of Sl.

The Fermi level difference (Efd - Efa) between N-type Sl and P-type St using these impurities is equal to the energy gap Eg of Sl, if the temperature change from 0°K is ignored.
It is about 94% to 97% of Eg, which is a value equal to Eg. In addition, the next smallest level difference (Ee-Ed) of the above impurities
, (Ka-Ev), the donor impurity is S(approximately 1 of Eg)
6%), and the acceptor impurity is In (approximately 14% of Eg).
), and N-type Sl and P-type Si using each impurity
The Fermi unit difference (Efd - Efm) is about 0.85Eg at O'K, and the deviation from the energy gap Eg of Sl is about 15%, and the deviation becomes extremely large due to the impurities mentioned above. I understand.

Therefore, the energy gap EgK of S, t, is the impurity material of P type and N type St to obtain approximately equal voltage, and 1,000 is LitSb + P + one donor impurity selected from the group of A, s and Bi and B ,A-
One acceptor impurity selected from the group 6 and Ga is preferred; other impurities may be suitable for the purpose of obtaining voltages significantly smaller than the energy gap Eg of Si.

Next, regarding the Fermi level difference (Efn-Efp),
The physical properties will be explained with reference to FIG. Figure 2 is a diagram showing the energy unit of semiconductors, with (a) and (
Figure b) shows an energy level model of an N-type semiconductor and its temperature characteristics, and Figures (e) and (d) each show an energy level model of a P-type semiconductor and its temperature characteristics.

Carriers in the semiconductor are electrons nd generated by ionization of the donor impurity Nd, electrons excited from the valence band, and holes T. When the impurity Nd is sufficiently large, the excited electrons and holes can be ignored, and the electron vln becomes n+nd (1). nd is the probability of donor level busy trapping,
Further, n is determined from the number of electrons present in the conduction band, and is determined by the number of electrons present in the conduction band. Here, h blank constant, f? ;Effective mass of electron From this, , and .

Here, the first term of equation (5) can be ignored since the 7 Hermi level is located close to Ec.

This equation shows that when the temperature is low, the temperature dependence is approximately equal to the temperature characteristic of Ec.

Margin below However, when the temperature becomes high enough, the number of pairs of electrons and holes excited from the valence band becomes large, the influence of impurities decreases, and the Fermi level approaches the level E1 of an intrinsic semiconductor. Drop. The above relationship is shown in Figure 2).

In the case of a P-type semiconductor containing only acceptor impurities as shown in Figure 2(C), the Fermi level is
It is located approximately between the top of the low electron band and the acceptor level, and as the temperature increases, it approaches the Fermi level of an intrinsic semiconductor.

This relationship is shown in FIG. 2(d).

Relationship - Specific Example Having explained the physical properties of the relationship between the temperature dependence of the Fermi levels Efp and Efn and the impurity concentration, next we will use the Si semiconductor, which is currently in large quantities and in practical use, as a specific example, based on the above-mentioned book. Referring to the data on page 37, the Fermi level difference (Efn-Efp) and its temperature dependence in practical use will be explained.

The data is reproduced in Figure 3.

In the normal Si semiconductor integrated circuit manufacturing process, boron B and phosphorus P are mostly used as impurity materials, and in areas where the impurity concentration is high, 10" (atoms
/cm'), but the impurity concentration is lowered by 2
Even if it is an order of magnitude lower than 10" (atoms/cm3), the difference in Fermi level (Efn "fp) between an N-type semiconductor and a P-type semiconductor is 300' as can be read from Figure 3.
It is 0.5-(-0,5)-1,0 (eV) at K, which is a value relatively close to the energy gap Eg: 1.1 eV at the same temperature. The change with temperature is from 200'K to 400°K <-c:=o'C= 130c
) (7) Range Te, approximately 1.04Ce■) to 0.86(
eV), the rate of change is 0.9 (mV/C). This is about 1/3 of the previously mentioned rate of change of the threshold voltage Vth of the IGFET and the forward drop voltage of the diode with respect to temperature, which is 2 to 3 mV/C.
is a small value.

If the impurity concentration is 10” cm-m or more, the silicon energy gap (E g ) S i =1.1 (
V ), and the rate of change in temperature is approximately 0.2 m
V/C, which is a sufficiently small value.

Therefore, if the impurity concentration is about 10'6 cm"'s or more, it is possible to obtain a temperature dependence that is at least 1/2 to 1/3 smaller than that of the conventional method, and more preferably 1010 C.
, -3 or more (improved to about 1710), and most preferably saturation concentration.

In the principle and example of extracting the Fermi level difference, this Fermi level difference (Efn-EfI))ν(Efn-J),
(J-Elp) On what principle can a voltage corresponding to K be extracted? An example is the case of two MOSFETs formed on the surface of the same semiconductor substrate and having semiconductor gate electrodes of four different conductivity types. Threshold voltage■t1.
It is to take advantage of the difference between A specific example will be explained below.

FIG. 5 shows a conceptual cross-sectional structure of each FET. For the sake of simplicity, hereafter, for the sake of simplicity, we will refer to a MOS transistor with a gate electrode of a P0 type semiconductor as a P+ gate MOS transistor, a MOS transistor with a gate electrode of an N0 type semiconductor as an N+ gate MO8, a MOS transistor with a gate electrode of an i type semiconductor as an i gate MO8. Let's say that. In the figure, the left half is a P+, i and N+ gate P-channel MOS transistor, and the right half is an N+, i and p 4-gate N-channel MO8) transistor.

MOSFETs (Qr) to (Q, ) in FIG.

The mutual threshold voltage differences between (Q4) to (Q.) are as shown in the table below.

Tables Figure 6 (a) e (b) to Figure 11 (a),
(1)) shows a plane pattern actually used in a circuit structure and a section A-A of the plane pattern for a P+ gate and an i gate.

N-gate each P-channel and N-channel MOS
) The transistor is shown together with its cross-sectional structure.

In each of the above figures, the P-type head regions of the source and drain are formed by diffusing impurities using polycrystalline Si as a mask. In order to ensure sufficient mask alignment between the mask for selectively diffusing P-type impurities and N-type impurities and the source and drain regions, P+ gate MOS and N+ The same impurities as the source and drain regions are diffused into both gate MO8. For example, in the P-channel MO8, boron, which is a P-type impurity, is diffused. In the center of the gate electrode, P
+ gate MOS has P type impurity, N+ gate MO8 has N
Type impurities are diffused.

The above figures 6, 7 and 8 show the P channel of P channel.
+ gate, i gate, N+ gate MO8 are shown in plan view and cross-sectional view, and FIGS.
A plan view and a cross-sectional view of the OS are shown.

In Figures 6 to 11, the same impurity diffusion regions as the source and drain regions of the gate, which were taken for self-alignment, were removed on the left and right sides (source side or drain side) during manufacturing due to mask alignment errors. In order to minimize the deviation (change) in the effective channel length of the MOS transistor due to biasing to one side, the rows of source and drain regions are arranged alternately, and overall the left half and right half are the channels. They are arranged line-symmetrically with respect to the direction. Therefore, even if misalignment of the mask alignment in the channel direction (left and right) changes the effective channel length of the FETs in each column, the P of each column connected in parallel
+ Goo) MO8i game) MOS, and N+ game) MOS
The average effective channel length of is almost constant as the deviations are canceled out as a whole.

FIG. 12 shows how P+GMOS and N+GMOS are constructed in a typical silicon gate CMOS manufacturing process.

In Figure 12(a), 101 is a specific resistance of 1Ωcm to 8
Ωcm N-type silicon semiconductor with a thermal oxide film 10 on top.
2 is grown to a thickness of approximately 400o^ to 16oooλ, and a window for diffusion is selectively opened using photoetching technology. Boron as a P-type impurity at 50KeV ~ 200Ke
10”-10” cm- with energy of V! Ions are implanted in a moderate amount, and then thermally diffused for about 20 hours between N channels.
- forming wells 103;

In FIG. 3), the thermal oxide film 102 is removed, a thermal oxide film 104 is formed with a thickness of about 1 μm to 2 μm, and the regions that will become the source, drain, and gate of the MOS transistor are removed by etching. Thereafter, a gate oxide film 105 of about 3008 to 1500 Å is formed. On top of that, polycrystalline 5i10
MO8) is grown to a thickness of about 2000^ to 6000^ and removed by etching leaving the gate part of the MO8) transistor.

In the same figure (C), an oxide film 107 is formed by vapor phase growth, and a region where P-type impurities are to be diffused is removed by photoetching. After that, 1020-10 1c, 1-
By diffusing boron, which becomes a P-type impurity at a high concentration of about 11,
The source and drain regions 108 of the channel MO8L run sister are formed, and at the same time, the gate electrode of the P-type semiconductor is formed.

In FIG. 1D, an oxide film 109 is formed by vapor phase growth as before, and the region where the N-type impurity is to be diffused is removed by photoetching. After that, 1020~l Q
! Phosphorus serving as an N-type impurity at a high concentration of I Cm-a is diffused to form the source and drain regions 110 of the N-channel interlayer O8) run sister, and at the same time, the gate electrode of the N-type semiconductor is formed.

Next, the oxide film 109 is removed and 4000
An oxide film of about A to 8000 A is formed, and the electrode lead portion is removed by photoetching. Then metal (
A)) is vapor-deposited and an electrode wiring portion is formed using photo-etching technology.

Next, it is covered with an oxide film of 1 μm to 2 μm by vapor phase growth.

Here, in FIG. 12(d), Q,,Q, are general C
MO8 that constitutes a MOS inverter, Q, -Qt
is a P+ gate for generating reference voltage.

N+ Gege MO8.

Figures 13(a) to d) show P-channel type P+
Fig. 4 shows cross sections in the manufacturing process of the gate MO8 and the gate MO8. In this example, up to (C) in the same figure is the 12th
Same as up to figure (C), but in figure (d) MO
S F E T Qt ') Oxide film on the gate 1o96
Diffuse N-type impurities without removing them.

FIGS. 14(a) to 14d) show cross sections suitable for the manufacturing process of N-channel type P+GEGA MO8 and N+GEGA MO8.

Figure 15 (a) to d) shows N□ channel type N+
It shows a cross section in the manufacturing process of GeGe MO8 and iGate MO8.

Next, the threshold voltage of a MOS transistor using a semiconductor as a gate electrode will be explained with reference to FIG. First, for the case of MO8 (P+game), see the 16th
The energy band diagram in Figure (a) shows that φM φS.

However, here ■. 1 Potential difference between semiconductor substrate and gate electrode (P + semiconductor) X - Electron affinity + Eg r Energy gap φ8 Surface potential of IN type semiconductor substrate φFp φF I Fermi potential of the N-type semiconductor substrate q based on the Fermi potential of the intrinsic semiconductor Unit charge of an electron Vo e Potential difference applied to the insulator Eo i Lower limit of the energy level of the conduction band Ev1 Upper limit of the energy level of the valence band EH + Fermi level of the intrinsic semiconductor In equation (7), if the work function of the gate electrode is expressed as a potential and is φMP0, and the work function of the semiconductor is similarly denoted as φsi, then q Therefore, v, = -vG + φwoo φsi - φ8 ・・・・・・・・・
・・・・・・・・・・・・Ql.

Also, from the charge relationship in Figure 16, etc., -C0X-Vo +Qss+Q1 +Qa =0 =Q
I). Here, COX + Capacity of insulator per unit area Qss g Fixed charge in insulator QB 1 Fixed charge due to ionization of impurities in semiconductor substrate Qi + Carrier al formed as a channel, (1 m) from -COX (-VG + φMF + −φS−φsrf )・
...aノ+Qs s +Q4 +QB -0...
・・・・・・・・・・・・・・・・・・ α side.

Gate voltage V when channel Q is formed.

is the threshold voltage, so if the P gate MO8 threshold voltage is Vthp+, then φ8-2φ.

Similarly, in the N+GEG MO8) transistor, the difference is only in the work function φMN+ of the gate electrode, which is q. Therefore, its threshold voltage VthN+ is now φ
8-2φ.

becomes.

The difference in threshold voltage between P+ gate MO8 and N+ gate MO8, Vthp+'thN+, is vthp+Vth
N+=φMP+-φMN+=φFP+-φFN+...
46), which is the difference in the Fermi potential of the semiconductors that make up the gate electrode. This is because comparing (a) and (C) in Figure 16, the gate voltage when the charge distribution is the same is the difference in work function of the gate electrode, and the difference in Fermi level. Easy to understand.

From the above, it was found that a voltage approximately equal to the energy and gap Eg can be extracted as the difference in threshold voltage between the P+ gate MO8 and the N+ gate MO8. The energy gap Eg is also determined by the difference between the threshold voltage of the MOS (hereinafter referred to as i-gate MO8) and the threshold voltage of the P+ gate MO8 or N+ gate MOS.
voltage can be extracted.

iGame) If the threshold voltage of MOS is vthi,
Since the 7-luminium level of an intrinsic semiconductor is 0 (because it is based on the 7-luminium level of an intrinsic semiconductor), the i-gate MO8
The difference in the threshold voltage between the i-gate MO8 and the N+ gate MO8 is 1Vthi'tbN+l=lφFN+ 01+ Eg-
It is easy to see that the voltage is exactly half the energy gap Eg.

The voltage obtained by the difference in threshold voltage between the i-gate MO8 and the P+ gate or N-1-gate MOS is approximately 0.55V, which is suitable for a low reference voltage source. In addition, since the step of doping the gate electrode with impurities can be performed in one step, it is very useful in that a highly accurate reference voltage source can be easily obtained even in the manufacturing process of a single channel MOS.

Next, we will explain the process for an N-channel MO8 semiconductor integrated circuit using the cross sections shown in FIGS. 17(a) to (e) (1).
A semiconductor substrate 101 having a specific resistance of 8 to 20 Ωcm is prepared, and a thermal oxide film 103 with a thickness of 1 μm is formed on the surface of this substrate.

(2) The thermal oxide film is selectively etched to expose the surface of the semiconductor substrate where the MISFET is to be formed.

(3) After bonding, a thickness of 750 mm is applied to the exposed semiconductor substrate surface.
Form a gate oxide film (Sift) 103 of ~100 OA (FIG. 17a) (4) Selectively etch the portion of the gate oxide film 103 that should be in direct contact with the polycrystalline silicon layer to form a direct contact hole 103a. Form. (Figure 17b
) (5) Oxide film 102, gate oxide film 103. Silicon is deposited on the entire main surface of the semiconductor substrate 101 having the contact hole 103a by chemical vapor deposition (CVD).
A polycrystalline silicon layer having a thickness of 3,000 to 500' OA is formed by depositing using the De-position method.

(6) Selectively etching polycrystalline silicon layer 104. (FIG. 17C) (7) The entire main surface of the semiconductor substrate 101 is coated with carbon by CVD method.
Deposit a V D SiO1 film to a thickness of 2000-3000A.

(8) The above-mentioned C
The V D SiO* film 105 is selectively left.

(Fig. 17d) (9) Using the polycrystalline silicon layer as a mask, the semiconductor substrate 10 is
Diffusion of phosphorus into the impurity concentration of 10” atoms/
The source and drain regions 106 of C1n3 are formed. At this time, impurities are also introduced into the polycrystalline silicon layer to form gate electrode 104b and direct contact 104.
c and a polycrystalline silicon wiring portion 104d. (
FIG. 17d) Ql The entire main surface of the semiconductor substrate 101 K P S G (
Phosph.

5ilicate Glass) film 107 to 7000
Form to a thickness of ~9000 mm.

(II) After printing, A-type film is deposited on the entire main surface of the single-conductor substrate 101 to form an A4 film 108 with a thickness of 1 ms.

α2 Above A! The film is selectively etched to form wiring area 1.
08 is formed. (Fig. 17e) The circuit explained below is based on the above-mentioned difference in the 7-luminium level (Ef).
n-Efp) (Efn-EI), (Ei-Efp), but in general,
It can be applied as a reference voltage generator that uses a voltage based on the difference in Vth of FETs having different Vths as a reference voltage.

FIG. 18(b) shows a circuit that generates a voltage corresponding to the threshold voltage of a MOS transistor. TlyT is a so-called MOS in which the drain and gate are connected in common.
It constitutes a diode.

Engineering. is a constant current source, Tr-T* is a different threshold voltage ■t
It is a MOSFET with transconductance β approximately equal to hl * Vlhz, and each drain voltage is set to V
l, V, then 1 o =, / (V'IVthl)''m-β(V
l Vthz)2 ・・・・・・・・・・・・・・・(
1? ), so Vt-Vthx + fπ sword...
aυVy −vth2 + m m++m+mm, and by taking the difference in drain voltage, the difference in threshold voltage can be extracted.

As a constant current source, you can use a sufficiently large resistor, and as long as it has the same characteristics, you can use a diffused resistor.

Polycrystalline Si resistor, resistor made by ion implantation,
MOS) resistors can be used.

In this circuit, as an example, N
By using the +gege MO8 and the P+ gate MOS, it is possible to extract the Fermi level difference (Efn - Efp) between the N-type semiconductor and the P-type semiconductor, which is approximately equal to the difference in threshold voltage.

FIGS. 19 and 20 are examples of circuits in which FETs having different threshold voltages are connected in series in the form of MOS diodes to extract the difference in threshold voltage. It is assumed that T1 has a threshold voltage ■thi t Tm and a key value voltage Vth2.

Under the conditions that the resistance R1 is sufficiently large compared to the impedance of T1, and the resistance R1 is sufficiently large compared to the impedance of T, VI Vy')vthl ・・・・・・・・・・・・
...... (to) V 1 + V (h2 ...
・・・・・・・・・・・・・・・C! Because of Xun, ■, ÷V
thl Vth2 ・・・・・・・・・・・・・・・
...(c).

In FIG. 21(a), a voltage corresponding to the threshold voltage is applied to both terminals of a capacitor, and the voltage held in the capacitor is extracted as a differential voltage. FIG. 21(b) shows the operation timing. The clock pulse φ turns on T,,T, to increase the L threshold voltage V, h1. of the capacitance C,KT,,T,. Charge the differential voltage of Vtbz.

After φ1 is cut off, turn on T by the clock φ,
Ground the node ■ of C1. At this time, since the differential voltage between the threshold voltages is held in CI, that potential is output as is to node (2). When used in a voltage detection circuit as described later, the potential at node (2) at this time can be used as it is as a reference voltage. However, in order to be able to use it in a more general form, the transmission gate (Ts, Ty) is turned on by the clock φ during the time when the clock φ is input, and the potential is taken into the capacitor C2. If the output is fully fed back to the negative phase input (-) of the operational amplifier 5 by a so-called voltage follower, the output will be in a state with sufficiently low internal impedance.
'r, e The difference in threshold voltage of Tt is obtained as a reference voltage.

FIG. 22 shows a reference voltage generating device that similarly utilizes the capacitor C2. T8 is turned on by clock φ1. At this time, it is in the off state due to T and beam ptsukφ. The potential of the node ■ is lower than the potential of the node ■ by the threshold voltage Vtht of T8.
The potential of node ■ is lower than the potential of node ■ by T,
is lowered by the threshold voltage Vth2, and the difference voltage between the two is charged across the capacitor C. Then, by φ, Tll
When T is turned off and T is turned on due to φ, a voltage difference between the threshold voltages is obtained at the node ■.

FIG. 23 shows an operational amplifier used in the circuit of FIG. 21. P+-Tt is a differential pair constituting a differential amplifier circuit, and T,,T.

is its active load. T, constitutes a constant current circuit together with a bias circuit formed by T, .

Tm and Ty are level O conversion and output buffer circuits with T as a constant current source load. Although the figure shows an example of the circuit configuration using C-MOS, it goes without saying that it can also be configured with a single channel MO8.

FIG. 24 schematically represents a general operational amplifier by taking only its differential part.
S) It is assumed that the transistors TI and T have different threshold voltages Vthl p Vth2, and other characteristics are the same. Also, (-), (
The symbols +) mean that the output is in opposite phase and in phase with the output, respectively.

If the input of T is V, and the input of T is Vt, then v,
Vthl -v, Vth2 "Mari L Vy = vth
t-vth2 ・・・・・・・・・・・・・・・・・・
- The output level changes after the condition (c) is reached.

An operational amplifier has an input offset equal to the difference between the threshold voltages, and if one of the inputs is connected to ground or the power supply, it can operate as a comparator using this offset voltage as the reference voltage. I can do it. Therefore, as shown in FIG. 24, by connecting the output to the (-) input terminal and grounding the +) input terminal, a difference in threshold voltage can be obtained at the output (out). In this case, in order to operate the operational amplifier, T must be in depletion mode. For example, T, P+ game) MOS, T, N+
When using Gege MO8, both MOSFETs
Ion implantation was performed under the same conditions in the channel section of
It may be a depression type.

In FIG. 25, the reference voltage can be arbitrarily set using the operational amplifier in FIG. 24. If the output is fed back to the (-) input through the voltage dividing means RIlyR11, and if the voltage dividing ratio is r, then the output voltage o will be as follows. The voltage dividing means us l R11 is preferably a linear resistance, but any resistance may be used as long as it has sufficiently uniform characteristics to an acceptable extent.

The circuits shown in FIGS. 24 and 25 are based on the use of a depletion type MO8, whereas the circuits shown in FIGS. 26 and 27 can also operate with an enhancement type MO8. Of course, it can also be of the Depledge Seal type.

The example in Figure 26 is similar to the example in Figure 24, in which the output is directly fed back to (to) the input, and the output V0 is the power supply voltage VD.
If D, then Vo = Vop (Vthx - ■thz) = 0°
°°゛°°1°°. In the circuit shown in Figures 24 and 25, it is necessary to put at least one of the differential pairs into the depletion mode, which may require an increase in the number of manufacturing steps depending on the case, but the difference voltage of Vth It can be taken out with reference to the ground potential.

Conversely, in the circuits shown in Figures 26 and 27, the reference for the resulting differential voltage is the power supply voltage that is not the ground potential, but there are no particular conditions for the operating mode of the FET.

Deciding which circuit type to adopt depends on its merits and demerits.

The example in FIG. 27 is the same as the example in FIG.
The output is fed back to the (-) input through s, and the output is .

Next, regarding the application of the reference voltage generator described above, the circuit, the structure of the IC chip, etc. will be explained.

Control of Threshold Voltage The threshold voltage (Vth) of the MOSFET, which is a local element in the MO8 integrated circuit, is an important parameter that determines the characteristics of the LSI. This Vth is subject to large variations due to manufacturing processes and changes due to temperature.
control is a difficult point in MO8LSI manufacturing.

On the other hand, in the MOS memory shown as an example in FIG. 28, a bias voltage is applied to the substrate to reduce parasitic capacitance. A substrate bias generation circuit is used to obtain this bias voltage. The substrate bias generation circuit has the configuration shown in FIG. 29. Conventional substrate bias generation circuits consist only of an oscillation section and a waveform shaping section, and generally do not perform two-weed packing based on Vth. For this reason, differences in oscillation frequency and waveform shaping ability occur due to manufacturing variations and temperature, making it impossible to obtain a stable back bias voltage VBB and causing large fluctuations in Vth.

In the present invention, a comparator based on the work function difference of the gate electrodes described above is used in the substrate bias generation circuit to control vth to a constant voltage.

Vth changes depending on the substrate bias and is expressed by the following formula.

vth-VthO1K (2φF+IVBI11 2φF
) Here, VthO is V, vth of B-OV, K is the substrate effect constant, and φ is the Fermi level. - Therefore, Vth can be controlled by changing the substrate bias v0. In FIG. 29, the oscillation circuit section uses a ring onlator. This oscillation circuit may be replaced by another oscillation circuit. The waveform shaping section has two M
It consists of OS diodes Qt pQ and six layers of capacitors, and has the function of drawing the charge of VIIB to GND by a pumping action. Due to this pump action, ■. is drawn to the negative voltage, but the maximum voltage of IVBBI ■. One is,
It is determined at which pumping action the pullout voltage and substrate leakage current become stable. ■As long as the oscillation circuit is operating. The stable point ■BBM is maintained, but when oscillation stops, the charge on the substrate leaks due to substrate leakage current and approaches the GND level.

■. When Vth approaches the GND level, Vth decreases.

The comparator section shown in FIG. 29 utilizes the aforementioned work function difference between the gate electrodes, and an example in an N-channel process is shown in FIG. 30. In FIG. 30, Qi uses an intrinsic level gate MO8, and Q uses an N gate open O8. Moreover, these are depression type MO8. Therefore, the 8g comparator is inverted when -0.55V (1') [pressure is input to the single force section. The Vth sensing section in FIG. 29 consists of one resistor and a MOS FETQs.

Here, the resistance may be either a polysilicon resistance diffusion layer resistance or an MO8 resistance, but the resistance value is Q, Vth is 0.5
It is set so that when the voltage reaches 5V, the output becomes 0.55V. Now, when VBB is close to GND level <Ql, Vth is 0.55V or less, the comparator section-input terminal becomes 0.55V or less, the output of the comparator becomes 1'', and the oscillation circuit continues to operate.■. ■!Vth increases as it approaches lBM, and when it exceeds 0.55V, the comparator output becomes "0"E, oscillation stops, and VBB approaches GND level due to leakage.In other words, a feedback loop is formed, and the substrate bias Vth is controlled by the generation circuit.The voltage of 0.55V obtained by the comparator section becomes the minus energy gap, and as mentioned above, it does not change much with temperature, manufacturing variations, and power supply voltage, so Vth can be controlled extremely. It becomes possible to control with high precision, and an MO8LSI with a wide temperature margin, manufacturing process margin, and power supply margin can be obtained.As will be described later, the memory cell shown in FIG. 32 has a high temperature margin in terms of process.

Since the intrinsic Lepergaer MO8 can be obtained in exactly the same process as that used to obtain the resistance R, it can be easily realized using a conventional process.

In the level shift circuit MO8LSI, when a 5■ power supply is used as a power supply and a signal from a TTL logic circuit is used as an input, 2. OV and low level are O and SV signals. When converting this TTL signal to a MOS level, conventionally the ratio of the input inverter is taken and converted to the MOS level, but there is a problem that the input level margin becomes small due to Vth variations and temperature changes.

An example of a TTL-)MO8 conversion circuit using the reference voltage generation circuit using the work function difference of the gate electrodes described above will be shown. FIG. 32 shows a specific example in which this method is used in an address buffer circuit of a MOS memory.

The reference voltage 1 is set as Vref by the circuit shown in FIG.
．． Generates 4v. Using the differential amplifier shown in FIG. 33 as an amplifier, an input buffer with an input logic Vth of 1.4■ is created. This method provides a TTL→MO8 conversion circuit.

Alternatively, the path shown in FIG. 23 may be used in the amplifier, and Vref, that is, the input voltage (2) in FIG. In this case, Tt and Ty are depression type MO
8 is used.

FIG. 34 shows an attempt to keep the logic threshold of a logic circuit such as an inverter constant against changes in the power supply voltage used, the threshold voltage of MOS transistors, temperature, etc.

Inno (-Y1゜Q4) composed of Q,,Q,tQs
- The inverter 2 composed of Q- and Q- each has MO8QI and Q4 for logic threshold world control.

Q, ,Q, ,Q, are configured to be similar to inverter 1 and inverter 2 (the MOS pattern size ratios are the same), and the input and output of the inverter are combined to form exactly Logic threshold voltages are now available.

CMP1 is a comparison circuit having the reference voltage described above as an offset of the differential circuit. CMP1 compares this logic threshold with its internal reference voltage, and controls the gate voltage of Q+ so that the difference between the two becomes approximately zero.

In other words, if the logic threshold > the reference voltage, the CMPI output will be high level and Q.

The equivalent resistance of is increased, which acts to lower the logic threshold. In the case of logic threshold (reference voltage), the opposite is true, and an equilibrium state occurs when both are equal.

The gate voltage of QI=Q4 is common to the gate voltage of Q, and the former and latter have a similar relationship, so that the inverter 1. The logic threshold of inverter 2 is equal to the reference voltage, resulting in very stable inverter characteristics.

As mentioned at the beginning, this does not necessarily apply only to inverters;
It can be similarly applied to other logic circuits such as NAND and NOR.

It can be easily applied to a logic circuit such as a normal single-channel inverter as well as a CMOS configuration.

These circuits are particularly useful as input interface circuits that can reliably digitally process signals even when the range of input level and logic amplitude is narrow.

The voltage detector shown in Fig. 35 adds the reference voltage from the reference voltage generator that uses the difference in Vth to one input of the comparator, adds the detected voltage to the other input, and calculates the detected voltage with respect to the reference voltage. This is a voltage detection circuit that can distinguish between high and low voltages.

In the example shown in FIG. 36, a reference voltage from a reference voltage generator using a difference in Vth is added to one input of the comparator, and the detected voltage is applied to the other input of the voltage dividing means R,,R,.

This is a voltage detection circuit that applies voltage divided by .

The voltage division ratio is r1, the reference voltage is Vref, and the detection level is ■se.
□5e, and the detection level v, en5e can be set arbitrarily by the partial pressure ratio.

The example in FIG. 37 uses an operational amplifier with an offset corresponding to the difference in Vth, and uses an off-set signal as described above.
This is a voltage detection circuit that uses a set voltage as a reference voltage. Again R,, , R,! is the same pressure dividing means as in the example of Fig. 36.

In the example of Figures 36, 36, and 37, if the voltage to be detected is the power supply voltage, it can be used as a battery checker in a system that uses a battery as a power source. A specific example in which the voltage detection circuit of FIG. 37 is applied to a battery φ checker for an electronic watch is shown in FIG. 44, and detailed explanation will be given later.

The example of the voltage regulator shown in FIG. 38 is applied to a stabilized power supply circuit. I would like to describe the reference voltage generation circuit first. and stabilize the output voltage.Any operational amplifier may be used as long as its characteristics are acceptable.

The example in Figure 39 uses bipolar transistors T instead of the MOS transistors T and o in the example in Figure 38.
This uses R1.

The example shown in FIG. 40 uses an operational amplifier having the offset voltage shown in the example shown in FIG. 'I'll
(Of course, MO8) may be a transistor, a bipolar transistor, or a junction field effect transistor.

Constant current device The example of FIG. 41 is a constant current circuit determined by the difference in threshold voltage between T and T.

T, , T, have the same transconductance β, and their threshold voltages are different Vth, ``th.'' If the resistance R2゜ is sufficiently high compared to the impedance of T, then the drain voltage of T1 ( - gate voltage) ■1 is ■tI□
, is almost equal to .

When Tt is in the saturation region, the current flowing through T.

teeth becomes.

In the example of FIG. 42, the voltage drop ■ due to the current I flowing through Ttt. This is a constant current circuit that compares utR□ with a reference voltage ref and controls the gate voltage of T so that both are always equal.

becomes.

Here, the reference voltage may be obtained by providing an operational amplifier with an offset, as in the previous example.

The example shown in FIG. 43 is a constant current circuit using the same transistor as Ts+s T33 and using a so-called current mirror circuit.

The example of an electronic watch shown in FIG. 44 is an example in which the battery checker shown in the example of FIG. 37 is applied to an electronic watch.

T, ,T, IT, ,~T4゜and R4, and R4,
constitutes a circuit that checks the voltage level of a mercury cell E, nominally 1.5V. The transistor pair of the differential part is composed of P gate/N channel-MOS, N+ gate/N channel-MO8T,,T, and the threshold voltage of both is 1.0 V to 1, which is the operating power supply range of the electronic watch. Ion implantation is performed in the channel part so that the voltage is within .5V.

The difference in threshold voltage, which is the reference voltage, is approximately 1. IV, and is adjusted by the resistance ratio of the resistance means R, , R, in order to adjust the level at which it is detected that the battery voltage has dropped to around 1.4V.

This battery checker operates intermittently by a clock signal φ obtained from the frequency divider circuit FD through the timing circuit TM in order to reduce the current consumption to a practically negligible level.

The output of the battery checker is a NAND gate game.
The logic level of this latch circuit output controls the timing circuit TM, which changes the drive output of the motor and changes the way the hands move, thereby adjusting the battery voltage. display a decline in The drop in battery voltage does not change the movement of the pointer, and it is also possible to display it by blinking an electro-optical element such as a liquid crystal or a light emitting diode.

In the same figure, O8C is a crystal oscillator circuit composed of a CMOS inverter and includes components crystal Xta1, capacitors CO, and CD outside the IC, and WS is a waveform shaping circuit that converts the oscillation output from a sine wave to a rectangular wave. , CM is an excitation coil for a step motor that drives the second hand, and BF, , BF is a buffer for driving the excitation coil CM by reversing its polarity every second, which is composed of a CMOS inverter.

All circuits within the IC are powered by a nominal 1.5-inch mercury cell E. Further, TM is the divided output of a plurality of different frequencies of the frequency dividing circuit FD and NA, , NA.

This is a timing pulse generation circuit that receives the control output of a latch configured as input and generates a pulse with an arbitrary period and pulse width. The IC is a Si game shown in Figure 6)C
This is a monolithic Si semiconductor chip for pointer type electronic wristwatches made using a MOS process.

The present invention has been described above based on various embodiments, but
The technical idea described herein is not limited to this, and may be applied to electronic devices for various other uses.

Next, a specific example will be described in which the reference voltage generating means according to the present invention is applied to a state setting circuit, an auto clear circuit, etc. of an electronic device.

FIG. 45 is a circuit diagram showing an example of a state setting circuit;
It is composed of MOSFETs. In the same figure, a
If the potential at point and point b is 0, when the power (-VDD) is turned on, M
Since O8FETT, T, are N-MOSFETs, they are both in the "ON" state, and points a and b are pulled to the power supply side (-VDD) at the same time as the power supply falls. At this time T3
The N-MOSFET uses the energy band difference of semiconductors.
About 3 times as much as that of (fiFIJ T+V111=
0.45V + TsVth = 1.25V), MO8FET71. is turned "OFF" first. MO8FBTT continues,
6ON" state, the point b is stable at the potential of -vDD and the point a is stable at the potential of GND.

Also, with the power (-VDD) turned off, OV at point a.

If a charge remains at about iV at point b, VDD=Vth of MO8FETTs during power supply fall.
Until N, T is in 'OF F' state,
MO8FETT is in the ON state when DD=TIVthN, so even if point a is ov and point b is IV (or up to VthN of T) in the initial state, b is in the stable state.
The point is ■DD, and the point a is OV. Furthermore, since this circuit is entirely composed of E-MOSFETs, current consumption in a stable state is almost zero.

FIG. 46 is a circuit diagram showing an example of a conventionally proposed state setting circuit. In the same figure, in order to increase the stability of the latch circuit,
OSFET is inserted. With this D-MOSFET, when the power (-VDD) is turned on, point a always falls at the same time as the power supply, and point b does not turn on unless the power falls to Vth of the MO8FET, so in a stable state, point b is VDIMa. The point becomes 0■. However, in this circuit, the point a and V
Since a D-MOSFET is used between the DD and the DD, the voltage at the point a A VDD + point b 0V (RES
ET) state, P-MO8FETT.

turns ON'', and a DC path is created between T and T, resulting in a large current consumption.On the other hand, the state setting circuit of the present invention as shown in FIG. Since it only needs to be extremely small, it is possible to provide an effective state setting means.

Next, a voltage regulator according to the present invention and an example of its application will be explained.

FIG. 47 shows a voltage regulator according to the present invention;
Figure 8 shows its characteristic diagram.

The comparison type voltage regulator shown in Fig. 47 has a similar configuration to a known one, but differs from a normal voltage comparator in that the voltage comparator CP is asymmetrical in voltage level when viewed from both the plus and minus input terminals. ing. In other words,
This voltage comparator is not balanced when the voltage levels of both the positive and negative inputs are equal, but is balanced when a predetermined high input voltage (in absolute value) is applied to the negative side. In other words, the positive and negative input levels of this voltage comparator have an offset with respect to the balance point.

° According to such a voltage regulator, the input voltage V
If in is high, the output voltage ■. ut depends on the reference voltage ref, and a large difference between Ivout and 'in' is taken, but if the input voltage io is low, then . The old one depends exclusively on ■in, and the difference l'V'-Voutl is made small. Regarding the input voltage Vin, the change point P of both n is vt
n≧V, (V+ is the regulator load/
(minimum operating voltage).

According to the voltage regulator configured in this way, when the input voltage ■in is high, the minimum operating voltage ■,
The output voltage ■ is higher than the input voltage ■in. u
Since it is operated at t, power consumption is reduced while operation is guaranteed. Also, when the input voltage ■in is low, the load/is the output voltage ■ which is approximately the same as the input voltage ■in or slightly smaller than it. Since it is operated at UT, the minimum operating voltage V for the input voltage IN of the load / is guaranteed, and for a high input voltage IN, the output voltage V is set to a voltage matching the load / IN. This voltage regulator has low power consumption and wide input voltage range for the load/load.
can have a width of

These effects will be explained in detail using the graph of FIG. 48 in comparison with a voltage comparator regulator having no offset.

In the same figure, the horizontal axis is the input voltage vin, and the vertical axis is the output
t and reference voltage ref. Curve a is ■i
■ Equal to n. In other words, it shows a hypothetical curve when the load / is operated directly at the input voltage ■io without using a voltage regirator.

Curve C shows a general reference voltage ref1, which is a normal reference voltage generation circuit. (The threshold voltage Vth of GENFET, the current amplification coefficient 13 mutual conductance gnl,
Alternatively, since the forward and reverse voltage drops of the PN junction ■F, ■2 and the current amplification factor hfe of the bipolar transistor are used, ■refGEN's output voltage ■ref is its power supply voltage ■
Depends on in (■ref”” f (Vin)).

When such a reference voltage ref1 is used as the reference voltage of the voltage comparator circuit CP, and the offset as described above is not provided in the comparator circuit CP, the output voltage ■. ut
is equal to the reference voltage vref, which matches the curve fiIC'
1" 1, and the reference voltage ref1 is the input voltage V.
Therefore, the output voltage chamber nVout is lower than the input voltage ■in in any range. As a result, the output voltage V. When ut becomes equal to the minimum operating voltage V of the load / (point R), the input ■, pressure ■i
n becomes Vt ('Vt > Vt). Therefore, the possible usable range of the load/input voltage v1n is IV2-V
, + will cause a loss.

In order to reduce this loss, in the voltage regirator shown in Fig. 47, a comparator C
Configure P.

Also, as a reference voltage, use a virtual reference voltage ■. [Reference voltage smaller than 1 and having similar characteristics ■ref2 (curve d)
Using
The values of Vref2 and Δ”of f are set to be equal to fl, that is, to match the target operating point S.

According to such a configuration, the voltage comparator C'P has vou
The input voltage ■io that is balanced under the condition of 1=■ref2+Δ■off and satisfies this equilibrium condition is Vin'≠vo
Since it is U1, this occurs only when vin total ■ref2+Δvoff.

When the input voltage ■in is smaller than (■refz+Δ■off), the output voltage ■io is also smaller than that, so the comparator CP outputs the voltage V. However, this feedback control is limited when ut is made equal to the input voltage vin (because Vout<Vin).

Therefore, the output voltage) ball v. ut is V r II - V r
ef 2+Δ■off is the inflection point (P), and when the input voltage Vio is higher than the inflection point P, ref2+Δ■o
ff (curve b+), and when vlo is lower than that, the input voltage is approximately ■in (curve-a2)
is made equal to

If this inflection point P is equal to or higher than the lowest operating chamber and pressure L (point Q) with respect to the input pressure Vin (on the horizontal axis), the above-mentioned loss can be avoided.

This is the curve f3! due to the curve ΔVoff. This is because the curve has an intersection with the curve a, and such an effect cannot be obtained when the curve Ml does not have an intersection with the curve a.

tx, +6, the FET in Figure 47 acts as a source follower (depression mode of the N-channel FET).
Since it is an ET, Vout-Vin is possible, and there is no loss in the threshold voltage Vth. Therefore, this is effective when the input voltage ■in is small.

However, this does not negate the use of enhancement mode source follower FETs.
The input voltage is large and Vth loss is not a serious problem,
This is extremely effective when it is difficult to employ a depression mode FET manufacturing process. In this case, the lower output voltage■. The song that determines ut (below the change point P) &!
a, (■out-■1n) is only shifted downward by Vth (Vout""'in-■th), and the output voltage is ■. It is still possible to give ut the effect described above.

Further, the N-channel FET in the figure can be replaced with a P-channel FET, and in this case, the P-channel #FET functions as a source grounding (therefore, there is no Vth loss described above).

There is no essential difference whether a source-grounded or source-follower type is used as a control FET, but when a source-grounded type is used, special consideration must be given to the loss of threshold voltage Vth, such as when using a depletion mode FET. Not necessary. In addition, when the source follower is used, this FET is This is useful because it works as a voltage follower. In other words, if the mutual conductance gm of this FET is sufficiently high, the output voltage is uniquely determined by the gate voltage.

It is also possible to use a bipolar transistor as the control transistor.

Offsela) V. Although it is not necessarily denied that ff is a function of the input voltage ■in, it is desirable that it be constant with respect to vin in setting the inflection point P.

Also, if a reference voltage having the same fluctuation factors as the load/ is used as the reference voltage ref2, the output voltage will be 1 depending on the characteristics of the load Z. I can get ut so this is 1
This is convenient. In that case, if ref2 is set to the lowest voltage for operating the load/, Δvoff can be used as a constant margin means.

The configuration that provides the offset Δvoff and its applied circuit will be described later, but here we will explain another method of providing the output voltage ■out with an inflection point using the circuit diagram in Figure 49 and the graph in Figure 50. .

In the following explanation and the graph of FIG. 50, all voltage values are absolute values.

In FIG. 49, Q+oy is a control transistor consisting of an N-channel depression mode FET. Q+ol, Qtot, and Q104 e Q+oa constitute a current mirror circuit, and Q,. FETQ, whose drain current is approximately equal to that of No. 3, is diode-grounded. 4 and Q+o*. Diode-connected P-channel FET QI04, N-channel FET Q+. The source-drain voltage drop VD8 of , is high impedance load Q1゜7, QI
Almost each threshold voltage Vthp,
■【hn.

Therefore, Vthp and (vin −vthn) are applied to both the positive and negative input terminals of the comparator CP, respectively.
IR pressure is applied (Figure 50, song 1Md, b).

Comparator CP has no offset and is therefore balanced when both inputs are equal. Therefore, the equilibrium condition is (vou
t - vthn ) = ■thn - i.e. ■. ut-
vthp+■thn. ■From the condition of jn≧Vout.

Output voltage V. ut is limited by K when ViiVthp+vthn (vthp+vthn), and vin4v
When thp+Vthn, it becomes approximately equal to vffin.

Therefore, when the load/ is composed of a CMO 8, its operating lower limit voltage is normally (Vthp+vthn), so the output voltage vout can compensate for it.

Note that the threshold voltage taken out by the MOS diode circuit is close to the original threshold voltage, but not equal, and follows its drain current.

Output voltage V at equilibrium point. Of course, the old one was originally σγ(VB, p+v
It is better to make each MOS diode Q+o+, Ql larger than thn). , to reduce the current flowing through FETQ,. It is better to keep the mutual conductance of 3 small.

Also, since the near threshold voltage extracted by the MOS diode is based on the assumption that drain current flows, the circuit should be configured so that current flows through both diodes even if the input voltage (in) becomes low. There must be.

Next, an example in which the voltage regulator shown in FIG. 49 is applied to an electronic watch will be explained using FIG. 51.

In FIG. 51, O20 is a crystal oscillator, WS is a waveform shaping circuit that converts the sine wave oscillation output into a rectangular wave, FD is a frequency dividing circuit, and TM is a timing diagram for creating a pulse with a predetermined period and width from the branch output. Pulse generation circuit, LF is a level shift circuit that converts a low level signal to a high level signal, BC is a battery life detector, VC is a voltage comparator, VR is a voltage regulator that uses it, and H is a hold circuit. ,
DT is an oscillation state detector, and LM is an excitation coil for a step motor that drives the second hand.

The detector DT detects the oscillation of O20 through the frequency divider FD and the timing circuit TM, and when it oscillates, operates the voltage regulator VR to output the oscillators O8C and WS,
Lower the operating power supply voltage of FD, TM, etc. from 1.5■.

At the moment when battery E is inserted, the input node of inverter I is discharge resistor R. 4, it is at ground potential (logic "0'"), so N channel FET Qvo+ is turned O.
Set to N state and set the output of the regirator to 1.5V of the battery voltage.
Make it. At this time, Q2os is also turned on, and FETQ2o
The gate node of t is charged (this is then F E
T Q. This is to make the negative feedback loop of the regulator active in advance so that the regulator output drops at the moment when the regulator 1 is switched OFF.

When the oscillator starts operating, other logic circuits are already in operation, so the timing circuit TM to the detector D
A pulse φ8 is supplied to T. exclusive OR circuit EX,
detects the appearance of this pulse φ8,
One input has 10 inverters for the other In, Is
, Ijf portion circuit CI++1 s A pulse φ8 delayed by RI03 is applied. Therefore, when the pulse φ8 is output, a pulse having a width corresponding to the delay time is generated at the output of the gate EXI. This pulse is FETQ, □,
It is integrated by a rectifier circuit consisting of an inverter I6 and a capacitor crow, and after a while after φ8 starts to appear, the N-channel FET Q. 1. Turn off Q2O3. Thereby, the regulator VR generates a predetermined output voltage (less than 1.5 V) only by its own control loop, contributing to low power consumption.

The operation of this regulator, particularly the voltage comparator VC, will be explained below. This comparator VC is based on the principle diagram in Fig. 47 and the principle diagram in Fig. 48.
Since it operates in the same way as the comparator CP explained in the characteristic diagram in the figure, a simple explanation will be given.

P-channel MO8FET Qzos, Q68. is the offset voltage V. To obtain ff, the gate of Qzoe is made QI in FIG. 5, P type as in FIG. 6, and Q,. The gate 7 is of Qt type in FIG. 5 and of ILN type as shown in FIG.

Therefore, Q. The threshold voltage Vth of , is Q 206
This is about 0.55V higher than the offset voltage (■) mentioned above. It becomes ff. N-channel FETQno- and P-channel FETQ. . are both diode-connected, so the positive input of the comparator VC, Q! . 7
Both phases of Vth (vthp+"thn) are applied to the gates of , and this becomes the voltage of Vrefz shown by curve d in FIGS. 48 and 50.

Therefore, the output voltage of voltage regulator VR is ■. ut is v
out=■thp+”thn+Δ■of f (■1n
kvthp +vthn+Δvoff).

When the input voltage E V i is low, V as described above. u
t=■in.

This comparator uses a timing signal φ,
Operating time is limited by Of course the reference voltage ■r
The circuit that obtains efi is also difficult, so the reference voltage
Capacitor CIO2 is also connected to Q to hold the voltage of ef2. , to hold the gate-1 voltage of capacitor CI0! is added separately from parasitic capacitance such as gate capacitance. The capacitors C and o3 are used to prevent oscillation caused by a phase rotation caused by several FETs connected in series in the feedback loop.

Since the battery checker BC has a configuration substantially similar to that shown in FIG. 44, a description thereof will be omitted.

In addition, the excitation coil driver IゎI3 at the output stage of the IC is
In order to increase the driving capacity, a 1.5V battery is used as a direct power source.

FIG. 52 shows a sequence in which the voltage regulator VR and battery checker Be according to the present invention are applied to a digital display electronic watch.

In the same figure, 08C, W8. Similar to the example shown in FIG. 51, the FD uses a voltage lower than 1.5V as a power source; logic circuits inside the IC such as the decoradar DC time correction circuit TC also use a low voltage as a power source.

DB has a voltage of 1.5v 3. This is a signal voltage circuit that boosts the voltage to Ov, and this voltage is used as a driving voltage for the liquid crystal display device DP (the driver is omitted).

/S is a level shift circuit, which converts a low signal level into a high DC current and supplies it to a circuit with a high power supply voltage.

In this way, normal logic circuits inside an IC that operate at a low operating voltage require a low operating power supply, while display drivers, etc. that require a high operating voltage at the input/output interface of the IC, use a high operating power supply to reduce power consumption. It is effective for electrification and expanding the range of power sources used.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the energy gap Eg of GaAs, Si and Ge semiconductors and its temperature dependence. Second
The figure shows the band structure and Fermi level Ef of a semiconductor.
C) and (d) are diagrams showing the band structure and Fermi level of a P-type semiconductor, respectively. FIG. 3 is a diagram showing the temperature characteristics of the Fermi level of N-type and P-type 8i with impurity concentration as a parameter. Figure 4(a). (b) and (C1 are Ge, Si and Ga, respectively)
FIG. 2 is a diagram showing the distribution of energy levels of an As semiconductor and various donor and acceptor impurities. Figure 5 shows the Fermi level difference (E
P+ which can be used to retrieve fn −Efp )
The cross-sectional structure of the gate and N+Dag-MOSFET is schematically shown, with the left half showing the P-channel FET and the right half showing the N-channel FET. Figures 6(a) and (b) are P+gate Pchi, yy, respectively.
Figure 7 (8) meb) shows the plan view and cross-sectional view of the /i Gege P-channel MO8FET, and Figure 8 (a) and (b) show the N+ Gege P-channel MO8FET. The plan view and sectional view of
), (bl is N+ Gege N channel MO8FET
Figures 10(a) and 10(b) show the plan view and sectional view of i.
The plan view and cross-sectional view of the gate-N-channel O8FET are shown below.
Figure 11(a). (b) shows a plan view and a cross-sectional view of a P+gege N-channel MO8FET. Figures 12(a) to (d), Figures 13(a) to (d), Figures 14(a) to (d), and Figures 15(a) to (d) are
FIG. 6 is a cross-sectional view of the main steps when manufacturing complementary MOSs together. Figures 16(a) and 16(b) are respectively P+ type semiconductors.
Figures (C) and (d) are diagrams showing the energy and charge states of an N+ type semiconductor-insulator-N type semiconductor structure, respectively. be. Figure 17 (a) or e) is an N-channel MO8FE
It is sectional drawing in each manufacturing process of T. FIGS. 18(a) and 18(b) are diagrams showing the characteristics of a MOS diode circuit and its circuit for extracting the difference in Vth of two FETs having different threshold voltages t11. 19 and 20 each show an example of a reference voltage generation circuit that utilizes the difference in Vth, FIG. 21(a) shows an example of another reference voltage generation circuit, and FIG. The timing signal waveform is shown. 22 to 27 are based on still other embodiments (reference voltage generation circuits are shown). FIG. 28 is a block diagram of a semiconductor memory, and FIG. Detailed circuit diagrams are shown. Figures 30, 31, 32, and 33 show the circuit diagrams of the comparator circuit, memory cell circuit, address buffer circuit, and differential amplifier, respectively. Figure 34 shows the logic circuit. Figures 35 to 37 show examples in which the reference voltage generation circuit is applied to a voltage detection circuit, Figures 38 to 40 show examples in which it is applied to a voltage regulator, and Figure 41 shows the circuit diagrams of the circuits. - Figure 43 shows an example applied to a constant current circuit, and Figure 44 shows an example applied to a battery checker for an electronic wristwatch. Figures 45 and 46 show the state setting of the present invention and the conventional one, respectively. 47 is a circuit diagram for explaining an example of a voltage regulator according to the present invention, and FIG. 48 is an electrical characteristic diagram for explaining its operation. FIG. Fig. 49 is a circuit diagram for explaining another example of the voltage regulator according to the present invention, and Fig. 50 is an electrical characteristic diagram for explaining its operation. This is a circuit diagram for explaining an example of application to an electronic watch, and FIG. 52 is a circuit system diagram for explaining an example of application to a digital display electronic watch. T...MOSFET, R...resistance , C... Capacitor, Xtal... Crystal resonator, O20... Crystal excavation circuit, WS... Sine wave - (form wave conversion waveform shaping circuit,
FD...Binary power counter multi-stage connection frequency divider circuit, TM...
Timing circuit, CM...excitation coil for the step motor for driving the second hand, BP...buffer for driving the CM, N
A...NAND game, IC...monolithic Si
Semiconductor integrated circuit chip, φ...clock pulse, E8
... Energy gap of semiconductor, Ev ... Upper limit level of valence band, EC ... Lower limit level of conduction band, E
i...Fermi level of intrinsic semiconductor, Efn p Ef
p...Fermi number 1 for N-type and P-type semiconductors, Ed,
Ea...donor, acceptor level. Figure 1 Figure 2 Figure 16 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Eaves Figure 33 Figure 37 Figure 34 Figure 35 Figure 36 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 46 Figure 45 Figure 47 Figure 48 °l-1

Claims (1)

[Claims] 1. A semiconductor integrated circuit device including a circuit to which a plurality of input signals are supplied, wherein the logic threshold voltage of the circuit is
First and second IGFETs having mutually different threshold voltages
A semiconductor integrated circuit device characterized by being set based on a threshold voltage difference between. 2. The above circuit is similar to the above 1. a reference voltage generator that forms a reference voltage based on the threshold voltage difference of the second IGFET; and a plurality of voltage comparison circuits to which an input signal is supplied at one input terminal voltage and the reference voltage is supplied to the other input terminal. A semiconductor integrated circuit device according to claim 1, characterized in that it has the following. 3. Above 1. 3. The semiconductor integrated circuit device according to claim 2, wherein the threshold voltage difference between the second IGFETs is based on the Fermi level difference between their gate electrodes. 4. Above 1. 4. The semiconductor integrated circuit device according to claim 3, wherein each gate electrode of the second IGFET has a semiconductor layer portion having a different conductivity type. 5. The digital circuit includes the first circuit whose sources are coupled to each other. a second IGFET; a first input terminal to which the gates of the first IGFET are coupled;
a plurality of differential amplifier circuits each having a second input terminal coupled to the gate of the first IGFET, and an output terminal to which a signal based on at least the drain output of the first or second IGFET is supplied; 2. The semiconductor integrated circuit device according to claim 1, wherein said input signal is supplied, and said second input terminal is supplied with a predetermined potential. 6. Above 1. 6. The semiconductor integrated circuit device according to claim 5, wherein the threshold voltage difference between the second IGFETs is based on the Fermi level difference between their gate electrodes. 7. Above 1. 7. The semiconductor integrated circuit device according to claim 6, wherein each gate electrode of the second IGFET has a semiconductor layer portion having a different conductivity type. Below margin