JPS60241238A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60241238A
JPS60241238A JP9645784A JP9645784A JPS60241238A JP S60241238 A JPS60241238 A JP S60241238A JP 9645784 A JP9645784 A JP 9645784A JP 9645784 A JP9645784 A JP 9645784A JP S60241238 A JPS60241238 A JP S60241238A
Authority
JP
Japan
Prior art keywords
holes
substrate
hole
semiconductor device
conductor patterns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9645784A
Other languages
Japanese (ja)
Inventor
Kazuo Kojima
和夫 小島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9645784A priority Critical patent/JPS60241238A/en
Publication of JPS60241238A publication Critical patent/JPS60241238A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA

Abstract

PURPOSE:To increase the number of conductor patterns by making rooms between through-holes by a method wherein a substrate is cut inside the line connecting the through-holes. CONSTITUTION:A plurality of through-holes 12 are bored in a glass-epoxy-made substrate 11 at suitable intervals, and the conductor patterns 2 are formed on both sides of the substrate 11. Next, the substrate 11 is cut with a press machine or the like along the line combining the through-holes 12. Then, the through- holes 12 are plated with Cu and Ni, thus connecting the upper and lower patterns 2. Since cutting is done on the line II-II inside the center line I - I of the through-holes 12, the distance between through-holes increases by the division thereof.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は半導体装置の製法に関し、特に、チップキャリ
アタイプパッケージの基板の大きさを大きくすることな
く高密度に配線を配設することができる技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a technique that allows wiring to be arranged at high density without increasing the size of a substrate of a chip carrier type package.

〔背景技術〕[Background technology]

チップキャリアタイプの半導体装置の一つとして、パッ
ケージのベース材料としてガラスエポキシ樹脂を用いた
ものが提案されている（特願昭−５７−１６２３０号、
同５７−１６２３１号）。As one of the chip carrier type semiconductor devices, one using glass epoxy resin as the base material of the package has been proposed (Japanese Patent Application No. 57-16230,
No. 57-16231).

このようなパッケージにあっては、近時電子機器の高密
度化に伴なって入出力端子数を増す、二とが要求され、
パッケージの周囲にできるだけ多くの導体パターン（メ
タライズ層）を配列した配線密度の高い製品がめられて
いる。しかしながら、導体パターンの数を増加しようと
する場合にはそれに伴ないパッケージのベースの大きさ
も大きくせざるを得なかった。In recent years, with the increasing density of electronic devices, there is a need for such packages to have an increased number of input/output terminals.
Products with high wiring density, in which as many conductor patterns (metallized layers) as possible are arranged around the package, are being sought after. However, when attempting to increase the number of conductor patterns, the size of the base of the package has to be increased accordingly.

〔発明の目的〕[Purpose of the invention]

本発明の目的は導体バター２ρ間隔を狭くして、高密度
に導体パターンを配列することができる半導体装置の製
法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device in which conductor patterns can be arranged with high density by narrowing the interval between conductor patterns 2ρ.

本発明の他の目的は高密度実装可能なチップキヤリアタ
イプの半導体装置を提供することにある。Another object of the present invention is to provide a chip carrier type semiconductor device that can be mounted at high density.

本発明の前記ならびにそのほかの［１的と新規な特徴は
、本明ｍ書の前述および添付図面からあきらかになるで
あろう。The above and other novel features of the present invention will become apparent from the foregoing and accompanying drawings of this specification.

〔発明の概要〕[Summary of the invention]

本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.

すなわち、例えば、スルーホールの切断位置をスルーホ
ールの中心線より内側にすることにより、スルーホール
間の距離を拡大し、それに伴ない導体パターンを多数増
加して配列できるようにしたものである。That is, for example, by arranging the cutting position of the through-holes inside the center line of the through-holes, the distance between the through-holes can be increased, and accordingly, the number of conductor patterns can be increased and arranged.

〔実施例〕〔Example〕

本発明の実施例であるチップキャリアタイプの半導体装
置を第１図〜第３図に示す。A chip carrier type semiconductor device according to an embodiment of the present invention is shown in FIGS. 1 to 3.

第１図にて、１は例えばガラスエポキシ基材により構成
されたパッケージのベース（以下基板）であり、当該基
板の上面には例えばＣｕ　ｆｆｉより成る複数の導体パ
ターン（プリント配線）２が配設されている。当該上面
のパターン２は、第２図に示すように、基板１上にマウ
ン１〜された半導体チップ３と例えばＡＱ細線より成る
コネクタワイヤ５により一端でボンディングされ、さら
に、当該上面パターン２は下面導体パターン６とスルー
ホールに形成された配線層４により電気的に接続されて
いる。半導体チップ３は湿気の侵入等外気から保護する
ために樹脂７によって封止される。In FIG. 1, 1 is a base (hereinafter referred to as a board) of a package made of, for example, a glass epoxy base material, and a plurality of conductor patterns (printed wiring) 2 made of, for example, Cu ffi are arranged on the upper surface of the board. has been done. As shown in FIG. 2, the upper surface pattern 2 is bonded at one end to the semiconductor chip 3 mounted on the substrate 1 by a connector wire 5 made of, for example, an AQ wire. The conductor pattern 6 is electrically connected to the wiring layer 4 formed in the through hole. The semiconductor chip 3 is sealed with a resin 7 to protect it from the outside air such as moisture intrusion.

第３図は当該装置をガラスエポキシ基材よりなるプリン
ト基板８に導体パターン９を介して半田ＩＯによって実
装して成る様子を示したものである。FIG. 3 shows how the device is mounted on a printed circuit board 8 made of a glass epoxy base material through a conductive pattern 9 by solder I/O.

このようなチップキャリアタイプパッケージにおいて、
その基板１は例えば次のようにして形成する。In such a chip carrier type package,
The substrate 1 is formed, for example, as follows.

（１）ガラスエポキシ素材基板を用意し、第４図に示す
ように当該素材基板１１に複数のスルーホール１２を適
宜間隔をおいて孔設するとともに前記した導体パターン
２，６を当該基板１両面に形成する。(1) A glass epoxy material substrate is prepared, and as shown in FIG. 4, a plurality of through holes 12 are formed in the material substrate 11 at appropriate intervals, and the conductor patterns 2 and 6 are placed on both sides of the substrate 1. to form.

（２）第４図および第５図に示すように、当該スルーホ
ール１２を結ぶ線に沿って当該素材基板１１をプレス機
等を用いて切断する。四角形成の素材基板が得られ、当
該基板の周端縁には円を切り欠いた断面形状の溝に形成
された溝（以下スルーホールという）が形成される。(2) As shown in FIGS. 4 and 5, the material substrate 11 is cut along the line connecting the through holes 12 using a press or the like. A rectangular material substrate is obtained, and a groove (hereinafter referred to as a through hole) having a circular cross-sectional shape is formed on the peripheral edge of the substrate.

（３）当該スルーホールに配線層例えば電解によるＧｕ
メッキ及びＮｉメッキを施し、前述のごとく、上下の導
体パターンを接続し、その際に、スルーホールの導通信
頼性を確保するために、スルーホールの周囲にはランド
を施す。(3) A wiring layer such as Gu formed by electrolysis is applied to the through hole.
Plating and Ni plating are applied to connect the upper and lower conductor patterns as described above, and at this time, lands are applied around the through holes to ensure continuity reliability of the through holes.

第５図は、このようにして得られる基板１のスルーホー
ル部（基板ｌの周辺端部）を示し、２は基板上面に形成
された導体パターン、１２はスルーホール、１３はスル
ーホールの中心線（破断線）、１４はランド（図中斜線
を施しである）であり、スルーホール１２を横切る切断
線１６は当該基板ｌの周縁と一致している。FIG. 5 shows the through-hole portion of the substrate 1 (peripheral edge of the substrate l) obtained in this way, where 2 is the conductor pattern formed on the top surface of the substrate, 12 is the through-hole, and 13 is the center of the through-hole. The line (broken line) 14 is a land (hatched in the figure), and the cutting line 16 that crosses the through hole 12 coincides with the periphery of the substrate l.

上記のような構造の場合、スルーホール（ランドを含め
て）の大きさと形状が外部端子すなわち導体パターンの
数を決定することになる。すなわち、スルーホール径を
小さく形成できれば、導体パターンを多数増加して配列
できる。しかし、現在のドリル等によるスルーホール形
成技術ではそれも困難であり、一般にスルーホール直径
０．４ｍ、ランド直径（外径）０．８ｍｍが限界で、当
該パターンピッチ１５もそれに伴ないせいぜい１ｍ／ｍ
までにしかできない。In the case of the above structure, the size and shape of the through holes (including lands) determine the number of external terminals, ie, conductor patterns. That is, if the diameter of the through hole can be made small, a large number of conductor patterns can be arranged. However, this is difficult with current through-hole forming technology using drills, etc., and generally the through-hole diameter is 0.4 m and the land diameter (outer diameter) is 0.8 mm, and the pattern pitch 15 is also at most 1 m/ m
I can only do so far.

本発明においては、第５図に示すように、ｌ−■線（ス
ルーホール１２の中心線）１３で切断することに代えて
■−■線１６のごとく、該スルーホールの中心線（１−
１線）１３より内側に切断する。これにより、スルーホ
ールの接線Ｘと接線Ｙとの距離Ｚ分だけスルーホール間
の距離が増大する。その分導体パターンのピッチを小さ
くしその配列（数）を増加することができ、延いてはパ
ターンが高密度に実装できるようになる。尚第５図にて
、２は導体パターン、Ｉ４はランドである。In the present invention, as shown in FIG.
1 line) Cut inward from line 13. As a result, the distance between the through holes increases by the distance Z between the tangents X and Y of the through holes. Accordingly, the pitch of the conductor patterns can be reduced and the arrangement (number) thereof can be increased, which in turn allows the patterns to be mounted at high density. In FIG. 5, 2 is a conductor pattern and I4 is a land.

上記のごとくスルーホールの中心線からずらしで切断す
る場合の距離としては１例えば約０．３ｍ　／　ｍが適
当である。When cutting off-center from the center line of the through-hole as described above, a suitable distance is 1, for example, about 0.3 m/m.

本発明においては、スルーホールを第６図に示すように
、その切断位置をずらし、かつパターンピッチＣスルー
ホールピッチ）をつめたときに、各ランド間が接触する
ような場合には、これらランド間のショートを防止する
ために、第６図に示すように、基板側面を切欠き１５し
、ランド１４゜１４′のショート部分を例えば断面コ字
状に取除きする。In the present invention, as shown in FIG. 6, when the cutting positions of the through holes are shifted and the pattern pitch C (through hole pitch) is reduced, if the lands come into contact with each other, these lands In order to prevent a short circuit between the two, as shown in FIG. 6, a notch 15 is made in the side surface of the substrate, and the short portion of the lands 14.about.14' is removed, for example, in a U-shaped cross section.

このようにして、得られた基板側面の要部拡大図は第１
図のように示され、基板１の周側面にスルーホール１２
が形成され、当該スルーホール１２の壁面には配線４が
形成されている。該配線４は上面の導体パターン２と下
面の導体パターン（図示せず）を電気的に導通させる。In this way, the enlarged view of the main part of the side surface of the substrate obtained is shown in Figure 1.
As shown in the figure, a through hole 12 is formed on the peripheral side of the substrate 1.
is formed, and a wiring 4 is formed on the wall surface of the through hole 12. The wiring 4 electrically connects the conductor pattern 2 on the upper surface and the conductor pattern (not shown) on the lower surface.

また、プリント基板ｌ側面には、ランド１／ｌ、１４’
のショートを防止するために、断面コ字状にカッ１へ１
５を施しである。Also, on the side of the printed circuit board l, there are lands 1/l and 14'.
In order to prevent short-circuiting, the cross section is C-shaped.
5 is alms.

〔効果〕〔effect〕

（１）スルーホールを形成した基板の切断に際し。 (1) When cutting a board with through holes formed.

従来のスルーホールの中心線よりも内側で切断するか、
あるいはスルーホールの孔設に際し、スルーホールの中
心線を従来のスルーホールの中心線より当該素材基板外
側にずらすことにより、スルーホール間に余裕（第５図
Ｚ）が出来、その分導体パターンの数を増加し、導体パ
ターンを高密度に実装できる。Cut inside the center line of a traditional through hole, or
Alternatively, when creating through-holes, by shifting the center line of the through-hole to the outside of the material board from the center line of the conventional through-hole, a margin (Z in Figure 5) can be created between the through-holes, and the conductor pattern can be adjusted accordingly. The number of conductor patterns can be increased and conductor patterns can be mounted with high density.

本発明によれば、パターンピッチ（ス、ルーホールピッ
チ）を板厚によっては０．６５ｍ／ｍ以下とすることが
でき、実装面積を著しく減少させることができた。そし
て、高密度にパターンが配列される分、基板の大きさも
小さくすることができた。逆に、基板を小さくしても高
密度に導体パターンが配列できることになる。According to the present invention, the pattern pitch (through-hole pitch) can be set to 0.65 m/m or less depending on the plate thickness, and the mounting area can be significantly reduced. Furthermore, since the patterns were arranged in high density, the size of the substrate could be reduced. Conversely, even if the substrate is made smaller, conductive patterns can be arranged with high density.

この点従来のガラスエポキシ基板を使用したチップキャ
リアではスルーホール、ランドがあい路となっ′て基板
外径を小さくする事が難しかったが、本発明法によれば
その外径を小さくすることができる。In this respect, with conventional chip carriers using glass epoxy substrates, the through holes and lands become open paths, making it difficult to reduce the outer diameter of the substrate, but with the method of the present invention, it is possible to reduce the outer diameter. can.

（２）各ランド間のショート部分をカットするようにし
たので、導体パターンがより一層高密度に配列でき、ま
たプリント基板の外径もより一層縮小できる。(2) Since the short portion between each land is cut, the conductor patterns can be arranged with higher density, and the outer diameter of the printed circuit board can be further reduced.

（３）本発明により得られた基板を使用して、当該基板
上に半導体チップをマウントし、コネクタワイヤで高密
度に配列された導体パターンとワイヤボンディングし、
樹脂封止することにより高密度に実装された、多ピン化
に対処できる、実装密度の高い第１図及び第２図に示す
ようなチップキャリアタイプのプラスチックパッケージ
が得られる。　例えば、前記実施例ではカット部分１５
を断面コ字状と成した実施例を示したが、半円形等信の
形状にカットしてもよい。(3) Using the substrate obtained according to the present invention, mounting a semiconductor chip on the substrate and wire-bonding it to a conductor pattern arranged in high density with a connector wire,
By resin sealing, it is possible to obtain a chip carrier type plastic package as shown in FIGS. 1 and 2, which can be mounted with high density and can cope with an increase in the number of pins. For example, in the above embodiment, the cut portion 15
Although an embodiment has been shown in which the cross section is U-shaped, it may be cut into a semicircular shape.

また当該カッ１−について前記実施例では基板側面の上
下全体にわたってカットした例を示したが、部分的にカ
ットシてもよく、例えば当該基板の」二部と下部の一部
のみをカッ１〜してもよい。In addition, although the above embodiment shows an example in which the cutter 1- is cut over the entire upper and lower sides of the board, it may also be partially cut. It's okay.

以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

〔利用分野〕[Application field]

以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野であるチップキャリアタイ
プパッケージの基板について適用した場合について説明
したが、それに限定されるものではなく、セラミック等
の他の各種基板にも適用できる。In the above explanation, the invention made by the present inventor was mainly applied to the substrate of a chip carrier type package, which is the background field of application, but the invention is not limited to this, and It can also be applied to various substrates.

伽Fairy tale

【図面の簡単な説明】[Brief explanation of drawings]

第１図はチップキャリアタイプの半導体パッケージの斜
視図、第２図はパッケージの断面図、第３図は同パッケ
ージをプリント基板に実装した状態を示す断面図、第４
図は従来例のプリント基板製造工程を説明する平面図、
第５図及び第６図は本発明の製造工程を説明する要部拡
大図、第７図は同要部断面図である。 ■・・・プリント基板、２・・・導体パターン、３・・
半導体チップ、４・・・配線、５・・・コネクタワイヤ
、６・・導体パターン、７・・・樹脂封止体、８・・・
プリント基板、９・・・導体パターン、１０・・・半田
、１１・・プリント基板用素材基板、１２・・スルーホ
ール、１３・・スルーホールの中心線、１４．］／Ｉ’
・・・ランド、Ｊ５・・・カット部分。 第　１　図 第　２　図 第　４　図 第　５　図 第　６　図 第　７　図Fig. 1 is a perspective view of a chip carrier type semiconductor package, Fig. 2 is a sectional view of the package, Fig. 3 is a sectional view showing the package mounted on a printed circuit board, and Fig. 4 is a sectional view of the package.
The figure is a plan view explaining the conventional printed circuit board manufacturing process.
FIGS. 5 and 6 are enlarged views of main parts for explaining the manufacturing process of the present invention, and FIG. 7 is a sectional view of the main parts. ■...Printed circuit board, 2...Conductor pattern, 3...
Semiconductor chip, 4... Wiring, 5... Connector wire, 6... Conductor pattern, 7... Resin sealing body, 8...
Printed circuit board, 9. Conductor pattern, 10. Solder, 11. Material board for printed circuit board, 12. Through hole, 13. Center line of through hole, 14. ]/I'
...Land, J5...Cut part. Figure 1 Figure 2 Figure 4 Figure 5 Figure 6 Figure 7

Claims (1)

【特許請求の範囲】 １、基板材料にスルーホールを適宜間隔をおいて複数設
け、各スルーホールの中心を結ぶ線に沿って当該基板材
料を切断して成る基板であって、上下両面に導体パター
ンが複数配置され、かつ当該上下両パターン間を前記ス
ルーホールに形成された配線により接続して成る基板を
有する半導体装置の製法において、前記基板材料の切断
に際し、前記スルーホールの中心を結ぶ線より内側を切
断することを特徴とする半導体装置の製法。 ２、各スルーホールの周囲に設けられた各ランド間が接
触する場合、基板側面からランド間接触部分を取除くこ
とを特徴とする特許請求の範囲第１項記載の半導体装置
の製法。　゛[Claims] 1. A board made by providing a plurality of through holes at appropriate intervals in a board material and cutting the board material along a line connecting the centers of each through hole, the board having conductors on both the top and bottom surfaces. In a method for manufacturing a semiconductor device having a substrate in which a plurality of patterns are arranged and the upper and lower patterns are connected by wiring formed in the through hole, a line connecting the centers of the through holes when cutting the substrate material. A method for manufacturing a semiconductor device characterized by cutting on the inner side. 2. The method for manufacturing a semiconductor device according to claim 1, characterized in that when the lands provided around each through hole come into contact, the contact portion between the lands is removed from the side surface of the substrate.゛
JP9645784A 1984-05-16 1984-05-16 Manufacture of semiconductor device Pending JPS60241238A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9645784A JPS60241238A (en) 1984-05-16 1984-05-16 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9645784A JPS60241238A (en) 1984-05-16 1984-05-16 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60241238A true JPS60241238A (en) 1985-11-30

Family

ID=14165553

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9645784A Pending JPS60241238A (en) 1984-05-16 1984-05-16 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60241238A (en)

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