JPS60240218A - Differential pcm encoding system - Google Patents

Differential pcm encoding system

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Publication number
JPS60240218A
JPS60240218A JP9696784A JP9696784A JPS60240218A JP S60240218 A JPS60240218 A JP S60240218A JP 9696784 A JP9696784 A JP 9696784A JP 9696784 A JP9696784 A JP 9696784A JP S60240218 A JPS60240218 A JP S60240218A
Authority
JP
Japan
Prior art keywords
value
difference
input
circuit
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9696784A
Other languages
Japanese (ja)
Other versions
JPH0215138B2 (en
Inventor
Hitoshi Sato
均 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9696784A priority Critical patent/JPS60240218A/en
Publication of JPS60240218A publication Critical patent/JPS60240218A/en
Publication of JPH0215138B2 publication Critical patent/JPH0215138B2/ja
Granted legal-status Critical Current

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  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)

Abstract

PURPOSE:To reproduce a correct value at a receiving side while making the scale of a circuit small, by using a value accumulated in a previous value forecasting memory for taking a difference from an input value, as a past input val- ue. CONSTITUTION:When transmitting a signal from a PCM encoder 1, with respect to a present signal X0, X-1 before the signal X0 by one is stored in advance as a forecasting value in a memory 4'', and a difference between the signals X0 and X-1 is derived by a subtracter 2 and sent out as a difference d0. At a receiving side, encoding can be executed by adding this difference d0 to the pre-input value X-1, and the circuit scale can be made small.

Description

【発明の詳細な説明】 fal 発明の技術分野 本発明はアナログ信号′ff:PCM符号化し帯域圧縮
して伝送する差分PCM符号化方式の改良に関する。
DETAILED DESCRIPTION OF THE INVENTION fal Technical Field of the Invention The present invention relates to an improvement in a differential PCM encoding method in which an analog signal 'ff is PCM encoded, band compressed, and transmitted.

fbl 技術の背景 差分PCM (以下DPCMと称す)符号化方式は、例
えばテレビジョン信号の伝送の如く、広帯域が必要で伝
送路費用の負担が大きく帯域圧縮の効果が大きい信号伝
送の場合良く使用される。
fbl Technology background The differential PCM (hereinafter referred to as DPCM) encoding method is often used for signal transmission, such as television signal transmission, which requires a wide band, has a large transmission path cost, and has a large band compression effect. Ru.

(C1従来技術と問題点 DPCMPCM符号化方式−第1図CM回路及列値X−
1r xQ l xl ”””をzn、差分出力値do
+d1・・・ ・・・をdnとすると、dnを算出する
のは、次式α)(2)に示す如く、前値予測メモリ4に
蓄積されている前値予測系列値xn−2′ と、差分出
力値dn−1との和を加算器8にてめた前値予測系列値
Xn −1’と入力系列値xnとの差を、減算器2にて
めて行っていた。
(C1 Prior art and problems DPCMPCM encoding system - Figure 1 CM circuit and value X -
1r xQ l xl """ is zn, difference output value do
+d1...... is dn, then dn is calculated based on the previous value prediction series value xn-2' stored in the previous value prediction memory 4, as shown in the following equation α) (2). , and the difference output value dn-1 in the adder 8, and the difference between the previous predicted sequence value Xn-1' and the input sequence value xn is calculated in the subtracter 2.

xn −1’ == dn −l+ xn −2’−=
=・・・・−(1)dn= xn −zn −1’・・
・・・・・・・・・・・・・・・・・・・(2)これは
主に差分出力値dnが伝送可能な最大値dn より大き
くなることがあり、例えばdn −1)dnの時、前値
予測系列値はxn −1’ = dn −1+ xa 
−z’であるものが次の(8)式の如くなり、zn −
1’ = dM+Xn−2・・・・・・・・・・・・・
・・・・・・・・(8)Xn−1′三Xrs−1と出来
なく、前入力値との差をめる方式がとれない為である。
xn -1' == dn -l+ xn -2'-=
=...-(1) dn= xn -zn -1'...
・・・・・・・・・・・・・・・・・・・・・(2) This mainly means that the differential output value dn may be larger than the maximum value dn that can be transmitted, for example, dn −1) dn When , the previous predicted series value is xn -1' = dn -1+ xa
−z' becomes as shown in the following equation (8), and zn −
1' = dM+Xn-2・・・・・・・・・・・・・
This is because (8) Xn-1'3Xrs-1 cannot be obtained, and a method of calculating the difference with the previous input value cannot be used.

(勿論dn>dMの場合がなければ前値予測系列値に置
換えることが出来る。) 例えば第2図(5)に示す如く入力系列値Ya+bpc
、dとし、bの値がaの値より伝送可能な最大値dMの
2倍太き(、b、c、dの値は同じ値だとすると、メモ
リ4に前入力系列値の(xn−1)Y蓄積し、入力系列
値X11との差をとり、差分l出力する方法だと、bの
値とaの値との差分は最大値dnとなり、後は差分Oと
なってしまうので、受信側で復学化した場合す、c、d
の値は第2図(clに示す如くaの値よりdMだゆ大き
いb’、’、d’の値となってしまうからである。
(Of course, if there is no case where dn>dM, it can be replaced with the previous predicted sequence value.) For example, as shown in FIG. 2 (5), the input sequence value Ya + bpc
, d, and the value of b is twice as thick as the maximum transmittable value dM than the value of a (assuming that the values of b, c, and d are the same), the memory 4 stores (xn-1) of the previous input sequence value. If the method is to accumulate Y, take the difference from the input series value If you are reinstated, c, d
This is because the values of b', ', and d' are much larger by dM than the value of a, as shown in FIG. 2 (cl).

しかし、メモリ4に蓄積するの71前値予測系列値(x
n−1’)とすると、bが入力した時は差分出力は2d
Mでなく、 dMとなるが、Cが入力した(B)に示す
如くbの値はaの値よりdMだけ大きいb′となり、c
、dの値はaの値より2dM大きいc、dの値となり、
bの時は正しい値とならないが次のc、dの時は正しい
値となるからである。
However, 71 previous predicted series values (x
n-1'), when b is input, the difference output is 2d
It becomes dM instead of M, but as shown in (B) inputted by C, the value of b becomes b' which is larger than the value of a by dM, and c
, the value of d is the value of c, d which is 2 dM larger than the value of a,
This is because the correct value is not obtained at the time of b, but the correct value is obtained at the following times of c and d.

だが常にdM 〉dMとなるよう伝送可能な最大値dM
のビット数を多くしておき、正しい値が受信側で再生出
来るDPCM符号化方式では、(1)式より次の(4)
式が成立し、(4)式より(4)7式が導かれる。
However, the maximum value dM that can be transmitted so that always dM > dM
In the DPCM encoding method, in which the correct value can be reproduced on the receiving side by increasing the number of bits, the following (4) is obtained from equation (1).
The formula holds, and formula (4)7 is derived from formula (4).

x n−s’ = d n−s 十x n−/・・・・
・・・・・・・・・・・・・・・・・・・(4)d n
−1’ = xn−1’−Xl!−*’・・・・・・・
・・・・・・・・・・・・・・(4)′一方(2)式よ
り次の(2)′が導かれ、dn 1=)(n t−zB
−己・・・・・曲・・・・・・・・・・・・・・・・・
(2)’Xn 1’:)(n 1となり 前値予測系列値Xn1”を実際の前入力値X11−1と
すればよいにかかわらず、前値予測系列値を用いている
ので、第1図のDPCM回路となり、回路規模が大きい
欠点がある。
x n-s' = d n-s 1 x n-/...
・・・・・・・・・・・・・・・・・・・・・(4)d n
-1' = xn-1'-Xl! -*'・・・・・・・・・
・・・・・・・・・・・・・・・(4)′ On the other hand, the following (2)′ is derived from equation (2), and dn 1=)(n t−zB
-Myself...Song......
(2) 'Xn 1':) (n becomes 1, so the previous value predicted series value The DPCM circuit shown in the figure has the disadvantage of a large circuit scale.

又正しい値が受信側で再生出来る別のDPCM符号化方
式として、dnくdMの時はDPCM符号化方式を用い
、dII)dMQ時は、差分とせずPCM信号を其のま
ま送り、両値予測メモリに蓄積する前値予測符号列値(
X、’)のかわりに前入力系列値(x−)に置換える方
式が既に提案されている。
In addition, as another DPCM encoding method that allows correct values to be reproduced on the receiving side, when dn dM, the DPCM encoding method is used, and when dII) dMQ, the PCM signal is sent as it is without using the difference, and both values are predicted. The previous predicted code string value (
A method has already been proposed in which the previous input sequence value (x-) is used instead of the previous input sequence value (x,').

この方式に付いて菖3図第4図ン用いて説明する。This method will be explained using Figure 3 and Figure 4.

この場合は、dfiくdMの時は、スイッチSWIはD
PCM側に接続され、DPCM部5にて、前記と同じ<
、PCM符号器lにてPCM符号化された入力値Xoと
、メモリ4′に記憶している前値予測系列値x−1′と
の差分doをとり、この差分ン多重化回路10に入力す
る。
In this case, when dfi - dM, switch SWI is D
It is connected to the PCM side, and in the DPCM section 5, the same <
, the difference do is taken between the input value Xo encoded by PCM in the PCM encoder l and the previous value prediction sequence value x-1' stored in the memory 4', and inputted to this difference multiplexing circuit 10. do.

この時識別信号発生部9には例えばOが発生し、多重化
回路10に入力し、多重化回路lOよりは、第4図の■
■で示される符号が出力される。
At this time, for example, O is generated in the identification signal generating section 9, inputted to the multiplexing circuit 10, and from the multiplexing circuit 10,
The code indicated by ■ is output.

次に減算器2にてめた差分がd+s)dMであると、過
負荷検出回路6はこれン検出し、スイッチSWI ’Y
 PCM側に接続すると共にゲート8を駆動して、メモ
リ7に蓄積されている今の入力系列値X+IYメモリ4
′に蓄積すると共に多重化回路10に送り、又識別信号
発生部9では例えば1が発生し、多重化回路10に入力
し、多重化回路】Oよりは第4図の■■に示される符号
が出力される。次はメモリ4′に蓄積された入力系列値
−R+−1と入力系列値x十gとの差分tとる。
Next, when the difference obtained by the subtracter 2 is d+s)dM, the overload detection circuit 6 detects this and switches SWI 'Y
Connect to the PCM side and drive the gate 8 to read the current input sequence value X+IY stored in the memory 7 memory 4
' and sends it to the multiplexing circuit 10, and the identification signal generating section 9 generates, for example, 1, which inputs it to the multiplexing circuit 10. is output. Next, the difference t between the input series value -R+-1 stored in the memory 4' and the input series value x0g is obtained.

しかしこの場合も差分lとるのはdn<、dMの時であ
り、dn)dMの時は差分tとらないので、前記説明の
如く、前値予測系列値のかわりに、実際の前入力系列値
を用いればよいにかかわらず、前値予測系列値Z用いて
いるので第3図に示す回路対執路規模が大きい欠点があ
る。
However, in this case as well, the difference l is taken when dn<, dM, and the difference t is not taken when dn)dM. Therefore, as explained above, instead of the previous predicted sequence value, the actual previous input sequence value However, since the previous prediction series value Z is used, there is a drawback that the scale of the circuit pair shown in FIG. 3 is large.

Tdl 発明の目的 ′本発明の目的は上記の欠点に鑑み、正しい値が受信側
で再生出来るDPCM符号化方式において、回路規模ン
小さく出来る萌入力値使用DPCM符号化方式の提供に
ある。
OBJECT OF THE INVENTION In view of the above-mentioned drawbacks, the object of the present invention is to provide a DPCM encoding method using MoE input values that can reduce the circuit size in a DPCM encoding method in which correct values can be reproduced on the receiving side.

[el 発明の構成 上記の目的は、DPCM符号化方式において、入力値と
の差分をとる前値予測メモリに蓄積する値ン、過去の入
力値とする本発明の構成により達成される。
[el Structure of the Invention The above object is achieved by the structure of the present invention in which, in the DPCM encoding system, the value stored in the previous value prediction memory that takes the difference from the input value is the past input value.

即ちこのようにすることにより、予測系列値を用いる必
要がなくなるので、第1図の場合は加算器3、第3図の
場合は加算器3、ゲート8及びメモリを1個削除出来、
回路規模を小さく出来る。
That is, by doing this, there is no need to use the predicted sequence value, so the adder 3 in the case of FIG. 1 and the adder 3, gate 8, and memory in the case of FIG. 3 can be deleted,
The circuit scale can be reduced.

(fl 発明の実施例 以下本発明の実施例につき図に従りて説明する。(fl Embodiments of the invention Embodiments of the present invention will be described below with reference to the drawings.

第5図は、當にdnくdMとなるよう伝送可能な最大値
dMのビット数7大きくした場合の、本発明の実施例の
回路のブロック図である。
FIG. 5 is a block diagram of a circuit according to an embodiment of the present invention when the number of bits of the maximum transmittable value dM is increased by 7 so that dn decreases dM.

図中第1図と同一機能のものは同一記号で示し、4“は
メモリである。
Components in the figure that have the same functions as those in FIG. 1 are indicated by the same symbols, and 4'' is a memory.

この場合はメモリ4″に蓄積された前入力値X−1と、
現在の入力値XQとの差分を減算器2でめ差分d0とし
て送出するもので、この差分山は従って第1図と比較す
れば明らかな如く加算器3は不要となり回路規模を小さ
く出来る。
In this case, the previous input value X-1 stored in the memory 4'',
The difference with the current input value XQ is sent out as the difference d0 by the subtracter 2, and this difference mountain is therefore made unnecessary, as is clear from a comparison with FIG. 1, and the circuit scale can be reduced.

第6図はdn)dMの場合もある時の本発明の実施例の
回路のブロック図で第3図と対応している。
FIG. 6 is a block diagram of a circuit according to an embodiment of the present invention in the case of dn)dM, and corresponds to FIG. 3.

図中第3図と同一機能のものは同一記号で示し、4′は
メモリである。
Components with the same functions as those in FIG. 3 are indicated by the same symbols, and 4' is a memory.

dnくdMの場合は、スイッチSWIはDPCM側に接
続されており、第5図の場合と同じくメモリ4′に蓄積
された前入力値x−1と現在の入力値Xo との差分Z
減算器2でめ差分d。とじ、第3図の場合と同じく識別
信号発生部9で発生する0と7多重化回路/f10で配
列して第4図■■で示す符号を出力する。
In the case of dnkudM, the switch SWI is connected to the DPCM side, and as in the case of FIG. 5, the difference Z between the previous input value x-1 stored in the memory 4' and the current input value Xo is
Subtractor 2 makes the difference d. As in the case of FIG. 3, the 0 and 7 multiplexing circuits/f10 generated by the identification signal generator 9 are arranged to output the code shown in FIG. 4.

次に入力値x+1が入力し減算器2にてめた差分がd+
l>dMであれば、過負荷検出回路6はこれン検出し、
スイッチSWI YPCM側に接続し、メモリ4Mに蓄
積された入力値x+1は多重化回路】0に送られ、識別
信号発生部9では第3図の場合と同じく1が発生し多重
化回路IOに入力し、多重化回路10よりは第4図■■
に示される符号が出力される。次はメモリ4Mに蓄積さ
れた入力値x+1と入力値x+sとの差分が減算器2に
てとられる。
Next, input value x+1 is input and the difference obtained by subtracter 2 is d+
If l>dM, the overload detection circuit 6 detects this,
The input value x+1 connected to the switch SWI YPCM side and stored in the memory 4M is sent to the multiplexing circuit 0, and the identification signal generating section 9 generates 1 as in the case of Fig. 3, which is input to the multiplexing circuit IO. However, from the multiplexing circuit 10, Fig. 4 ■■
The code shown in is output. Next, the subtracter 2 calculates the difference between the input value x+1 and the input value x+s stored in the memory 4M.

即ち第6図で第3図と同様の帯域圧縮が行なわれ、比較
すれば判る如く、メモIJ 1個及び加算器及びゲート
回路を削減出来回路規模を小さくすることが出来る。
That is, the same band compression as in FIG. 3 is performed in FIG. 6, and as can be seen from the comparison, one memory IJ, adder, and gate circuit can be eliminated, and the circuit scale can be reduced.

(gl 発明の効果 以上詳細に説明せる如く本発明によれば、正しい値が受
信側で再生出来るDPCM符号化方式においては、従来
方式に比し回路規模を小さく出来る効果がある。
(gl Effects of the Invention As explained in detail above, according to the present invention, in the DPCM encoding method in which correct values can be reproduced on the receiving side, there is an effect that the circuit scale can be made smaller than in the conventional method.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例のDPCM回路のブロック図、第2図は
予測系列値ケ用いる理由ン説明する線図、第3図は従来
例の正しい値が受信側で再生出来るDPCM回路のブロ
ック図、第4図は第3図の場合の符号化出力の一例を示
す説明図、幀I−≠亭撓Hem flllGf’15 
?μl11m1i第5図は本発明の実施例の正しい値が
受信側で再生出来る前人力値使用DPCM回路のブロッ
ク図、第6図はdn)dMの場合もある時の本発明の実
施例の回路のブロック図である。 図中1はPCM符号器、2は減算器、3は加算器、4.
4’、4“、4” 、 7はメモリ、5はDPCM部、
6は過負荷検出回路、8はゲート、9は識別信号発生部
、10は多重化回路、SWIはスイッチ馨示す。 亭 1 図 茶 2 因 吟閲− ’114M1− 茶 3 目 茶 4− ス
Fig. 1 is a block diagram of a conventional DPCM circuit, Fig. 2 is a diagram explaining why predicted sequence values are used, and Fig. 3 is a block diagram of a conventional DPCM circuit that can reproduce correct values on the receiving side. FIG. 4 is an explanatory diagram showing an example of the encoded output in the case of FIG. 3.
? μl11m1i Figure 5 is a block diagram of a DPCM circuit using human input values that can reproduce the correct value on the receiving side according to an embodiment of the present invention, and Figure 6 is a block diagram of a DPCM circuit according to an embodiment of the present invention in which the correct value can be reproduced on the receiving side. It is a block diagram. In the figure, 1 is a PCM encoder, 2 is a subtracter, 3 is an adder, 4.
4', 4", 4", 7 is memory, 5 is DPCM section,
6 is an overload detection circuit, 8 is a gate, 9 is an identification signal generator, 10 is a multiplexing circuit, and SWI is a switch. Tei 1 Zucha 2 Inginbaku-'114M1- Tea 3 Mecha 4- Su

Claims (1)

【特許請求の範囲】[Claims] 差分PCM符号化方式において、入力値との差分をとる
前値予測メモリに蓄積する値ビ、過去の入力値とするこ
とン特徴とする差分PCM符号化方式。
A differential PCM encoding method is characterized in that a value stored in a previous value prediction memory that takes a difference from an input value is taken as a past input value.
JP9696784A 1984-05-15 1984-05-15 Differential pcm encoding system Granted JPS60240218A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9696784A JPS60240218A (en) 1984-05-15 1984-05-15 Differential pcm encoding system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9696784A JPS60240218A (en) 1984-05-15 1984-05-15 Differential pcm encoding system

Publications (2)

Publication Number Publication Date
JPS60240218A true JPS60240218A (en) 1985-11-29
JPH0215138B2 JPH0215138B2 (en) 1990-04-11

Family

ID=14178999

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9696784A Granted JPS60240218A (en) 1984-05-15 1984-05-15 Differential pcm encoding system

Country Status (1)

Country Link
JP (1) JPS60240218A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02285720A (en) * 1989-04-26 1990-11-26 Canon Inc Encoder

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55143830A (en) * 1979-04-26 1980-11-10 Nippon Telegr & Teleph Corp <Ntt> Forecasting coding unit
JPS5866439A (en) * 1981-10-16 1983-04-20 Fujitsu Ltd Waveform coding system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55143830A (en) * 1979-04-26 1980-11-10 Nippon Telegr & Teleph Corp <Ntt> Forecasting coding unit
JPS5866439A (en) * 1981-10-16 1983-04-20 Fujitsu Ltd Waveform coding system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02285720A (en) * 1989-04-26 1990-11-26 Canon Inc Encoder

Also Published As

Publication number Publication date
JPH0215138B2 (en) 1990-04-11

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