JPS60239831A - Microprogram control device - Google Patents

Abstract

PURPOSE:To expand the freedom of address distribution by optionally setting a branch condition inserting position in a branch control system. CONSTITUTION:Addredd information on an address signal line 8 for a control storage device consists of 16 bits. At the execution of an embedding instruction having an one-bit condition in branch processing, an embedding condition is added to any one bit specified by P0, P1 in the low-order 4 bits S4-S7 of an address field NEXA of a microinstruction to be the low-order 8 bits of the address through a signas line 7 to form the succeeding address on an address signal line 8. In said address formation method, the width of address branched in two directions by the condition-provided embedding type branch instruction can be varied.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to i-microprogram controlled snow removal, and in particular to its branch control method.

(Prior Art) In general, a microprogram-controlled data processing device basically includes a control storage device that stores a microprogram,
It consists of an address register corresponding to the control memory and a microinstruction register for storing the microinstruction currently being executed at the address read from the control memory. The execution order of microprograms is controlled by determining the address of the next microprogram to be executed, depending on the type of instruction of the currently executed microprogram.

One method for specifying the address of the microprogram to be executed next, that is, the next instruction address, is to provide a field for giving the next execution address element to the microinstruction.This method is suitable for branch processing. used. One of them is a conditional embedded branch type instruction. In this method, a condition is embedded in a predetermined pit position of a given address to determine the next address. With this type of instruction, branching in two or more directions is also possible by increasing the number of bits in the embedded condition. However, for example, in a 1-bit embedded branch as shown in FIGS. 1(a) and (b)K, if the insertion bit position of the embedded condition is fixed, two-way branching as shown in the address table of FIG. The number of steps between branch destinations, that is, the branch width, is fixed according to the insertion bit position of the embedding condition. Here, FIG. 1(a)H is a block diagram explaining the next address generation operation in a conventional 1-bit conditional embedded branch instruction.
Figure (b) shows the bit pattern for next address generation.

Figure 2 is a diagram showing address allocation for a 1-bit conditional embedded instruction in a microprogram.fi, al'2 +
bl "2 + CI '2 are two-way branch destinations in the conventional embedded bit fixation.

As mentioned above, there are restrictions on address allocation in microprograms, and as the number of embedded bits increases, address allocation becomes even more difficult.For example, if a useless unconditional branch is added in the middle, the number of steps increases and the allocation becomes The drawback was that it was impossible.

(Objective of the Invention) An object of the present invention is to provide a microprogram control device that eliminates the above-mentioned drawbacks and increases the degree of freedom in address assignment by configuring the branch condition insertion position in a branch control system to be freely settable. It's in particular.

(Structure of the Invention) A microprogram control device according to the present invention includes a next address generation section, and has a field for storing the address of a microinstruction to be executed next to a microinstruction.
! The next address is r1! The part includes a state holding means and an embedded holding means.

It is equipped with a selection means and an 8th address storage means.

The state holding means is an abbreviation for holding state information after execution of a preceding instruction.

The embedding holding means is for embedding and holding the state information as a part of the branch destination address when the branch processing is completed.

The selection means is for selecting the insertion position of the embedding.

The next address storage means is for generating and holding the next address.

(Example) Next, an example of the present invention will be described in detail with reference to the drawings.

FIG. 8 is a block diagram illustrating an embodiment of a portion of a microprogram controller according to the present invention.

Partial division of the microprogram control device shown in Figure 8,
It shows a microinstruction register 2 for holding the microinstruction currently being executed and a secondary address generation m3. In FIG. 3, the next address generation section 3 includes a state holding section 10 for holding various state information, a decoder 11 for generating a selection signal for the embedding position at the time of embedding branch with two conditions, and It is comprised of selection gates 12 to 15 for inserting condition information from the state holding section 10 for holding the various states mentioned above into the selected embedding position via a signal a7.

In this embodiment, the address signal m for the control storage device 1 is
The address information on 8 is assumed to be 16 bits.

In addition, when a 1-bit conditional embedding instruction is used in branch processing, the embedding condition is set in any one bit specified by Po and Pl of the lower 4 bits A4 to A7 of the address field NEXA of the microinstruction that is the lower 8e of the above address. is the signal Ii! i17 to generate the next address on address signal line 8.

By the above-described next address generation method, the address width of the branch destination in two directions in the conditional embedded branch instruction is made variable as shown in FIG. In FIG. 4, do-d, d2. d.

It has been shown that d4+eOel +82 +e'l +64 can realize the edible branch width of the branch destination in two directions by selecting the embedded bit.

The problem with the flexibility of address allocation explained in Figure 2 using the above method is that branching and
When assigning an address to the condition insertion position, use P o e P l
This problem can be resolved by freely setting the settings.

(Effects of the Invention) As explained above in the eleventh aspect of the present invention, when an embedded branch type instruction with a φ condition is used, the insertion position for embedding a specified condition can be freely set, thereby providing freedom in address allocation. This has the effect of increasing the speed, reducing unnecessary no-φ branch instructions, and allowing high-speed microprograms with a smaller number of steps to be handled.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating the next address generation operation in a conventional 1-bit conditional embedded branch instruction. FIGS. 2 and 4 are diagrams showing address assignment for a 1-bit format embedding instruction in a microprogram. FIG. 8 is a block diagram illustrating one embodiment of a next address generator forming part of a microprogram controller according to the present invention. 1...Control storage device 2...Fist/Micro instruction register 3...Medium address generation section 4...Current address register 10...Decoder 11...Status holding section 12-15...Work selection circuit 5-8 As-biased line patent applicant NEC Co., Ltd. agent Patent attorney Inoro 1st figure (6) (1)) 2nd figure T'11 B? ,, # Fig. 4 1tx translation multi-F

Claims (1)

[Claims] Selecting a state holding means for holding state information after execution of a preceding instruction, an embedded holding means for embedding and holding the state information as part of a branch destination address in branch processing, and an insertion position for the embedding. and a next address storage means for generating and holding a secondary address in the next address generation section, and a field for storing an address of a microinstruction to be executed next to the microinstruction. A stone microprogram control device characterized by comprising: