JPS60238923A - Bus line driving circuit - Google Patents

Abstract

PURPOSE:To realize a bus line driving circuit with a small chip area, by providing a p-channel MOS transistor (Tr) for pre-charging to a bus line and performing the output to the bus line by means of an n-channel MOSTr only. CONSTITUTION:During the ''1'' level period of a timing signal T1, a p-channel MOSTrTPR is turned on and a bus line 1 is pre-charged. Thereafter, if an output signal from a circuit block 5 is ''1'' level during the ''1'' level period of a timing signal T3, an n-channel MOSTrTN4 is turned on and the line 1 changes from ''1'' level to ''0'' level. If the signal from the block 5 is ''0'' level, the TrTN4 is turned off and ''1'' level is maintained at the line 1. During the ''1'' level period of a timing signal T2, an n-channel MOSTrTN2 and p-channel MOSTrTP2 are turned on and the data on the line 1 are transferred to a circuit block 4 through a clocked inverter 2.

Description

[Detailed Description of the Invention] [Technical Field] The present invention is a bus/line drive driven at high speed. The appearance of magnetic heads has been eagerly awaited.

However, metal magnetic materials generally have lower resistivity than ferrite, and as a result, the attenuation in the high frequency range due to the skin effect is large, so in order to obtain sufficient performance, the thickness of the head core had to be several tens of microns thick. . However, with such a thickness, the mechanical strength is weak, and in order to construct the head, it was necessary to join some kind of reinforcing body to both sides of the core. Conventionally, bonding has been performed using glass or ceramic as this reinforcing body. However, it is not easy to manufacture soft magnetic materials with a thickness of several tens of microns using sendust, ferrite, etc., and the bonding with the reinforcing plate is currently done with an organic adhesive, so it has poor heat resistance, moisture resistance, etc. There was a problem with basic quality. Furthermore, when lapping the gap portion as a head, machining the azimuth angle, etc. using a soft magnetic material bonded with an organic adhesive, the workpiece escapes due to processing stress, which is related to the basic 2-circuit.

C. Prior Art] In recent years, semiconductor integrated circuits (hereinafter referred to as ICs) such as microprocessors and display controllers have been commercialized, but the internal circuits of the ICs generally adopt a cross-line method. A bus line is a signal line configured such that valid data exists only at a certain timing and may or may not be fixed at other timings.

FIG. 1 shows a conventional bus line drive circuit.

1 is a clocked inverter that inputs the bus line, 2 is a clocked inverter that inputs the nox line 1, and 8 is a clocked inverter that outputs data to the no;
4 is a P-channel type MO transistor, TJ to TN- is an N-channel type MO8) transistor, 4 is a circuit block whose input is the output of the clocked inverter 2, and 5 is the input of the bus/line line node 8. This is a circuit block that provides In Figure 1, the Clocked Innocent is connected to the Nokusu line.

Although only two clocked inverters (2.8) are shown, it is common for general ICs to have two more clocked inverters connected.

N-channel transistor TN2. The switching of TN3 is controlled by the timing signal T2mT8, and the switching of the P-channel transistor TPhTP3 is controlled by the timing signal T2mT8.
Switching is controlled by zs"s<Tx+Ts inversion signal). This bus line method can reduce the wiring area within the IC because one signal line is time-divisionally driven. The capacitance added to the bus line increases because the signal line wiring length is long and a large number of input/output circuits are connected.Therefore, when driving the bus line at high speed, the clock drive shown in Figure 1.・I/No (
- In case 8, the channel width of the transistor must be increased by a certain p compared to the transistor in circuit block 4.5, and MO! 3) In transistors, P-channel transistors have lower carrier mobility than N-channel transistors, so in order to balance the transistor performance of P-channel and N-channel transistors, P-channel transistors are usually used.
rp3. 'rp, 8-channel width of N-channel transistor TN3jTN4
It is necessary to make it approximately twice the channel width of . From the above,
The size of the clocked inverter driving the bus line, especially the P-channel transistor, becomes very large. Furthermore, if the size of this clock drive/verter is large, the gate capacitance will also be large, so the transistor that drives it must also be large. Therefore circuit block 5
will inevitably become larger. Furthermore, many clocked inverters are connected to the bus line, which has the disadvantage of increasing the chip size.

In addition, if a large number of large-sized M100 transistors are connected to the bus line, their large drain capacitance will be added to the bus line, and the effect of increasing the size of the transistor is to drive at high speed. It also had the disadvantage of being smaller.

〔the purpose〕

The present invention is intended to solve these drawbacks, and its object is to provide a bus line drive circuit that can drive at a high speed of '25λ with a small IC area.

〔overview〕

The bus line drive circuit of the present invention includes a P-channel type MOB transistor whose switching is controlled by a timing signal between the bus line and the power supply, and outputs signals from the circuit block to the bus line using an N-channel type MOB transistor. It is characterized in that it is performed by a clocked Φ gate consisting only of transistors.

〔Example〕 Hereinafter, the present invention will be described in detail based on examples.

Figure 2 shows the button of the present invention. Since FIG. 2 corresponds to the embodiment shown in FIG. 1, corresponding parts are denoted by the same reference numerals. P-channel type MO8 installed between the bus line and the power supply
The transistor TPR is driven by a timing signal 〒1 (an inverted signal of T1) other than the timing signal T2+TI. In FIG. 8, the timing signal T1*T of FIG. 2 is shown.
2a The time chart of T3 is shown. The operation will be explained below based on FIGS. 2 and 8.

First, during the 11-level period t15- of the timing signal Tl, the P-channel MO8) transistor TPR is turned on, and the bus line 1 is charged to 11 levels. Next, if the output signal from the circuit block 5 (point A in FIG. 2) is 11 levels during the MIM level period t3 of the timing signal T3, then the N-channel M
O8 transistor TN4 turns on, and bus line 1 changes from 11 lvl to IQW level. Also, if the output signal from circuit block 5 is IQ level, then N
Since the channel type MO8) transistor TN4 is in the off state, the bus line 1 continues to be held at the Ill level that was pre-charged during the period t1. Then, in the lIW level period t11 of the timing signal T2, the N-channel type M
O8) Transistor TRI2. P-channel type MO8) transistor TP2 is turned on, and the data signal on the bus line determined in period t3 is transferred to circuit block 4 through all clocked inverters 2.

According to the present invention, instead of providing a P-channel type MτS transistor for pre-charging between the bus line and the power supply, the output from the circuit block to the bus line is provided using only an N-channel type MO8) transistor. A clocked gate may be used, eliminating the need for a P-channel type MO8) transistor. Among the many circuit blocks currently connected to the bus line, the circuit block that outputs signals to the bus line (corresponds to circuit block 5 in Figure 1)
The number of P-channel type M driving the bus line is n.
If the area occupied by a pattern of a 6B transistor is sp per circuit block, an area of %, 8P can be eliminated. Since the pattern area of the newly provided P-channel MO transistor for pre-charging is approximately sp, n, SP - EIP = (n-1), BP
This will contribute to reducing the chip area. Therefore, the chip size becomes smaller and the IC can be manufactured at a lower cost. In addition, the P-channel type MOEI) transistor becomes thinner when outputting a signal to the bus line, so the bus
The capacitance added to the line and the gate capacitance of the transistor driving the bus line are also reduced, allowing high-speed operation.

7- Also, FIG. 4 shows another embodiment according to the present invention. Second
Similar to the figure, since this embodiment corresponds to that of FIG. 1, the same reference numerals are given to corresponding parts. The timing signals are also the same as in FIG. 8, and the operation is the same as in FIG. 2. In this example, the bus
line into one N-channel type MO8) transistor TN5
The NOR gate circuit 6 is configured with the output timing signal Ts (inverted signal of Ta) from the circuit block 5, and the NOR gate circuit 6 is driven with the output of the NOR gate circuit 6.
"fr: Driving. If the transistors that drive the bus line are connected in series in multiple stages, it is necessary to increase the size of each transistor in proportion to the number of transistors connected in series. Fig. 4 If you configure a gate circuit with signals and timing signals from the circuit block and use one transistor to drive the bus line, the area required for the transistor to drive the bus line will be smaller than the area required to configure the gate circuit. Since the area of the IC is larger, the area of the IC as a whole decreases.

Although a clocked inverter is used in this embodiment, it is also possible to use a transmission gate.

〔effect〕

As described above, the present invention provides a P-channel type MO8) transistor for pre-charging on the bus line, and the output from the circuit block to the bus line is an N-channel type M'' transistor.
'5s), by using clocked gates using only transistors, the bus line drive circuit can be realized with a small chip area, making it possible to manufacture ICs at a lower cost. Furthermore, since the gate capacitance of the bus lines and the transistors that drive the bus lines is reduced, high-speed operation is possible, which is an excellent effect.

[Brief explanation of drawings]

FIG. 1 shows a conventional bus line drive circuit, FIG. 2 shows a bus line drive circuit showing an embodiment based on the present invention, and FIG. 8 shows a time chart of the timing signal T1*T2+Ta in FIG. 2. FIG. 4 is a bus line drive circuit showing another embodiment based on the present invention. 1...Bus line 2.8...Clocked inverter 4.5...Circuit block 6...NOR gate circuit TPR...P-channel MOS transistor for pre-charging and above Applicant: Suwa Seiko Co., Ltd. Figure 5 Procedural Amendment (Voluntary) 1. Display of the case Patent Application No. 95160 of 1982 2, Name of the invention Bus/Line Drive Circuit 3, Person making the amendment Relationship to the case Applicant Representative Director Tsuneya Nakamura 4, Agent Address: Kyobashi, Chuo-ku, Tokyo 104 2-6-21 The workpiece escaped due to machining stress, and the text "Basic" was deleted in its entirety.

Claims (2)

[Claims] (1) Bus line, a circuit block connected to the bus line via an N-channel output MOa+ and a transistor, and a circuit block connected via a clocked inverter that receives input signals from the bus line. and a switching element connected between the bus line and a power source and controlled by switching by a timing signal. (2) The bus line drive circuit according to claim 1, wherein the switch element is a P-channel type Mτ transistor.