JPS60237379A - Signal changes display - Google Patents

Abstract

PURPOSE:To display condition of changes in signals accurately without expansion of necessary display space by dividing a signal value train into sections of (n) signal values each to display the tendency of changes in signals at each section in terms of one character and signal. CONSTITUTION:As directed by an input unit 10, a central processing unit 20 reads the results of a logical simulation from a file unit 60 to be stored into a signal value train input area 41 on a random access memory 40. The central processing unit 20 fetches signal values for each display section from the signal value area 41. One display character and symbol are selected for each pattern of the signal values thus fetched according to a correspondence table 43 and stored sequentially into a display output area 42. The central processing unit 20 transfers character and symbol trains of the display output area 42 to display or print out.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a method for displaying signal changes in logic circuits, etc., and is particularly suitable for compressing one display space and displaying logic simulation results with high accuracy. This invention relates to a signal change display method.

Background of the Invention As logic circuits are increasingly integrated into LSIs, a method of verifying their logic operations using logic simulations has become established. In this case, verification of signal changes resulting from logical simulation has conventionally been carried out by sampling the simulation result signals at predetermined time intervals with a certain time width and displaying the signal values as they are. For this reason,
This method has the disadvantage that signal changes within a certain time interval are unknown, and even if there is a signal change that could be a clue to discovering a logic defect, it is overlooked. To overcome this problem, it is possible to shorten the sampling interval and output and display the signal value at each sampling point, but this has the disadvantage that it requires an enormous amount of space on the display surface and printing paper.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a signal change display method that can accurately output and display a signal change state without expanding the necessary display space when outputting and displaying logical simulation results and the like.

[Summary of the invention]

The present invention samples signals such as logic simulation results at minute intervals to obtain a signal value string of '188%lQ'', and divides the signal value string into a predetermined number of sections (hereinafter referred to as display sections). , for each interval, the 1″' included in it
, "o" signal pattern, a single character, symbol, etc. indicating the tendency of signal change in the section is used for output display.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail using the drawings.

FIG. 1 is a system configuration diagram of the present invention, which includes an input device 10, a processing device (CPU) 20, a ROM 30, a RAM/10, an output device 50, and a file device 60. The input device 10 consists of a keyboard or the like, and is used to input necessary operation instructions or data to the CPU 20. The output device 50 is a display device such as a CRT, a printer device, or the like, and outputs and displays signal changes resulting from the logic simulation using characters, symbols, and the like.

The ROM 30 stores various programs required for processing by the CPU 20. The RAM 40 is used to temporarily store processing data, etc., but as related to the present invention, the signal value insertion crab 9 file 411 display output cardia/1
2, and a correspondence table 43 between signal patterns and display characters/symbols within one display section. The file device 60 is used to previously store signal values that are the results of logic simulation.

Figure 2 shows signal A as a result of logic simulation.

This shows that B and C are sampled at partial time intervals Δt. Signal A obtained in this way.

FIG. 3 shows the signal values "o" or "1" of B and C arranged in the order of time t and 1°tl+. That is, the signal values of the logic simulation results are stored in advance in the file device 60 in the format shown in FIG. The CPU 20 reads a signal value string corresponding to, for example, the signal A based on instructions from the input device 10, etc., and, under the control of the program in the ROM 30, uses the correspondence table 43 in the RAM 40 for each display section to convert the signal pattern into one. Replace it with one character, symbol, etc., and output and display it on the output device [50].

FIG. 4 is a specific example of the correspondence table 43, and (a) shows the case where the signal value string is divided into 3 bits m or so to form one display section.
(b) shows the case where the data is divided into 4-bit units to form one display section.

Processing related to the present invention regarding the CPU 20 in FIG. 1 will be described in detail below. It is assumed that the signal value string is divided into three middle bits, and that the correspondence table shown in FIG. 4(a) is prepared in the RAM 40.

FIG. 5 shows an overview of the entire processing flow, in which the CPU 20 first performs a logic simulation '
The resulting signal value string, for example, signal A, is read from the file device 60 and stored in the signal value engraving canister 41 on the RAM 40 (step 101). FIG. 7(a) shows an example of a signal value string stored in the signal value area 41. Next, C
PU20 is shown in FIG. 7(a) as 401, 202, 203 .
As shown in . . . , signal values are sequentially cut out from the signal value area 41 of the RAM 40 in one display section, that is, three bits at a time (step 102). And this cut out 3
For each signal value pattern of bits, display characters and symbols corresponding to the pattern are selected according to the correspondence table 43 prepared in the RAM 40 (step 103), and sequentially stored in the display output canister 42 on the RAM 40 (step 103). 104). That is, signal value pattern 2 in FIG. 7(a)
Corresponding to 01, 202, 203, ..., RAM/1
The character/symbol 2 in Figure 7(b) is on the output canilia 42 above 0.
01', 202', 203', . . . are stored.

Display characters for the signal value string in the signal implantation canilia 41
When all symbol replacement is completed, the CPU 20
The character/symbol string in the display output 42 on the M40 is transferred to the output device 50 (step 105), and the output device 50 displays or prints out the character/symbol string (step 106).

FIG. 6 shows details of the processing of steps 102 to 104 in FIG. 5. First, in order to determine the end point of cutting out the signal value sequence, the final sampling time Te of the signal value sequence stored in the signal implantation canister 41 on the RAM 40 is determined.
is set in the desired register (step 110). Next, the desired counter C1 indicating the read pointer of the signal implantation canister 41 on the RAM 40 is initialized to O, and similarly the RA
A desired counter C/ indicating the write pointer of the display output canister 42 on the M/10 is initialized to O (step 11).
1). Next, it is checked whether the value of the counter CI exceeds Ta (step 1.12), and if it does not, the signal value for one display section, that is, 3 bits, is stored in the RAM 40 from the position indicated by the counter CI. The signal is read from the implanted canilia 41 (step 113). Next, this read 3
Check the signal values of the bits (step 114), and if the signal values are all the same, according to the correspondence table in FIG.
' is replaced with the character/symbol "1" and written in the position indicated by the counter C2 in the display output area 42 in the RAM 40 (step 115). If there is a difference in the 3-bit signal value, check the pattern (step 116), and similarly, according to the correspondence table in FIG. 4(a), "oto" is changed to the symbol "△" and "101" is is the symbol rVJ
, and the others are replaced with the symbol "*", and the RAM
/10 The display on the display 42 gets hot (step 1)
17°118.119). Next, add 3 to counter C0,
After incrementing the counter C2 by 1 (step 120).

Return to step 112, and if CI≦Te, step 1
The process from step 13 onward is repeated, and when C+ > Te, the process goes to step 105 in FIG.

According to this embodiment, the signal within one display section is 0]
”, “101”, the tendency of the change can be expressed with one symbol “△” or “”2
Signal changes such as logic simulation results can be accurately displayed without increasing the number of displayed characters and symbols.

Similarly, by using the correspondence table shown in FIG. 4(b), a 4-bit signal value can be represented by one character/symbol.

〔Effect of the invention〕

As described above, according to the present invention, the required space for logical simulation results and the like on one display screen and printout paper is increased. It can be displayed with high precision without the need to discover logic defects.

Analysis becomes easier.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a system configuration for achieving the method of the present invention, FIG. 2 is a diagram illustrating a method for generating a signal value sequence targeted by the present invention, and FIG. A diagram showing the contents of the file device, FIG. 4(a). (b) is a diagram showing a specific example of a correspondence table, Figures 5 and 6 are flow diagrams for explaining the operation of Figure 1, and Figures 7 (a) and (b) are shown as signal value sequences. FIG. 3 is a diagram showing an example of correspondence between character and symbol strings. 10...Input device, 20...Central processing unit I (CPU
), 3C1 ROM, 40-RAM, 50... output device, 60... file device. Figure 1 Figure 2 Figure 3, Figure 4 Figure 5 Figure 6, Figure 7

Claims (1)

[Claims] (1) A method of extracting a signal that takes a binary state of "O" or "1" at a predetermined interval and displaying the change in the signal. n
is an integer of 2 or more), and each division is replaced with one character/symbol indicating the tendency of the signal change.