JPH0696155A - Pattern generating system for logic circuit simulation - Google Patents

Abstract

PURPOSE:To improve efficiency for the simulation of a logic circuit by automatizing primary work in the generation of a pattern for simulation. CONSTITUTION:Operating procedure in the simulation is described on an operation description file 2 by operation description based on a descriptive method defined in advance. A fundamental timing condition for each operation in a logic circuit to be tested is described on a timing condition file 3. A pattern generator 1 for simulation generates the pattern 4 for simulation required for the simulation of the logic circuit to be tested basing on the operation description file 2 and the timing condition file 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides a simulation pattern of a logic circuit under test (a logic circuit to be tested by simulation) when a logic circuit is simulated (given to a logic circuit under test on a simulator). The present invention relates to a logic circuit simulation pattern generation method for generating a signal timing pattern group (see, for example, FIG. 5).

[0002]

2. Description of the Related Art Conventionally, in this kind of pattern generation method for logic circuit simulation, a circuit designer examines an operation procedure in a simulation of a logic circuit under test, and a simulation pattern based on the operation procedure is the hand of the circuit designer. It was generated by work. Here, the simulation pattern is complicated and requires accuracy.

[0003]

In the above-described conventional logic circuit simulation pattern generation method, the circuit designer manually generates the simulation pattern based on the operation procedure (in addition, the simulation to be generated). Since the usage pattern is complicated and requires accuracy, the man-hours for simulating the logic circuit increase due to the man-hours for generating the simulation pattern, which is caused by manual work during the simulation pattern. There is a problem that errors are easily mixed in, and the efficiency of logic circuit simulation is deteriorated.

This drawback becomes serious as the number of timing patterns required for simulation increases as the scale and complexity of the logic circuit under test increase.

In view of the above points, an object of the present invention is to enable the automation of the central work in the generation of the simulation pattern and to improve the efficiency of the logic circuit simulation. To provide.

[0006]

A pattern generation method for logic circuit simulation according to the present invention is a pattern generation method for logic circuit simulation, which generates a simulation pattern for a logic circuit under test when a logic circuit is simulated. A behavioral description file that describes an operational procedure in simulation by a behavioral description based on a predefined description method, a timing condition file that describes basic timing conditions for each operation in the logic circuit under test, the behavioral description file and the timing condition And a simulation pattern generator for generating a simulation pattern necessary for simulating a logic circuit under test based on the file.

[0007]

In the pattern generation method for logic circuit simulation of the present invention, the operation description file describes the operation procedure in the simulation by the operation description based on the previously described description method, and the timing condition file describes each operation in the logic circuit under test. The basic timing condition is described, and the simulation pattern generator generates a simulation pattern necessary for simulating the logic circuit under test based on the operation description file and the timing condition file.

[0008]

The present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a pattern generation system for logic circuit simulation according to the present invention. The logic circuit simulation pattern generation method of the present embodiment is configured to include a simulation pattern generator 1, a behavioral description file 2, a timing condition file 3, and a simulation pattern 4.

FIG. 2 is a diagram showing an example of the behavioral description file 2.

FIG. 3 is a diagram showing an example of the timing condition file 3.

FIG. 4 is a diagram (a diagram showing an example of a timing pattern) for explaining a mode of generation of the simulation pattern 4.

FIG. 5 is a diagram showing an example of the simulation pattern 4.

Next, the operation of the logic circuit simulation pattern generation system of the present embodiment thus constructed will be described.

When a certain logic circuit is simulated, an operation description file 2 and a timing condition file 3 relating to the logic circuit under test are prepared.

As shown in FIG. 2, the operation description file 2 describes the operation procedure in the simulation of the logic circuit under test by the operation description based on the previously described description method.

For example, in the operation description file 2 shown in FIG. 2, "IOW" (operation name indicating writing to the input / output device), "IOR" (operation name indicating reading from the input / output device) and "MEMW". An operation description having an operation name such as (operation name indicating writing to memory) is described.

As shown in FIG. 3, the timing condition file 3 includes, for each operation in the logic circuit under test, a signal name of a signal to be generated to realize the operation and a signal of each signal name. Information indicating what kind of signal value should be given at what timing (time number) is described. Here, the signal name, the value of the signal, and the number of times (for example, "@IOW in the timing condition file 3:
100 in the description “100” or “RW: 20
Information indicating that 20 or 40 in the description (Z), 40 (0), 40 (Z) "corresponds to the number of times (the unit is nanoseconds, for example) is called the basic timing condition. The timing condition file 3 describes basic timing conditions for each operation in the logic circuit under test.

The simulation pattern generator 1 generates a timing pattern corresponding to the operation description based on the basic timing condition in the timing condition file 3 for the operation of the operation name in each operation description in the operation description file 2. . Further, the timing patterns corresponding to all the behavioral descriptions in the behavioral description file 2 are organized (integrated) with respect to the signal names, and the simulation pattern 4 of the logic circuit under test is generated.

That is, the simulation pattern generator 1 performs the following processing based on the above-described operation description file 2 and timing condition file 3.

1. One behavioral description is extracted from the behavioral description file 2.

2. Referring to the timing condition file 3,
The basic timing conditions (the basic timing conditions in the timing condition file 3 for the operation with the operation name in the operation description) that match the operation description extracted from the operation description file 2 are extracted.

3. Based on the behavioral description extracted from the behavioral description file 2 and the basic timing conditions extracted from the timing condition file 3 as matching the behavioral description, a timing pattern (for example, refer to FIG. 4) related to the behavioral description is generated. .

4. The above-described processing (processing described in 1 to 3 above) is repeated for all the behavioral descriptions in the behavioral description file 2, and timing patterns are organized (integrated) for each signal name. 5) is generated.

Next, the specific operation of the logic circuit simulation pattern generation method of this embodiment will be described with reference to FIGS.

The behavioral description file 2 shown in FIG.
The behavioral description and so on are described. Here, for example, the behavioral description of “IOW 50H, 3012H”
Is an IO (Inp) called 50H (H is a hexadecimal number).
ut Output) 3 for input / output device of address
This means an operation of writing (WRITE. Writing) data (value) 012H.

The timing condition file 3 shown in FIG. 3 describes basic timing conditions (1) to (3) in FIG. 3 (basic timing conditions for each operation).

It should be noted that the behavioral descriptions 1 to 3 in FIG. 2 correspond to the basic timing conditions 1 to 3 in FIG. 3 (FIG. 2).
The basic timing condition for the operation indicated by the operation name "IOW" in the operation description in (1) corresponds to the basic timing condition in FIG. 3).

Here, for example, in the description "&IOA" in the basic timing condition in FIG. 3, the IO address (IO address "50H") in the operation description in FIG. 2 is substituted for the description "&IOA". It means what to do. Also, the description "&DATA" in the basic timing condition of is the description "&DATA".
Write target data ("3012
(Data “H”) should be substituted (the same applies to the description “& IOA” in the basic timing condition of “and the description“ & MEMA ”and“ & DATA ”in the basic timing condition of)).

Further, for example, in the description of "RW: 20 (Z), 40 (0), 40 (Z)" in the basic timing condition of "Z", "Z" is an indefinite value related to a binary value (0 or 1). It means a state.

The simulation pattern generator 1 performs the following processing based on the operation description file 2 and the timing condition file 3 as described above.

1. The timing condition file 3 for the operation of the operation name "IOW" is recognized by recognizing the operation name "IOW" in the operation description in the operation description file 2.
Medium basic timing conditions (basic timing conditions starting with "@IOW", that is, basic timing conditions)
Search for and take out.

2. IO address "50" in the behavior description of
After substituting "H" and the data "3012H" to be written into the descriptions "&IOW" and "&DATA" in the information indicating the basic timing conditions,
4 based on the behavioral description and the basic timing condition of FIG.
A timing pattern as shown in is generated.

3. Similar to the processes 1 and 2 described above, as for the other behavioral description (and the behavioral description thereof) in the behavioral description file 2 shown in FIG. Based on the basic timing conditions (and the basic timing conditions thereof) with respect to the above.

4. Some timing patterns generated as described above are integrated (arranged) with respect to signal names (signal names such as “A (31:00)” and “RW”), and FIG.
A simulation pattern 4 as shown in is generated. In the simulation pattern 4 shown in FIG. 5, for example, the signal name “A (31:00)” is 100 (50H), 100 (50H), and 80 (30).
(00H) etc., the information in each timing pattern is integrated, and the signal name “MIO” is 100
Information in each timing pattern of (1), 100 (1), and 80 (1) is integrated (the number of times in each information is added to generate information of 200 (1)).

Needless to say, the description method of the operation description file 2, the timing condition file 3 and the simulation pattern 4 is not limited to the description method shown in FIGS.

[0037]

As described above, according to the present invention, the simulation pattern can be generated only by describing the operation procedure based on the operation description in which the description method is defined in advance (the circuit in the generation of the simulation pattern is described. By reducing the manual work of the designer), the man-hours for simulating the logic circuit can be reduced, errors due to manual work are less likely to be mixed in the simulation pattern, and the simulation efficiency of the logic circuit can be reduced. There is an effect that it is possible to improve. The effect is that as the size and complexity of the logic circuit under test increases (the larger the simulation pattern),
It will be noticeable.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a behavioral description file in FIG.

FIG. 3 is a diagram showing an example of a timing condition file in FIG.

FIG. 4 is a diagram for explaining a mode of generation of a simulation pattern in FIG.

5 is a diagram showing an example of a simulation pattern in FIG.

[Explanation of symbols]

 1 Simulation pattern generator 2 Behavior description file 3 Timing condition file 4 Simulation pattern

Claims (1)

[Claims] 1. A logic circuit simulation pattern generation method for generating a simulation pattern of a logic circuit under test when a logic circuit is simulated, wherein an operation procedure in the simulation is performed by an operation description based on a description method defined in advance. A behavior description file to be described, a timing condition file that describes basic timing conditions for each operation in the logic circuit under test, and a simulation necessary for simulating the logic circuit under test based on the behavior description file and the timing condition file. A pattern generation method for logic circuit simulation, comprising: a simulation pattern generator for generating a pattern.