JPS60230249A - Storage protecting system - Google Patents

Abstract

PURPOSE:To execute a protection check as quickly as possible by making both a table buffer and a tag memory have a copy of a key of a key storage. CONSTITUTION:A computer has a buffer memory BS, a table buffer TLB, and a tag memory TM. A key for protecting a data is stored in advance not only in the table buffer TLB but also in the tag memory TM. When the table buffer TLB is non-bit at the time of an access in a real mode, the tag memory TM is brought to access, and in case it is hit and the key concerned is read out, the protection check is executed thereby.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a storage protection system for an electronic computer using a key.

Conventional technology and problems In calculators, a key (KEY) is attached to the stored data.
In order to protect stored data, a key is indicated when reading data, and if the key matches a key attached to the stored data, reading of the data is permitted.

In addition, in computers that use virtual memory, TLB (Table
When reading data, the TLB converts a logical address into a real address, and the real address is used to access the main storage. A computer having this TLB can also operate in real mode, in which case it is a logical address-real address, and the TLB is inactive for its original purpose.

In addition, the computer is equipped with a buffer storage (BS), so that when the main memory is accessed one after another, the read data is also stored in the BS, and when there is a subsequent read request for the same data,
Some systems use a system in which the data is supplied from the BS without accessing the main memory. In this case, a block fetch is performed to the main memory, the fetched block is stored in the BS, a tag (TAG) indicating the location on the main memory is attached to the block, and the tag is TA
The method is to store it in G memory. In this way, it is possible to determine whether the data is in the buffer storage BS by looking at the TAG memory.

The present invention relates to a computer that has such a buffer memory BS, table buffer TLB, and tag memory and performs storage protection. In such computers, it is common to add the key to the TLB. That is, key storage (KS)
When a real address corresponding to a logical address is stored in the TLB, a key for the real address is read from the KS and stored together with the key. However, in this conventional method, if the TLB is non-hit during memory access, the key storage KS must be accessed to obtain the key for the access address and key verification (protection check) must be performed. In logical mode, TL
If there is a B non-hit, direct address conversion processing such as retrieving the address conversion table in the main memory must be started, and since the KS is also accessed at this time, some processing is unavoidable, but in real mode, the desired data is stored in the buffer storage. This can be determined from the tag memory, so it should be possible to check the protection without accessing the key storage.

OBJECTS OF THE INVENTION The present invention focuses on these points and attempts to perform a protection check as quickly as possible.

Structure of the Invention The present invention provides a data protection key in a storage protection system for a computer equipped with a table buffer for logical/real address conversion, a buffer storage range for storing a copy of read main memory data, and its tag memory. It is stored not only in the table buffer but also in the tag memory, and when accessed in real remote mode, especially if the table buffer is non-hint, the tag memory is accessed, and if the key is hit and read, a protection check is performed. Next, this will be explained with reference to examples.

Embodiments of the invention The drawings show embodiments of the invention, TLB, KS, BS
are the aforementioned table buffer, key storage range, and buffer memory, and TM is the tag memory. A.R.
is the address register, CI, C2 is the comparator, Pc
t and PO2 are protection checkers, and 01 to G3 are gates. In the present invention, a key is also written in the tag memory TM, and a protection check circuit C using this key is written.
2. It differs from the conventional model in that G2°PO2 is provided.

When accessing memory in logical mode, a logical address is set in the address register AR, and part of it (the address part, the rest is data) is stored in the table buffer T.
Access LB and read real address RA. This real address RA passes through the gate G1 to access the tag memory TM, and although not shown, the real address serves as a memory access address to access the BS and the like. At this time, the key is also sent to the register KR, and compared with the key read from the TLB by the checker PCI, and if they match, a signal indicating access is outputted through the OR gate G3.

If the corresponding real address RA does not exist in the table buffer TLB, an address exception occurs and the process moves to DAT (direct address translation).

In real mode, a real address is set in address register AR. A part of the real address (address part) accesses the table buffer TLB and stores the real address R.
Read A and key KEY.

This real address RA is the same as the address set in register AR (if it exists in TLB),
Comparator C1 compares these and produces an output H indicating a match (hint), which activates checker Pct to perform the protection check described above. Although not shown, the real address R read from the TLB
A is the address for accessing the main memory, etc., and the main memory, etc. is accessed.

When the real address corresponding to the address (real address) set in the address register AR in real mode does not exist in the table buffer TLB, a match cannot be made on the conveyor C1, and in this case, a non-hint output NH is generated and the ant game) G2 is opened. .

Furthermore, in real mode, the gate G1 is switched to the address register AR side by the logic/real switching signal L/R, and the address (real address) input to the address register AR is input to the tag memory TM and comparator C2. . This causes the data at that address to be stored in the buffer.
If it is in range BS, its address RA and key KEY are read out from tag memory TM, and the former is read out from comparator C.
The latter is input to the second parity checker PC2. The real address RA read from the tag memory TM and the real address set in the address register AR should be equal, so the comparator C2 outputs the hint output H.
Since the AND gate G2 is open at this time, the checker PC2 is activated, and the key of the register KR and the key from the tag memory TM are compared by the checker PC2, and if they match, an access permission signal is sent to the OR gate. G3
is output through. If there is no corresponding address RA in the tag memory TM, a match cannot be achieved, and the comparator C2 produces a non-hit output NH. Further, if the checker PC 2 does not find a match, the access permission signal is not output, and the access is prohibited.

In this way, in the real mode, a protection check for an address that is not in the TLB but is in the tag memory TM can be executed without accessing the KS, and the protection check can be speeded up.

As described in detail, in the present invention, both the table buffer TLB and the tag memory TM have a copy of the key in the key storage KS, so that the protection check in the real mode can be performed even if the TLB is non-hit.
If given a hint, it is possible to perform a protection check on the keys in the TM, and it is possible to speed up the protection check.

[Brief explanation of the drawing]

The drawing is a block diagram showing an embodiment of the invention. In the figure, TLB is table buffer 1, BS is pan fast-
Range, TM is tag memory, and PCI is protection checker. Applicant Fujitsu Limited Representative Patent Attorney Minoru Aoyagi

Claims (1)

[Claims] In a storage protection system for a computer equipped with a table buffer for logical/real address conversion, a buffer storage for storing a copy of read main memory data, and its tag memory, the key for data protection is provided only in the table buffer. This memory protection method is characterized in that the key is stored in the tag memory as well, and when the table buffer is accessed in real mode, if the table buffer is non-hint, the tag memory is accessed, and when the key is hit and the key can be read, a protection check is performed accordingly. method.