JPH02254553A - Information processor - Google Patents

Abstract

PURPOSE:To prevent loss of address conversion information in an address conversion buffer by providing a protection key buffer used for memory access at the time of not designating the address conversion mode. CONSTITUTION:An address conversion buffer 20 is provided which adopts the virtual storage system and holds a part of an address conversion table, and a copy of protection key memory information is stored in this address conversion buffer, and the address conversion buffer 20 is used for table address conversion. A protection key buffer 14 is provided where a copy of a protection key memory 12 is held, and the protection key buffer 14 is used when the table address conversion mode is not designated, and the address conversion buffer 20 is used to access the memory when the table address conversion mode is designated. Thus, address conversion information is prevented from being lost in an address conversion buffer TLB when the address conversion mode is not designated.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an information processing device that employs a virtual storage method.

[Conventional technology]

Unexamined Japanese Patent Publication No. 1983 as an information processing device that adopted a virtual memory method
There is one shown in Japanese Patent No.-159287. This information processing device converts the virtual address given by the processing device into a real address using an address conversion table prepared in advance, and uses this real address to convert the virtual address given by the processing device into a main memory (MM).
). The address translation table is a table that associates virtual addresses with real addresses, and a register that holds a frequently used portion of this table is called an address translation buffer (TLB).

Furthermore, the main memory MM is provided with several bits of protection key data for each page as a protection key memory (YM) in order to check for memory protection violations. A copy of the protection key is kept and a memory protection violation check is performed at the same time as address conversion.

FIG. 2 shows a conventional information processing apparatus designed with the above considerations in mind. In the figure, (1) is an address translation buffer TLB having 256 entries;
DX is an index field for comparing virtual address bits 1 to 11, and T is an address translation buffer TL.
Whether the contents of each entry in B are used for address translation of virtual addresses (logical 1) or used only for protection key check without address translation of real addresses (logical 0).
), RA is the real address page field,
Y is a copy of the protection key in the protection key memory KYM corresponding to the real address page field RA, and ■ is a valid bit indicating that each entry in the address translation buffer TLB is valid. (2) indicates an address translation mode register that holds an address translation mode flag that controls whether or not to perform address translation for virtual addresses;
When this flag is logical 1, address translation is performed on the virtual address; when this flag is logical 0, address translation is not performed. (3) is the address translation buffer TLB (
1) the real page address register that holds the real page address corresponding to the virtual address to be written to the R^ field in (4) the address translation buffer TLB; indicates YW in the protection key write data register that holds the protection key data from.

Further, (5) indicates a virtual address register that holds a virtual address, PA indicates a page address portion of the virtual address, and BA indicates an address within the page of the virtual address.
6) indicates a protection key read data register KYR that holds protection key data read from the KY field of the address translation buffer TLB (1), and this protection key data detects a storage protection violation. (7) is the data read from the T field of the address translation buffer TLB (1) and the address translation mode flag register (2)
(8) is a comparator that checks for a match between the INDX field of the address translation buffer TLB (1) and bits 1 to 11 of the virtual address register (5). (9) is a TLB hit An AND gate is shown for detecting the condition of .

Furthermore, (10) indicates a selector that selects between the real page address register (3) and the virtual address register (5), and when the value of the address translation mode register (2) is logic 1, the real address page register (3) is selected. When it is logical 0, bits 1 to 19 of the virtual address register (5) are selected. (11) is the main memory MM, a physical address register to hold the real address for accessing YM to the protection key memory, (12) is the protection key memory with protection key data, and (13) is the main memory shows.

Next, the operation of each address translation mode will be explained.

[A] When address translation mode is specified A1; When a memory access request is generated from a program In this case, the virtual address of the request is set in the virtual address register (5). Virtual address translation (5)
Each field is read from address translation buffer TLB (1) by bits 12 to 19 of the address set in . Address translation buffer TLB (1) T
A match between the data read from the INDX field and the output of the address translation mode register (2) is detected by the comparator (7), and the data read from the INDX field and bits 1 to 11 of the virtual address register (5) are matched. a comparator (7) in which a match is detected by the comparator (8);
When the results of (8) are both logical 1 and the output data of the ■ field of address translation buffer TLB (1) is logical 1, the NO gate (9) causes T
LB hit is detected. At the same time, the protection key data read from the Y field of address translation buffer TLB (1) is set in register KYR, and a storage protection violation is detected. At this time, since there is no memory protection violation due to the TLB hit, the address translation buffer TLB
The real page address of the R^ field in (1) and bits 20 to 31 of the virtual address register (5) are set in the physical address register (11), and the main memory MM (1) is set in the physical address register (11).
3) Access.

A2 i When there is no corresponding address conversion information in the TLB, that is, when there is no TLB hit, the conversion information is read from the main memory MM (13) to the real page address register RAR (3) and selected by the selector (10). and written to the RA field of address translation buffer TLB (1). At the same time, the pending key data corresponding to the real page address is also stored in the protected key memory YM (1
2), is set to YW in the register (4), is written to the Y field in the address translation buffer TLB (1), and is further read out from the address translation mode register (
2) to address translation buffer TLB (1) T field, virtual address register (5) to address translation buffer TLB (1) INDX field, logic 1
is written to the V field of address translation buffer TLB (1), and writing of address translation information is completed. Thereafter, the process A1 described above is performed.

[B] When the address translation mode is not specified, that is, address translation is unnecessary, so the virtual address and real address match.

Bli TLB (1) is virtual address register (5)
When a copy of the protection key corresponding to the real address held in is held, the same process as process A1 is performed.

However, at this time, the logical value of the address translation mode register (2) is O, and the RA field of the address translation buffer TLB (1) is the same as bits 1 to 19 of the virtual address register (5).

B2; If the address translation buffer Tl, B (1) does not have a protection key corresponding to the real address of the virtual address register (5), that is, if there is no TLB hit, read the protection key data from YM (12) to the protection key memory. Set YW (4) in register and address translation buffer TL
B Write in the Y field in (1). At the same time, selector (10) bits 1 to 19 of the virtual address register.
and writes it into the R^ field of address translation register TLB (1). Further, from address translation mode register (2), address translation register TLB (1
), bits 1 to 11 of virtual address register (5) address translation register TLB. INDX field of (1), logic 1 indicates address translation register T
It is written to the ■ field of LB (1) and the process ends. After this, the process of B1 is performed.

[Problem to be solved by the invention]

As described above, in conventional information processing devices, the address translation buffer TLB is used both when an address translation mode is specified and when an address translation mode is not specified. The problem was that it was lost. Additionally, there is a problem in that performance is affected because memory access is usually required several times to generate address translation information.

On the other hand, in JP-A-63-206844 and JP-A-60-230249, a buffer with a copy of the main memory key is provided separately, and the target main memory key is obtained from the address translation buffer or key buffer. It is described that speeding up the processing is achieved by
Publication No. 249 states that in the real address mode, the address translation buffer is checked first, and if there is a non-hit, the key buffer is checked, but normally, the frequency of virtual address requests is much higher than that of real address requests, and There is a problem in that an address translation buffer entry set for a virtual address request may be lost due to a storage protection violation due to a real address request, resulting in a large loss.

This invention was made in order to solve the above-mentioned problems, and it is possible to prevent address translation information from being lost from the address translation buffer TLB when an address translation mode is not specified, and also prevent a memory protection violation caused by a key. You can reduce the address translation penalty by checking
An object of the present invention is to obtain an information processing device that can improve the hit rate of an address translation buffer TLB.

[Means to solve the problem]

An information processing device according to the present invention uses a virtual storage method,
An address translation buffer that holds a part of the address translation table is provided, a copy of the protection key memory information is also stored in the address translation buffer, and the information processing apparatus uses the address translation buffer for table address translation. A protected key buffer that holds a copy of the memory is provided, and if table address translation mode is not specified, the above protected key buffer is used, and if table address translation mode is specified, the above address translation buffer is used to copy the memory. It is something to access.

[Effect]

In this invention, the protection key buffer that holds a copy of the protection key memory is used for memory access when the address translation mode is not specified, so the address translation buffer TLB is not used at this time and the address translation buffer TLB is No address translation information is lost.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, the same reference numerals are used for the same or corresponding parts as those in the conventional example shown in FIG. 2, and the illustrations are omitted. (14) is the protection key buffer KYB with 256 entries, INDX is the index field for comparison with bits 1 to 11 of the virtual address register (5), and Y is the protection key of the real address to which the entry corresponds. The key field, which is a copy, is a valid bit field that indicates whether the entry is valid. (15) is the protection key buffer K
A comparator that checks whether the INDX field of YB (14) and bits 1 to 11 of the virtual address register (5) match, (16) is the protection key buffer) tY
B (14) INDX field and virtual address bits 1 to 11 matching condition and protection key buffer
ANfl gate that takes the AND condition that the V field of 141 is logical 1, (17) is the match condition of the INDX field of address translation buffer TLB (20) and bits 1 to 11 of the virtual address, and the address translation buffer TLB ( 20) shows an AND gate that takes the AND condition that the ■ field is logical 1.

Also, (1B) is the address translation buffer TLB (
20) R^ field and bits 1-1 of the virtual address
Selector 9 is selected by the output of address translation mode register (2), (19) is YB in the protection key buffer.
(14) MY field and address translation buffer T
Indicates a selector that selects the KY field of LB (20) according to the output of the address translation mode register, and (20
) is between the address translation buffer TLB (1) in FIG. 2, but shows the address translation buffer TLB in which the unnecessary T field is removed by having the protection key buffer KYB (14).

The present invention will be described in detail below with reference to the drawings.

[C] When address translation mode is specified This case is almost the same as the process [A] of the conventional example described above, the difference being that the T field does not need to be included in the address translation buffer TLB (20). , there is no need to detect a match between the address translation mode register (2) and the T field, and the protection key data read from the Y field in the address translation buffer TLB (20) is controlled by the output of the address translation mode register. This is the point selected by the selector (19).

[D] When address translation mode is not specified In this case, when a memory access request occurs, the virtual address of the request is set in the virtual address register (5). At this time, since address translation is not necessary, the address translation buffer TLB (20) is not used. Bit 12 of the address set in the virtual address register
~19 reads each field from YB (14) to the protected key buffer. Protection key buffer KYB
A match between the data read from the INFIX field (14) and bits 1 to 11 of the virtual address register (5) is detected by the comparator (15). This comparator (1
5) When the logical value of both the ■ field of YB (14) in the protected key buffer is 1, to NO gate (9)
XY8 human is detected.

At this time, MY of YB (14) is stored in the protection key buffer at the same time.
A copy of the protection key data read from the field is selected by the selector (19) and stored in the register YR (8
) to check for memory protection violations. Furthermore, bits 1 to 19 of the virtual address register are set to selector (1
8) and set in the physical address register (11), and then memory access is performed if there is no storage protection violation.

[E] If the protection key buffer KYB (14) does not have a protection key corresponding to the virtual address, that is, if YB is not hit, the protection key data corresponding to that address is stored in the protection key memory YM (12). Set the read register KYW (4) to the KY field of YB (14) in the protection key buffer, and write the protection key data to the KY field of YB (14) in the protection key buffer. At the same time, set bits 1 to 11 of the virtual address register (5) to the protection key buffer in YB (14). I of
Write to the NDX field and write a logic 1 to the V field of YB (14) in the protected key buffer. After this, the process [D] described above is performed.

Note that in the above embodiment, the address translation buffer TLB
Although the case in which the number of sets of protection key buffers KYB is one has been described, the same effect can be achieved even if the number of sets is plural.

(Effects of the Invention) As described above, according to the present invention, loss of address translation information in the address translation buffer TLB is prevented by providing a protection key buffer used during memory access when no address translation mode is specified. Since the address translation penalty associated with memory access can be minimized, the efficiency of memory access when address translation is not specified is not reduced, which is effective in improving performance. .

In addition, TLB entries generated for virtual address requests are not lost due to real address requests, which improves the TLB hit rate and reduces address translation penalties due to TLB misses. The headness of an address request is usually much higher than a real address request, and the TLB set for the virtual address request by the real address request
Losing an entry would be a big loss, but it has the effect of preventing such a loss.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an information processing apparatus according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional information processing apparatus. (1) and (20) are address translation buffer TLB
, (2) is the address translation mode register, (3) is the real page address register, (4) is the protection key write data register, (5) is the virtual address register, (6) is the protection key read data register, (7) , (8)
, (15) is a comparator, (9) is a three-man AND gate,
(10), (18), (19) are selectors,
(11) is a physical address register, (12) is a protection key memory YM, and (13) is a main memory memory MM. (14) is the protected key buffer KYB, (16),
(17) is a two-person AND gate. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] Using a virtual memory method, an address translation buffer is provided for holding a part of the address translation table, and a copy of the protection key memory information is also stored in this address translation buffer;
An information processing device that uses the above address conversion buffer for table address conversion is provided with a protected key buffer that holds a copy of the above protected key memory, and when the table address conversion mode is not specified, the above protected key buffer is used and the table address An information processing device characterized in that when a conversion mode is specified, memory access is performed using the address conversion buffer.