JPS60229334A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60229334A JPS60229334A JP59085589A JP8558984A JPS60229334A JP S60229334 A JPS60229334 A JP S60229334A JP 59085589 A JP59085589 A JP 59085589A JP 8558984 A JP8558984 A JP 8558984A JP S60229334 A JPS60229334 A JP S60229334A
- Authority
- JP
- Japan
- Prior art keywords
- mark
- alignment mark
- film
- alignment
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 28
- 238000002955 isolation Methods 0.000 claims abstract description 3
- 238000010894 electron beam technology Methods 0.000 claims description 8
- 230000001464 adherent effect Effects 0.000 abstract 3
- 230000008034 disappearance Effects 0.000 abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 13
- 239000000758 substrate Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000002313 adhesive film Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Electron Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
＋ａｌ 発明の技術分野
本発明は半導体装置の製造方法のうち、特に電子ビーム
露光法を用いて、半導体集積回路（ＩＣ）のパターンを
描画する場合に用いられる位置合わせマークの形成方法
に関する。Detailed Description of the Invention +al Technical Field of the Invention The present invention relates to an alignment mark used in a semiconductor device manufacturing method, particularly when drawing a pattern of a semiconductor integrated circuit (IC) using an electron beam exposure method. The present invention relates to a method of forming.
中） 従来技術と問題点
ＬＳＩ等のＩＣにおいては、高密度化、微細化が進んで
おり、リソグラフィ技術も従来の紫外線露光法に代って
、微細化に適した電子ビーム露光法が使用されるように
なってきた。(Middle) Conventional technology and problems ICs such as LSIs are becoming denser and smaller, and lithography technology is also using electron beam exposure, which is suitable for miniaturization, in place of the conventional ultraviolet exposure method. It's starting to happen.
このような電子ビーム露光法は、半導体ウェハー上でビ
ームを走査（スキャンニング）し、直接パターンを描画
する直接露光法であり、その場合に露光走査前の位置合
わせが必要になって、半導体ウェハー上には複数の位置
合わせマークが設けられ、そのマーク部分を電子ビーム
で走査し、その位置を認識し補正を行なった後に、所定
のパターン描画が行なわれている。This type of electron beam exposure method is a direct exposure method in which a beam is scanned on a semiconductor wafer to directly draw a pattern.In this case, alignment is required before exposure scanning, and the semiconductor wafer A plurality of alignment marks are provided on the top, and a predetermined pattern is drawn after the mark portions are scanned with an electron beam to recognize and correct their positions.
このような位置合わせマークは、マーク部分だけ異種材
料を被着する方式と、表面の凹凸を利用する方式とがあ
るが、前者は特別に異種材料を被着する工程が必要であ
るから工程が長（かかり、そのため専ら後者の凹凸を利
用する方式の位置合わせマークが使用されている。本発
明も、この凹凸状の位置合わせマークの形成方法に関す
るも、のである。There are two types of alignment marks: one is to apply a different material only to the mark part, and the other is to use the unevenness of the surface. However, the former requires a special process to apply the different material, so the process is slow. For this reason, the latter type of alignment mark that utilizes the unevenness is used exclusively.The present invention also relates to a method for forming the uneven alignment mark.
また、位置合わせマークには、半導体ウェハー全体の位
置合わせを行なうマークと、更にウェハー内のそれぞれ
のチップの位置合わせを行なうマークとがあるが、何れ
も同様形状のもので、第１図にウェハー全体の位置合わ
せマークの位置を例示している。図のように、ウェハー
全体の位置合わせマークは、ウェハーの左右２個所に相
対的に位置合わせマークｍが設けられる。In addition, alignment marks include marks for aligning the entire semiconductor wafer and marks for aligning individual chips within the wafer, but they all have the same shape, and the wafer The position of the overall alignment mark is illustrated. As shown in the figure, as the alignment marks for the entire wafer, alignment marks m are provided relatively to each other on the left and right sides of the wafer.
尚、このマーク位置検出法は、ビームで位置合わせマー
ク部分を走査し、その反射電子量を検出する方法で、凹
凸状マークのエツジにビームが当たると、反射電子検出
器で検出される反射電子の量が異なってくるから、それ
を検出してその位置をめ、ウェハーの位置補正を自動的
に行なうものである。This mark position detection method scans the alignment mark with a beam and detects the amount of backscattered electrons.When the beam hits the edge of the uneven mark, the backscattered electrons are detected by the backscattered electron detector. Since the amount of wafer differs, this is detected, the position is determined, and the position of the wafer is automatically corrected.
このマーク形状は、方形の凹部状にエツチングして形成
することが多く、第２図はその断面形状を示し、Ｅがエ
ツジ部分である。且つ、その平面形状はかぎ形等の他の
形状も用いられている。This mark shape is often formed by etching in the shape of a rectangular concave portion, and FIG. 2 shows its cross-sectional shape, and E indicates the edge portion. In addition, other shapes such as a hook shape are also used as the planar shape.
ところが、ＩＣを製造する際には、半導体基板上に被着
膜を被覆する工程があり、その時には折角設けた位置合
わせマークが消失することが起こる。例えば、第３図に
示すように製造の初期に誘電体からなる素子分離帯を形
成する工程で、半導体基板ｌに（Ｊ ｓｎをエツチング
して形成し、その上に減圧化学気相成長（ＣＶＤ）法で
多結晶シリコンｙ！２を被着する工程がある。その場合
に、Ｕ溝ｎと同時に位置合わせマークｍを形成しても、
多結晶シリコン１１１２が位置合わせマークｍを埋没さ
せて、マークが消失することが生じる。その時には、再
び次工程のための位置合わせマークをもう一度形成して
おり、このような再度のマーク形成工程はそれだけ製作
工程が多くかかることになる。However, when manufacturing an IC, there is a step of coating a semiconductor substrate with an adhesive film, and at that time, the alignment marks that have been painstakingly provided may disappear. For example, as shown in FIG. 3, in the process of forming device isolation bands made of dielectric material in the early stage of manufacturing, (Jsn) is formed on the semiconductor substrate l by etching, and then low pressure chemical vapor deposition (CVD) is formed on the semiconductor substrate l. ) method to deposit polycrystalline silicon y!2.In that case, even if the alignment mark m is formed at the same time as the U groove n,
The polycrystalline silicon 1112 buries the alignment mark m, causing the mark to disappear. At that time, alignment marks for the next process are formed again, and such a process of forming marks again requires a correspondingly large number of manufacturing steps.
ｆｃｌ 発明の目的
本発明は、このような位置合わせマークの消失を防止し
、マーク形成工程の繰り返しをなくするための電子ビー
ム露光用位置合わせマークの形成方法を提案するもので
ある。fcl OBJECT OF THE INVENTION The present invention proposes a method for forming alignment marks for electron beam exposure to prevent such alignment marks from disappearing and to eliminate repetition of the mark forming process.
Ｔｄｌ 発明の構成
その目的は、凹形状に形成した位置合わせマークの一遍
の長さを、少なくとも被着膜の膜厚の２倍よりも大きく
した電子ビーム露光用位置合わせマークを、素子分離帯
と同時に形成するようにした半導体装置の製造方法によ
って達成される。Tdl Structure of the Invention The object of the invention is to use an alignment mark for electron beam exposure, in which the length of the alignment mark formed in a concave shape is at least twice the thickness of the deposited film, to be used as an element separation band. This is achieved by a method of manufacturing semiconductor devices in which they are formed simultaneously.
（ｅｌ 発明の実施例 以下、実施例を参照して詳細に説明する。(el Embodiments of the invention Hereinafter, a detailed description will be given with reference to examples.
第４図は従来の位置合わせマークｍが消失する理由を説
明するための工程途中の断面図である。FIG. 4 is a sectional view in the middle of a process for explaining the reason why the conventional alignment mark m disappears.
図は、半導体基板１に窒化シリコン膜３を選択的に形成
し、Ｕｆｉｎおよび位置合わせマークｍをエツチングし
て、次に二酸化シリコン膜４を生成した後、減圧ＣＶＤ
法により多結晶シリコンＩＩ！２を被着した工程である
。この時、減圧ＣＶＤ法はカバレージが極めて良いから
、孔内の側面にも多結晶シリコンｙＩ２が被着して、例
えばり＃ｎの幅を２μｍ、方形の位置合わせマークｍの
一遍の長さを４μｍとし、膜厚２μｍの多結晶シリコン
膜を成長すると、第４図のように側面からも多結晶シリ
コン膜が成長して、大きな孔の位置合わせマークｍをも
丁度埋没させる。従って、表面上の多結晶シリコン膜を
ボリフシュして除去しても、第３図のように位置合わせ
マークｍが埋没されて消失することになる。The figure shows that a silicon nitride film 3 is selectively formed on a semiconductor substrate 1, Ufin and alignment marks m are etched, a silicon dioxide film 4 is formed, and then a low pressure CVD film is formed.
Polycrystalline silicon II by method! This is the process of applying 2. At this time, since the low pressure CVD method has extremely good coverage, the polycrystalline silicon yI2 is also deposited on the side surfaces of the hole, and for example, the width of #n is 2 μm and the length of the rectangular alignment mark m is When a polycrystalline silicon film with a thickness of 4 μm and a film thickness of 2 μm is grown, the polycrystalline silicon film also grows from the side surfaces as shown in FIG. 4, and just buries the alignment mark m of the large hole. Therefore, even if the polycrystalline silicon film on the surface is removed by polishing, the alignment mark m will be buried and disappear as shown in FIG.
そのため、本発明では方形の位置合わせマークの一遍の
長さを、被着膜の膜厚の２倍よりも大きくした位置合わ
せマークを形成するもので、そうすると埋没は回避でき
る。第５図は本発明にかかる実施例の工程途中の断面図
を示しており、例えば、Ｕ溝ｎの幅を２μｍ、方形の位
置合わせマークＭの一遍の長さを６μｍとして、膜厚２
μｍの多結晶シリコン膜を成長するとする。そうすると
、減圧ＣＶＤ法によって位置合わせマークの凹部孔内に
、孔側面から多結晶シリコン膜２が成長しても、中心部
分に凹部を残存させることができる。Therefore, in the present invention, a rectangular alignment mark is formed in which the length of each mark is greater than twice the thickness of the deposited film, thereby avoiding embedding. FIG. 5 shows a cross-sectional view in the middle of the process of the embodiment according to the present invention. For example, if the width of the U groove n is 2 μm and the length of each rectangular alignment mark M is 6 μm,
Suppose that a polycrystalline silicon film of μm thickness is grown. In this way, even if the polycrystalline silicon film 2 grows from the side surfaces of the recessed hole of the alignment mark by low-pressure CVD, the recessed portion can remain in the center portion.
従って、第６図に示すように表面上の余分の多結晶シリ
コン膜をボリフシュして除去すると、エツジＥを有する
位置合わせマークＭが形成され、マーク位置を認識する
ことができる。尚、この時、多結晶シリコン膜を被着し
たために、エツジＥの位置がずれて両エツジ間の間隔が
狭くなるが、位置合わせマークの位置は反射電子量の多
いエツジＥの位置をめ、両方のエツジ間の中点を計算す
る方法であるから、多結晶シリコン膜被着による位置ず
れは影響しない。Therefore, when the excess polycrystalline silicon film on the surface is removed by polishing as shown in FIG. 6, an alignment mark M having an edge E is formed, and the mark position can be recognized. At this time, since the polycrystalline silicon film is deposited, the position of edge E shifts and the distance between the two edges narrows, but the position of the alignment mark is set at the position of edge E with a large amount of reflected electrons. Since this method calculates the midpoint between both edges, positional deviation due to the deposition of the polycrystalline silicon film does not affect this method.
このようすれば、Ｕ溝からなる素子分離帯と位置合ねゼ
マークが同時に形成され、その形成工程が簡単化される
。In this way, the element separation band consisting of the U-groove and the alignment mark are formed at the same time, and the formation process is simplified.
（ｆｌ 発明の効果
以上の説明から明らかなように、本発明によれば電子ビ
ーム露光法における位置合わせマークを形成するための
工程を設ける必要がなく、製造工程の短縮に顕著に寄与
するものである。(fl Effects of the Invention As is clear from the above explanation, the present invention eliminates the need to provide a process for forming alignment marks in electron beam exposure, which significantly contributes to shortening the manufacturing process. be.
第１図はウェハー上の位置合わせマークを示す図、第２
図は位置合わせマークの断面図例、第３図は従来のマー
クの断面図、第４図はその形成工程途中の断面図、第５
図は本発明にかかる形成工程途中の断面図、第６図は本
発明にかかる形成方法で作成されたマークの断面図であ
る。
図中、ｎはＵ溝１ｍは従来の位置合わせマーク。
Ｍは本発明にかかる位置合わせマーク、１は半導体基板
、２は多結晶シリコン膜、３は窒化シリコン膜、４は二
酸化シリコン躾を示している。
第１図
ｆｓ２１１１１
第３１］３Figure 1 shows the alignment marks on the wafer, Figure 2 shows the alignment marks on the wafer.
The figure shows an example of a cross-sectional view of an alignment mark, Figure 3 is a cross-sectional view of a conventional mark, Figure 4 is a cross-sectional view during the formation process, and Figure 5
The figure is a cross-sectional view in the middle of the forming process according to the present invention, and FIG. 6 is a cross-sectional view of a mark created by the forming method according to the present invention. In the figure, n is the U groove 1m is the conventional alignment mark. M is an alignment mark according to the present invention, 1 is a semiconductor substrate, 2 is a polycrystalline silicon film, 3 is a silicon nitride film, and 4 is a silicon dioxide layer. Figure 1 fs21111 No. 31] 3
Claims (1)
なくとも被着膜の膜厚の２倍よりも大きくした電子ビー
ム露光用位置合わせマークを、素子分離帯と同時に形成
するようにしたことを特徴とする半導体装置の製造方法
。The alignment mark for electron beam exposure, in which the length of the alignment mark formed in a concave shape is at least twice the thickness of the deposited film, is formed at the same time as the element isolation band. A method for manufacturing a featured semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59085589A JPS60229334A (en) | 1984-04-26 | 1984-04-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59085589A JPS60229334A (en) | 1984-04-26 | 1984-04-26 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60229334A true JPS60229334A (en) | 1985-11-14 |
Family
ID=13862998
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59085589A Pending JPS60229334A (en) | 1984-04-26 | 1984-04-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60229334A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5482893A (en) * | 1990-06-29 | 1996-01-09 | Canon Kabushiki Kaisha | Method for producing semiconductor device having alignment mark |
| KR100802221B1 (en) | 2005-12-30 | 2008-02-11 | 주식회사 하이닉스반도체 | Method for forming semiconductor device |
| KR100842494B1 (en) | 2007-06-25 | 2008-07-01 | 주식회사 동부하이텍 | Method for shaping alignment key of a semiconductor device |
| US7485543B2 (en) | 2005-12-30 | 2009-02-03 | Hynix Semiconductor Inc. | Method for manufacturing semiconductor device with overlay vernier |
| US11984406B2 (en) | 2020-03-30 | 2024-05-14 | Changxin Memory Technologies, Inc. | Semiconductor structure and method for manufacturing same |
-
1984
- 1984-04-26 JP JP59085589A patent/JPS60229334A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5482893A (en) * | 1990-06-29 | 1996-01-09 | Canon Kabushiki Kaisha | Method for producing semiconductor device having alignment mark |
| US5663099A (en) * | 1990-06-29 | 1997-09-02 | Canon Kabushiki Kaisha | Method for producing semiconductor device having alignment mark |
| KR100802221B1 (en) | 2005-12-30 | 2008-02-11 | 주식회사 하이닉스반도체 | Method for forming semiconductor device |
| US7485543B2 (en) | 2005-12-30 | 2009-02-03 | Hynix Semiconductor Inc. | Method for manufacturing semiconductor device with overlay vernier |
| KR100842494B1 (en) | 2007-06-25 | 2008-07-01 | 주식회사 동부하이텍 | Method for shaping alignment key of a semiconductor device |
| US11984406B2 (en) | 2020-03-30 | 2024-05-14 | Changxin Memory Technologies, Inc. | Semiconductor structure and method for manufacturing same |
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