CN114823448A - Method for forming alignment mark in semiconductor process - Google Patents
Method for forming alignment mark in semiconductor process Download PDFInfo
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- CN114823448A CN114823448A CN202110107393.6A CN202110107393A CN114823448A CN 114823448 A CN114823448 A CN 114823448A CN 202110107393 A CN202110107393 A CN 202110107393A CN 114823448 A CN114823448 A CN 114823448A
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Abstract
The invention provides a method for forming an alignment mark in a semiconductor process, which is characterized in that an epitaxial layer and/or a polycrystalline silicon layer are filled in a device region and an alignment region after grooves are formed by etching simultaneously, and a dielectric layer is filled in the grooves of the alignment region to be used as the alignment mark, so that the attenuation or disappearance of an alignment signal caused by a planarization process after epitaxy can be avoided, and the alignment error is not influenced because an additional photoetching step is not required; after the back of the substrate is thinned, the bottom of the dielectric layer serving as the alignment mark is exposed on the back of the substrate or is close to the back of the substrate, an alignment signal is clear when a back process is carried out, and the influence of substrate distortion caused by the thinning process is small; the appearance of the alignment mark is not influenced by the thickness of the epitaxial layer, the alignment precision is high, and the process reliability is improved.
Description
Technical Field
The invention relates to a method for forming an alignment mark in a semiconductor process.
Background
In a conventional semiconductor process, an alignment mark (e.g., a separate alignment mark or an alignment mark pattern in an active area mask) for photolithography is formed on a substrate surface as an initial step, and then other steps are performed. However, for cis (cmos image sensor) or other processes requiring epitaxy before formation of the active region, the shallow alignment mark may be affected by the planarization process after epitaxy is completed, so that the alignment signal may be attenuated or disappear.
In order to solve the alignment problem in the semiconductor process of epitaxy before the formation of an active region, a shallow trench can be formed in an alignment region and a dielectric layer is filled as an alignment mark, a deep trench is formed in a device region and is subjected to epitaxy, and then the active region is formed in an epitaxial layer; and because the alignment mark is far away from the back surface of the substrate, an alignment signal is weak when a back surface process is carried out, and the method cannot be applied to a semiconductor process needing back surface processing, such as a back-illuminated image sensor process.
Disclosure of Invention
The invention aims to provide a method for forming an alignment mark in a semiconductor process, which can avoid the attenuation or disappearance of an alignment signal caused by a planarization process after epitaxy, can not increase the alignment error, can ensure that the alignment signal is clear during a back process, and can improve the process reliability.
Based on the above consideration, the present invention provides a method for forming an alignment mark in a semiconductor process, comprising: providing a semiconductor substrate, and defining a device region and an alignment region; simultaneously etching the device region and the alignment region to form a groove respectively; filling a dielectric layer in the groove of the alignment area as an alignment mark; and forming a semiconductor device in the device region.
Preferably, the step of filling the trench in the alignment region with a dielectric layer as the alignment mark includes: forming a first epitaxial layer in the trenches of the device region and the alignment region respectively, wherein when the trenches of the device region are filled with the first epitaxial layer, the trenches of the alignment region are not filled with the first epitaxial layer; and filling a dielectric layer in the groove of the alignment area as an alignment mark.
Preferably, the step of filling the trench in the alignment region with a dielectric layer as the alignment mark further includes: a second epitaxial layer is formed in the device region and the alignment region, respectively.
Preferably, the step of filling the trench in the alignment region with a dielectric layer as the alignment mark includes: forming a first dielectric layer and a polysilicon layer in the trenches of the device region and the alignment region respectively, wherein when the trenches of the device region are filled with the polysilicon layer, the trenches of the alignment region are not filled with the polysilicon layer; and filling a second dielectric layer in the groove of the alignment area to be used as an alignment mark.
Preferably, the step of filling the trench in the alignment region with a dielectric layer as the alignment mark includes: forming a first dielectric layer and a polysilicon layer in the trenches of the device region and the alignment region respectively; removing the polysilicon layer in the groove of the alignment region; and filling a second dielectric layer in the groove of the alignment region, wherein the first dielectric layer and the second dielectric layer are jointly used as alignment marks.
Preferably, the step of forming the first dielectric layer in the trenches of the device region and the alignment region further comprises: a first epitaxial layer is formed in the trenches of the device region and the alignment region.
Preferably, after the step of filling the second dielectric layer in the trench of the alignment region, the method further includes: a second epitaxial layer is formed in the device region and the alignment region, respectively.
Preferably, the trench width of the alignment region is 0.2 to 5 microns greater than the trench width of the device region.
Preferably, the grooves of the alignment region are in the shape of elongated strips having a width not exceeding 8 microns.
Preferably, the material of the dielectric layer includes at least one or a combination of silicon oxide, silicon oxynitride and silicon nitride.
Preferably, the forming process of the dielectric layer includes at least one or a combination of chemical vapor deposition, physical vapor deposition and atomic layer deposition.
Preferably, the step of filling the trench in the alignment region with a dielectric layer as the alignment mark further includes: the device region and the alignment region are planarized by chemical mechanical polishing.
Preferably, the method for forming the alignment mark is applied to a back-illuminated image sensor process.
Preferably, the depth of the trench of the alignment region is 1.5 to 5 micrometers.
According to the method for forming the alignment mark in the semiconductor process, the epitaxial layer and/or the polycrystalline silicon layer are/is refilled after the device region and the alignment region are etched to form the groove at the same time, and the medium layer is filled in the groove of the alignment region to serve as the alignment mark, so that the attenuation or disappearance of an alignment signal caused by the planarization process after the epitaxy can be avoided, and the alignment error is not influenced because the additional photoetching step is not needed; after the back of the substrate is thinned, the bottom of the dielectric layer serving as the alignment mark is exposed on the back of the substrate or is close to the back of the substrate, an alignment signal is clear when a back process is carried out, and the influence of substrate distortion caused by the thinning process is small; and the appearance of the alignment mark is not influenced by the thickness of the epitaxial layer, the alignment precision is high, and the process reliability is improved.
Drawings
Other features, objects and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments thereof, which proceeds with reference to the accompanying drawings.
FIG. 1 is a flow chart of a method for forming an alignment mark in a semiconductor process according to the present invention;
fig. 2-7 are schematic process diagrams illustrating a method for forming an alignment mark in a semiconductor process according to a first embodiment of the invention;
fig. 8-13 are schematic process diagrams illustrating a method for forming an alignment mark in a semiconductor process according to a second embodiment of the invention;
fig. 14-19 are schematic process diagrams illustrating a method for forming an alignment mark in a semiconductor process according to a third embodiment of the invention.
In the drawings, like or similar reference numbers indicate like or similar devices (modules) or steps throughout the different views.
Detailed Description
In order to solve the problems in the prior art, the invention provides a method for forming an alignment mark in a semiconductor process, wherein an epitaxial layer and/or a polycrystalline silicon layer are/is refilled after a device region and an alignment region are etched to form a groove at the same time, and a dielectric layer is filled in the groove of the alignment region to be used as the alignment mark, so that the attenuation or disappearance of an alignment signal caused by a planarization process after the epitaxy can be avoided, and the alignment error is not influenced because an additional photoetching step is not required; after the back of the substrate is thinned, the bottom of the dielectric layer serving as the alignment mark is exposed on the back of the substrate or is close to the back of the substrate, so that an alignment signal is clear when a back process is carried out, and the influence of substrate distortion caused by the thinning process is small; and the appearance of the alignment mark is not influenced by the thickness of the epitaxial layer, the alignment precision is high, and the process reliability is improved.
In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof. The accompanying drawings illustrate, by way of example, specific embodiments in which the invention may be practiced. The illustrated embodiments are not intended to be exhaustive of all embodiments according to the invention. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
Fig. 1 shows a flow chart of a method for forming an alignment mark in a semiconductor process of the invention, which comprises the following steps: providing a semiconductor substrate, and defining a device region and an alignment region; simultaneously etching the device region and the alignment region to form grooves; filling a dielectric layer in the groove of the alignment area as an alignment mark; and forming a semiconductor device in the device region.
The present invention will be described in detail with reference to specific examples.
Example one
Fig. 2-9 illustrate a preferred embodiment of a method for forming an alignment mark in a semiconductor process according to the present invention.
As shown in fig. 2, a semiconductor substrate 100 is provided, a device region 100A and an alignment region 100B (separated by a dotted line) are defined, and trenches 102 are etched simultaneously in the device region 100A and the alignment region 100B, respectively, using a hard mask 101. Preferably, the material of the hard mask 101 includes at least one or a combination of silicon oxide, silicon oxynitride and silicon nitride.
As shown in fig. 3 and 4, a first epitaxial layer 103 is formed in the trenches 102 of the device region 100A and the alignment region 100B, and the first epitaxial layer 103 and the hard mask 101 are sequentially planarized by chemical mechanical polishing, stopping on the surface of the semiconductor substrate 100.
Preferably, the width WB of the trench 102 of the alignment region 100B is 0.2 to 5 microns larger than the width WA of the trench 102 of the device region 100A, so that the trench 102 of the alignment region 100B is not filled with the first epitaxial layer 103 when the trench 102 of the device region 100A is filled with the first epitaxial layer 103.
As shown in fig. 5 and 6, a dielectric layer 108 is formed in the device region 100A and the alignment region 100B, and the dielectric layer 108 is planarized by chemical mechanical polishing, stopping on the surface of the semiconductor substrate 100, and the dielectric layer 108 filled in the trench 102 in the alignment region 100B is used as an alignment mark.
Preferably, the material of the dielectric layer 108 includes at least one or a combination of silicon oxide, silicon oxynitride and silicon nitride, and the forming process of the dielectric layer 108 includes at least one or a combination of chemical vapor deposition, physical vapor deposition and atomic layer deposition.
Preferably, the trench 102 in the alignment region 100B is in the shape of an elongated strip, and the width WB is not more than 8 μm, so as to avoid that a large deep trench easily causes more photoresist residues at the bottom of the trench and is thrown out during spin coating, so as to form a photoresist tail, which affects the process accuracy, and thus affects the alignment signal accuracy.
According to the process requirements, as further shown in fig. 7, after the dielectric layer 108 is formed, the second epitaxial layer 105 is formed in the device region 100A and the alignment region 100B, respectively, and in a subsequent step, not shown, the semiconductor device is formed in the second epitaxial layer 105 in the device region 100A.
In this embodiment, by using the dielectric layer 108 filled in the trench 102 of the alignment region 100B as an alignment mark, it is possible to avoid attenuation or disappearance of an alignment signal due to a planarization process after epitaxy, and since no additional photolithography step is required, alignment errors are not affected; and the appearance of the alignment mark is not influenced by the thickness of the second epitaxial layer 105, the alignment precision is high, and the process reliability is improved.
In addition, the method for forming the alignment mark of the present embodiment may be applied to a semiconductor process that requires a backside processing, for example, a backside illumination image sensor process, preferably, the depth H of the trench 102 in the alignment region 100B is 1.5 to 5 micrometers, after the backside of the substrate 100 is thinned, the bottom of the dielectric layer 108 serving as the alignment mark is exposed at the backside of the substrate 100 or is closer to the backside of the substrate 100, an alignment signal is clear when the backside process is performed, and an influence of substrate distortion caused by the thinning process is small.
Example two
Fig. 8-13 illustrate another preferred embodiment of the method for forming alignment marks in a semiconductor process according to the present invention.
As shown in fig. 8, a semiconductor substrate 200 is provided, a device region 200A and an alignment region 200B (separated by a dotted line) are defined, and trenches 202 are simultaneously etched in the device region 200A and the alignment region 200B, respectively, using a hard mask 201. Preferably, the material of the hard mask 201 includes at least one or a combination of silicon oxide, silicon oxynitride and silicon nitride.
As shown in fig. 9 and 10, a first dielectric layer 206 and a polysilicon layer 207 are sequentially formed in the trenches 202 of the device region 200A and the alignment region 200B, respectively, and the polysilicon layer 207 and the hard mask 201 are sequentially planarized by chemical mechanical polishing, stopping on the surface of the semiconductor substrate 200. A first epitaxial layer (not shown) may also be formed prior to forming the first dielectric layer 206 in the trenches 202 of the device region 200A and the alignment region 200B, depending on process requirements.
Preferably, the width WB of the trench 202 of the alignment area 200B is 0.2 to 5 micrometers greater than the width WA of the trench 202 of the device area 200A, so that when the trench 202 of the device area 200A is filled with the polysilicon layer 207, the trench 202 of the alignment area 200B is not filled with the polysilicon layer 207.
As shown in fig. 11 and 12, a second dielectric layer 208 is formed in the device region 200A and the alignment region 200B, and the second dielectric layer 208 is planarized by chemical mechanical polishing, stopping on the surface of the semiconductor substrate 200, and the second dielectric layer 208 filled in the trench 202 of the alignment region 200B is used as an alignment mark.
Preferably, the material of the first dielectric layer 206 and the second dielectric layer 208 includes at least one or a combination of silicon oxide, silicon oxynitride, and silicon nitride, and the forming process of the first dielectric layer 206 and the second dielectric layer 208 includes at least one or a combination of chemical vapor deposition, physical vapor deposition, and atomic layer deposition.
Preferably, the trench 202 of the alignment region 200B is in the shape of an elongated bar, and the width WB is not more than 8 μm, so as to avoid that a large deep trench easily causes more photoresist residues at the bottom of the trench and is thrown out during spin coating, so as to form a photoresist tail, which affects the process accuracy, and thus affects the alignment signal accuracy.
According to the process requirements, as further shown in fig. 13, after forming the second dielectric layer 208, a second epitaxial layer 205 is formed in the device region 200A and the alignment region 200B, respectively, and in a subsequent step, not shown, a semiconductor device is formed in the second epitaxial layer 205 in the device region 200A.
In this embodiment, by using the second dielectric layer 208 filled in the trench 202 of the alignment region 200B as an alignment mark, it is possible to avoid attenuation or disappearance of an alignment signal due to a planarization process after epitaxy, and since an additional photolithography step is not required, alignment errors are not affected; and the appearance of the alignment mark is not influenced by the thickness of the second epitaxial layer 205, the alignment precision is high, and the process reliability is improved.
In addition, the method for forming the alignment mark of the present embodiment may be applied to a semiconductor process that requires a backside processing, for example, a backside illumination image sensor process, preferably, the depth H of the trench 202 of the alignment region 200B is 1.5 micrometers to 5 micrometers, after the backside of the substrate 200 is thinned, the bottom of the second dielectric layer 208 serving as the alignment mark is exposed at the backside of the substrate 200 or is closer to the backside of the substrate 200, an alignment signal is clear when the backside process is performed, and the influence of substrate distortion caused by the thinning process is small.
EXAMPLE III
Fig. 14-19 illustrate another preferred embodiment of the method for forming an alignment mark in a semiconductor process according to the present invention.
As shown in fig. 14, a semiconductor substrate 300 is provided, a device region 300A and an alignment region 300B (separated by a dotted line) are defined, and trenches 302 are simultaneously etched in the device region 300A and the alignment region 300B, respectively, using a hard mask 301. Preferably, the material of the hard mask 301 includes at least one or a combination of silicon oxide, silicon oxynitride, and silicon nitride.
As shown in fig. 15 and 16, a first dielectric layer 306 and a polysilicon layer 307 are sequentially formed in the trenches 302 of the device region 300A and the alignment region 300B, respectively, and then the polysilicon layer 307 in the trenches 302 of the alignment region 300B and the polysilicon layer 307 above the trenches 302 of the device region 300A are removed. A first epitaxial layer (not shown) may also be formed prior to forming the first dielectric layer 306 in the trenches 302 of the device region 300A and the alignment region 300B, depending on process requirements.
Preferably, trench 302 width WB of alignment region 300B is 0.2 microns to 5 microns greater than trench 302 width WA of device region 300A, so that when trench 302 of device region 300A is filled with polysilicon layer 307, trench 302 of alignment region 300B is not filled with polysilicon layer 307.
As shown in fig. 17 and fig. 18, a second dielectric layer 308 is formed in the device region 300A and the alignment region 300B, and the second dielectric layer 308 and the hard mask 301 are planarized by chemical mechanical polishing, stopping on the surface of the semiconductor substrate 300, and using the first dielectric layer 306 and the second dielectric layer 308 filled in the trench 302 of the alignment region 300B as an alignment mark.
Preferably, the material of the first dielectric layer 306 and the second dielectric layer 308 includes at least one or a combination of silicon oxide, silicon oxynitride, and silicon nitride, and the forming process of the first dielectric layer 306 and the second dielectric layer 308 includes at least one or a combination of chemical vapor deposition, physical vapor deposition, and atomic layer deposition.
Preferably, the trench 302 of the alignment region 300B is in the shape of an elongated bar, and the width WB is not more than 8 μm, so as to avoid that a large deep trench easily causes more photoresist residues at the bottom of the trench and is thrown out during spin coating, so as to form a photoresist tail, which affects the process accuracy, and thus affects the alignment signal accuracy.
According to the process requirements, as further shown in fig. 19, after forming the second dielectric layer 308, a second epitaxial layer 305 is formed in the device region 300A and the alignment region 300B, respectively, and in a subsequent step, not shown, a semiconductor device is formed in the second epitaxial layer 305 in the device region 300A.
In this embodiment, the first dielectric layer 306 and the second dielectric layer 308 filled in the trench 302 of the alignment region 300B are used together as an alignment mark, so that the alignment signal can be prevented from being attenuated or disappearing in the planarization process after epitaxy, and no additional photolithography step is required, and alignment error is not affected; and the appearance of the alignment mark is not influenced by the thickness of the second epitaxial layer 305, so that the alignment precision is high, and the process reliability is improved.
In addition, the method for forming the alignment mark of the present embodiment may be applied to a semiconductor process that requires a backside processing, for example, a backside illumination image sensor process, preferably, the depth H of the trench 302 of the alignment region 300B is 1.5 to 5 micrometers, after the backside of the substrate 300 is thinned, the bottoms of the first dielectric layer 306 and the second dielectric layer 308 serving as the alignment mark are exposed at the backside of the substrate 300 or are closer to the backside of the substrate 300, an alignment signal is clear when the backside process is performed, and the influence of substrate distortion caused by the thinning process is small.
In summary, according to the method for forming the alignment mark in the semiconductor process, the epitaxial layer and/or the polysilicon layer are/is refilled after the device region and the alignment region are etched to form the trench, and the dielectric layer is filled in the trench of the alignment region to serve as the alignment mark, so that the attenuation or disappearance of an alignment signal caused by a planarization process after epitaxy can be avoided, and the alignment error is not influenced because an additional photolithography step is not required; after the back of the substrate is thinned, the bottom of the dielectric layer serving as the alignment mark is exposed on the back of the substrate or is close to the back of the substrate, an alignment signal is clear when a back process is carried out, and the influence of substrate distortion caused by the thinning process is small; and the appearance of the alignment mark is not influenced by the thickness of the epitaxial layer, the alignment precision is high, and the process reliability is improved.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive. Furthermore, it will be obvious that the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. Several elements recited in the apparatus claims may also be embodied by one element. The terms first, second, etc. are used to denote names, but not any particular order.
Claims (14)
1. A method for forming an alignment mark in a semiconductor process is characterized by comprising the following steps:
providing a semiconductor substrate, and defining a device region and an alignment region;
simultaneously etching the device region and the alignment region to form a groove respectively;
filling a dielectric layer in the groove of the alignment area as an alignment mark;
and forming a semiconductor device in the device region.
2. The method of claim 1, wherein the step of filling a dielectric layer in the trench of the alignment region as the alignment mark comprises: forming a first epitaxial layer in the trenches of the device region and the alignment region respectively, wherein when the trenches of the device region are filled with the first epitaxial layer, the trenches of the alignment region are not filled with the first epitaxial layer; and filling a dielectric layer in the groove of the alignment area to be used as an alignment mark.
3. The method as claimed in claim 2, wherein the step of filling the trench in the alignment region with a dielectric layer as the alignment mark further comprises: a second epitaxial layer is formed in the device region and the alignment region, respectively.
4. The method of claim 1, wherein the step of filling a dielectric layer in the trench of the alignment region as the alignment mark comprises: forming a first dielectric layer and a polysilicon layer in the trenches of the device region and the alignment region respectively, wherein when the trenches of the device region are filled with the polysilicon layer, the trenches of the alignment region are not filled with the polysilicon layer; and filling a second dielectric layer in the groove of the alignment area to be used as an alignment mark.
5. The method of claim 1, wherein the step of filling a dielectric layer in the trench of the alignment region as the alignment mark comprises: forming a first dielectric layer and a polysilicon layer in the trenches of the device region and the alignment region respectively; removing the polysilicon layer in the groove of the alignment region; and filling a second dielectric layer in the groove of the alignment region, wherein the first dielectric layer and the second dielectric layer are jointly used as alignment marks.
6. The method as claimed in claim 4 or 5, wherein the step of forming the first dielectric layer in the trenches of the device region and the alignment region further comprises: a first epitaxial layer is formed in the trenches of the device region and the alignment region.
7. The method as claimed in claim 4 or 5, wherein the step of filling the second dielectric layer in the trench of the alignment region further comprises: a second epitaxial layer is formed in the device region and the alignment region, respectively.
8. The method of claim 1, wherein the trench width of the alignment region is 0.2 to 5 microns greater than the trench width of the device region.
9. The method of claim 1, wherein the trench in the alignment region has a shape of an elongated strip having a width of no more than 8 μm.
10. The method as claimed in claim 1, wherein the dielectric layer comprises at least one or a combination of silicon oxide, silicon oxynitride, and silicon nitride.
11. The method as claimed in claim 1, wherein the dielectric layer is formed by at least one of chemical vapor deposition, physical vapor deposition, and atomic layer deposition.
12. The method of claim 1, wherein the step of filling a dielectric layer in the trench of the alignment region as the alignment mark further comprises: the device region and the alignment region are planarized by chemical mechanical polishing.
13. The method of claim 1, wherein the method is applied to a backside illuminated image sensor process.
14. The method of claim 13, wherein the trench of the alignment region has a depth of 1.5 to 5 μm.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117012761A (en) * | 2023-08-04 | 2023-11-07 | 荣芯半导体(淮安)有限公司 | Semiconductor structure and forming method thereof |
| CN117174574A (en) * | 2023-11-03 | 2023-12-05 | 合肥晶合集成电路股份有限公司 | Method for preparing semiconductor structure and semiconductor structure |
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2021
- 2021-01-27 CN CN202110107393.6A patent/CN114823448A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117012761A (en) * | 2023-08-04 | 2023-11-07 | 荣芯半导体(淮安)有限公司 | Semiconductor structure and forming method thereof |
| CN117174574A (en) * | 2023-11-03 | 2023-12-05 | 合肥晶合集成电路股份有限公司 | Method for preparing semiconductor structure and semiconductor structure |
| CN117174574B (en) * | 2023-11-03 | 2024-02-09 | 合肥晶合集成电路股份有限公司 | Method for preparing semiconductor structure and semiconductor structure |
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